2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/timer.h>
28 #include <linux/platform_device.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-event.h>
31 #include <media/v4l2-ioctl.h>
32 #include <media/v4l2-mem2mem.h>
33 #include <media/videobuf2-dma-sg.h>
34 #include <media/videobuf2-v4l2.h>
39 static void job_abort(void *prv)
41 struct rga_ctx *ctx = prv;
42 struct rockchip_rga *rga = ctx->rga;
44 if (!rga->curr) /* No job currently running */
47 wait_event_timeout(rga->irq_queue,
48 !rga->curr, msecs_to_jiffies(RGA_TIMEOUT));
51 static void device_run(void *prv)
53 struct rga_ctx *ctx = prv;
54 struct rockchip_rga *rga = ctx->rga;
55 struct vb2_buffer *src, *dst;
58 spin_lock_irqsave(&rga->ctrl_lock, flags);
62 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
63 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
72 spin_unlock_irqrestore(&rga->ctrl_lock, flags);
75 static irqreturn_t rga_isr(int irq, void *prv)
77 struct rockchip_rga *rga = prv;
80 intr = rga_read(rga, RGA_INT) & 0xf;
82 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
85 struct vb2_v4l2_buffer *src, *dst;
86 struct rga_ctx *ctx = rga->curr;
92 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
93 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
98 dst->timecode = src->timecode;
99 dst->timestamp = src->timestamp;
100 dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
101 dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
103 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
104 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
105 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
107 wake_up(&rga->irq_queue);
113 static struct v4l2_m2m_ops rga_m2m_ops = {
114 .device_run = device_run,
115 .job_abort = job_abort,
119 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
121 struct rga_ctx *ctx = priv;
124 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
125 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
126 src_vq->drv_priv = ctx;
127 src_vq->ops = &rga_qops;
128 src_vq->mem_ops = &vb2_dma_sg_memops;
129 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
130 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
131 src_vq->lock = &ctx->rga->mutex;
133 ret = vb2_queue_init(src_vq);
137 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
138 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
139 dst_vq->drv_priv = ctx;
140 dst_vq->ops = &rga_qops;
141 dst_vq->mem_ops = &vb2_dma_sg_memops;
142 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
143 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
144 dst_vq->lock = &ctx->rga->mutex;
146 return vb2_queue_init(dst_vq);
149 static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
151 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
155 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
157 case V4L2_CID_PORTER_DUFF_MODE:
161 ctx->hflip = ctrl->val;
164 ctx->vflip = ctrl->val;
166 case V4L2_CID_ROTATE:
167 ctx->rotate = ctrl->val;
169 case V4L2_CID_BG_COLOR:
170 ctx->fill_color = ctrl->val;
173 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
177 static const struct v4l2_ctrl_ops rga_ctrl_ops = {
178 .s_ctrl = rga_s_ctrl,
181 static int rga_setup_ctrls(struct rga_ctx *ctx)
183 struct rockchip_rga *rga = ctx->rga;
185 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 5);
187 v4l2_ctrl_new_std_menu(&ctx->ctrl_handler, &rga_ctrl_ops,
188 V4L2_CID_PORTER_DUFF_MODE,
189 V4L2_PORTER_DUFF_CLEAR, 0,
190 V4L2_PORTER_DUFF_SRC);
192 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
193 V4L2_CID_HFLIP, 0, 1, 1, 0);
195 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
196 V4L2_CID_VFLIP, 0, 1, 1, 0);
198 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
199 V4L2_CID_ROTATE, 0, 270, 90, 0);
201 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
202 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
204 if (ctx->ctrl_handler.error) {
205 int err = ctx->ctrl_handler.error;
207 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
208 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
215 struct rga_fmt formats[] = {
217 .fourcc = V4L2_PIX_FMT_ARGB32,
218 .color_swap = RGA_COLOR_RB_SWAP,
219 .hw_format = RGA_COLOR_FMT_ABGR8888,
226 .fourcc = V4L2_PIX_FMT_XRGB32,
227 .color_swap = RGA_COLOR_RB_SWAP,
228 .hw_format = RGA_COLOR_FMT_XBGR8888,
235 .fourcc = V4L2_PIX_FMT_ABGR32,
236 .color_swap = RGA_COLOR_ALPHA_SWAP,
237 .hw_format = RGA_COLOR_FMT_ABGR8888,
244 .fourcc = V4L2_PIX_FMT_XBGR32,
245 .color_swap = RGA_COLOR_ALPHA_SWAP,
246 .hw_format = RGA_COLOR_FMT_XBGR8888,
253 .fourcc = V4L2_PIX_FMT_RGB24,
254 .color_swap = RGA_COLOR_RB_SWAP,
255 .hw_format = RGA_COLOR_FMT_BGR888,
262 .fourcc = V4L2_PIX_FMT_ARGB444,
263 .color_swap = RGA_COLOR_RB_SWAP,
264 .hw_format = RGA_COLOR_FMT_ABGR4444,
271 .fourcc = V4L2_PIX_FMT_ARGB555,
272 .color_swap = RGA_COLOR_RB_SWAP,
273 .hw_format = RGA_COLOR_FMT_ABGR1555,
280 .fourcc = V4L2_PIX_FMT_RGB565,
281 .color_swap = RGA_COLOR_RB_SWAP,
282 .hw_format = RGA_COLOR_FMT_BGR565,
289 .fourcc = V4L2_PIX_FMT_NV21,
290 .color_swap = RGA_COLOR_UV_SWAP,
291 .hw_format = RGA_COLOR_FMT_YUV420SP,
298 .fourcc = V4L2_PIX_FMT_NV61,
299 .color_swap = RGA_COLOR_UV_SWAP,
300 .hw_format = RGA_COLOR_FMT_YUV422SP,
307 .fourcc = V4L2_PIX_FMT_NV12,
308 .color_swap = RGA_COLOR_NONE_SWAP,
309 .hw_format = RGA_COLOR_FMT_YUV420SP,
316 .fourcc = V4L2_PIX_FMT_NV16,
317 .color_swap = RGA_COLOR_NONE_SWAP,
318 .hw_format = RGA_COLOR_FMT_YUV422SP,
325 .fourcc = V4L2_PIX_FMT_YUV420,
326 .color_swap = RGA_COLOR_NONE_SWAP,
327 .hw_format = RGA_COLOR_FMT_YUV420P,
334 .fourcc = V4L2_PIX_FMT_YUV422P,
335 .color_swap = RGA_COLOR_NONE_SWAP,
336 .hw_format = RGA_COLOR_FMT_YUV422P,
343 .fourcc = V4L2_PIX_FMT_YVU420,
344 .color_swap = RGA_COLOR_UV_SWAP,
345 .hw_format = RGA_COLOR_FMT_YUV420P,
353 #define NUM_FORMATS ARRAY_SIZE(formats)
355 struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
359 for (i = 0; i < NUM_FORMATS; i++) {
360 if (formats[i].fourcc == f->fmt.pix.pixelformat)
366 static struct rga_frame def_frame = {
367 .width = DEFAULT_WIDTH,
368 .height = DEFAULT_HEIGHT,
369 .colorspace = V4L2_COLORSPACE_DEFAULT,
372 .crop.width = DEFAULT_WIDTH,
373 .crop.height = DEFAULT_HEIGHT,
377 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
380 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
382 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
385 return ERR_PTR(-EINVAL);
389 static int rga_open(struct file *file)
391 struct rockchip_rga *rga = video_drvdata(file);
392 struct rga_ctx *ctx = NULL;
395 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
399 /* Set default formats */
401 ctx->out = def_frame;
403 if (mutex_lock_interruptible(&rga->mutex)) {
407 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
408 if (IS_ERR(ctx->fh.m2m_ctx)) {
409 ret = PTR_ERR(ctx->fh.m2m_ctx);
410 mutex_unlock(&rga->mutex);
414 v4l2_fh_init(&ctx->fh, video_devdata(file));
415 file->private_data = &ctx->fh;
416 v4l2_fh_add(&ctx->fh);
418 rga_setup_ctrls(ctx);
420 /* Write the default values to the ctx struct */
421 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
423 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
424 mutex_unlock(&rga->mutex);
429 static int rga_release(struct file *file)
431 struct rga_ctx *ctx =
432 container_of(file->private_data, struct rga_ctx, fh);
433 struct rockchip_rga *rga = ctx->rga;
435 mutex_lock(&rga->mutex);
437 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
439 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
440 v4l2_fh_del(&ctx->fh);
441 v4l2_fh_exit(&ctx->fh);
444 mutex_unlock(&rga->mutex);
449 static const struct v4l2_file_operations rga_fops = {
450 .owner = THIS_MODULE,
452 .release = rga_release,
453 .poll = v4l2_m2m_fop_poll,
454 .unlocked_ioctl = video_ioctl2,
455 .mmap = v4l2_m2m_fop_mmap,
459 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
461 strlcpy(cap->driver, RGA_NAME, sizeof(cap->driver));
462 strlcpy(cap->card, "rockchip rga", sizeof(cap->card));
463 strlcpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
465 cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
466 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
471 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
475 if (f->index >= NUM_FORMATS)
478 fmt = &formats[f->index];
479 f->pixelformat = fmt->fourcc;
484 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
486 struct rga_ctx *ctx = prv;
487 struct vb2_queue *vq;
488 struct rga_frame *frm;
490 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
493 frm = rga_get_frame(ctx, f->type);
497 f->fmt.pix.width = frm->width;
498 f->fmt.pix.height = frm->height;
499 f->fmt.pix.field = V4L2_FIELD_NONE;
500 f->fmt.pix.pixelformat = frm->fmt->fourcc;
501 f->fmt.pix.bytesperline = frm->stride;
502 f->fmt.pix.sizeimage = frm->size;
503 f->fmt.pix.colorspace = frm->colorspace;
508 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
512 fmt = rga_fmt_find(f);
515 f->fmt.pix.pixelformat = fmt->fourcc;
518 f->fmt.pix.field = V4L2_FIELD_NONE;
520 if (f->fmt.pix.width > MAX_WIDTH)
521 f->fmt.pix.width = MAX_WIDTH;
522 if (f->fmt.pix.height > MAX_HEIGHT)
523 f->fmt.pix.height = MAX_HEIGHT;
525 if (f->fmt.pix.width < MIN_WIDTH)
526 f->fmt.pix.width = MIN_WIDTH;
527 if (f->fmt.pix.height < MIN_HEIGHT)
528 f->fmt.pix.height = MIN_HEIGHT;
530 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
531 f->fmt.pix.bytesperline = f->fmt.pix.width;
533 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
535 f->fmt.pix.sizeimage =
536 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
541 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
543 struct rga_ctx *ctx = prv;
544 struct rockchip_rga *rga = ctx->rga;
545 struct vb2_queue *vq;
546 struct rga_frame *frm;
550 /* Adjust all values accordingly to the hardware capabilities
553 ret = vidioc_try_fmt(file, prv, f);
556 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
557 if (vb2_is_busy(vq)) {
558 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
561 frm = rga_get_frame(ctx, f->type);
564 fmt = rga_fmt_find(f);
567 frm->width = f->fmt.pix.width;
568 frm->height = f->fmt.pix.height;
569 frm->size = f->fmt.pix.sizeimage;
571 frm->stride = f->fmt.pix.bytesperline;
572 frm->colorspace = f->fmt.pix.colorspace;
574 /* Reset crop settings */
577 frm->crop.width = frm->width;
578 frm->crop.height = frm->height;
584 vidioc_try_crop(struct rga_ctx *ctx, struct v4l2_selection *s)
586 struct rockchip_rga *rga = ctx->rga;
589 f = rga_get_frame(ctx, s->type);
594 case V4L2_SEL_TGT_COMPOSE:
596 * COMPOSE target is only valid for capture buffer type, return
597 * error for output buffer type
599 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
602 case V4L2_SEL_TGT_CROP:
604 * CROP target is only valid for output buffer type, return
605 * error for capture buffer type
607 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
611 * bound and default crop/compose targets are invalid targets to
618 if (s->r.top < 0 || s->r.left < 0) {
619 v4l2_err(&rga->v4l2_dev,
620 "doesn't support negative values for top & left.\n");
624 if (s->r.left + s->r.width > s->r.width ||
625 s->r.top + s->r.height > s->r.height ||
626 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
627 v4l2_err(&rga->v4l2_dev, "unsupport crop value.\n");
634 static int vidioc_g_selection(struct file *file, void *prv,
635 struct v4l2_selection *s)
637 struct rga_ctx *ctx = prv;
639 bool use_frame = false;
641 f = rga_get_frame(ctx, s->type);
646 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
647 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
648 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
651 case V4L2_SEL_TGT_CROP_BOUNDS:
652 case V4L2_SEL_TGT_CROP_DEFAULT:
653 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
656 case V4L2_SEL_TGT_COMPOSE:
657 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
661 case V4L2_SEL_TGT_CROP:
662 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
675 s->r.width = f->width;
676 s->r.height = f->height;
682 static int vidioc_s_selection(struct file *file, void *prv,
683 struct v4l2_selection *s)
685 struct rga_ctx *ctx = prv;
689 ret = vidioc_try_crop(ctx, s);
693 f = rga_get_frame(ctx, s->type);
702 static const struct v4l2_ioctl_ops rga_ioctl_ops = {
703 .vidioc_querycap = vidioc_querycap,
705 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
706 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
707 .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
708 .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
710 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
711 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
712 .vidioc_try_fmt_vid_out = vidioc_try_fmt,
713 .vidioc_s_fmt_vid_out = vidioc_s_fmt,
715 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
716 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
717 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
718 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
719 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
720 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
721 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
723 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
724 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
726 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
727 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
729 .vidioc_g_selection = vidioc_g_selection,
730 .vidioc_s_selection = vidioc_s_selection,
733 static struct video_device rga_videodev = {
734 .name = "rockchip-rga",
736 .ioctl_ops = &rga_ioctl_ops,
738 .release = video_device_release,
739 .vfl_dir = VFL_DIR_M2M,
742 static int rga_enable_clocks(struct rockchip_rga *rga)
746 ret = clk_prepare_enable(rga->sclk);
748 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
752 ret = clk_prepare_enable(rga->aclk);
754 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
755 goto err_disable_sclk;
758 ret = clk_prepare_enable(rga->hclk);
760 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
761 goto err_disable_aclk;
767 clk_disable_unprepare(rga->sclk);
769 clk_disable_unprepare(rga->aclk);
774 static void rga_disable_clocks(struct rockchip_rga *rga)
776 clk_disable_unprepare(rga->sclk);
777 clk_disable_unprepare(rga->hclk);
778 clk_disable_unprepare(rga->aclk);
781 static int rga_parse_dt(struct rockchip_rga *rga)
783 struct reset_control *core_rst, *axi_rst, *ahb_rst;
785 core_rst = devm_reset_control_get(rga->dev, "core");
786 if (IS_ERR(core_rst)) {
787 dev_err(rga->dev, "failed to get core reset controller\n");
788 return PTR_ERR(core_rst);
791 axi_rst = devm_reset_control_get(rga->dev, "axi");
792 if (IS_ERR(axi_rst)) {
793 dev_err(rga->dev, "failed to get axi reset controller\n");
794 return PTR_ERR(axi_rst);
797 ahb_rst = devm_reset_control_get(rga->dev, "ahb");
798 if (IS_ERR(ahb_rst)) {
799 dev_err(rga->dev, "failed to get ahb reset controller\n");
800 return PTR_ERR(ahb_rst);
803 reset_control_assert(core_rst);
805 reset_control_deassert(core_rst);
807 reset_control_assert(axi_rst);
809 reset_control_deassert(axi_rst);
811 reset_control_assert(ahb_rst);
813 reset_control_deassert(ahb_rst);
815 rga->sclk = devm_clk_get(rga->dev, "sclk");
816 if (IS_ERR(rga->sclk)) {
817 dev_err(rga->dev, "failed to get sclk clock\n");
818 return PTR_ERR(rga->sclk);
821 rga->aclk = devm_clk_get(rga->dev, "aclk");
822 if (IS_ERR(rga->aclk)) {
823 dev_err(rga->dev, "failed to get aclk clock\n");
824 return PTR_ERR(rga->aclk);
827 rga->hclk = devm_clk_get(rga->dev, "hclk");
828 if (IS_ERR(rga->hclk)) {
829 dev_err(rga->dev, "failed to get hclk clock\n");
830 return PTR_ERR(rga->hclk);
836 static int rga_probe(struct platform_device *pdev)
838 struct dma_attrs cmdlist_dma_attrs;
839 struct rockchip_rga *rga;
840 struct video_device *vfd;
841 struct resource *res;
845 if (!pdev->dev.of_node)
848 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
852 rga->dev = &pdev->dev;
853 spin_lock_init(&rga->ctrl_lock);
854 mutex_init(&rga->mutex);
856 init_waitqueue_head(&rga->irq_queue);
858 ret = rga_parse_dt(rga);
860 dev_err(&pdev->dev, "Unable to parse OF data\n");
862 pm_runtime_enable(rga->dev);
864 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
866 rga->regs = devm_ioremap_resource(rga->dev, res);
867 if (IS_ERR(rga->regs)) {
868 ret = PTR_ERR(rga->regs);
872 irq = platform_get_irq(pdev, 0);
874 dev_err(rga->dev, "failed to get irq\n");
879 ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
880 dev_name(rga->dev), rga);
882 dev_err(rga->dev, "failed to request irq\n");
886 rga->alloc_ctx = vb2_dma_sg_init_ctx(&pdev->dev);
888 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
891 vfd = video_device_alloc();
893 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
898 vfd->lock = &rga->mutex;
899 vfd->v4l2_dev = &rga->v4l2_dev;
901 video_set_drvdata(vfd, rga);
902 snprintf(vfd->name, sizeof(vfd->name), "%s", rga_videodev.name);
905 platform_set_drvdata(pdev, rga);
906 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
907 if (IS_ERR(rga->m2m_dev)) {
908 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
909 ret = PTR_ERR(rga->m2m_dev);
910 goto unreg_video_dev;
913 pm_runtime_get_sync(rga->dev);
915 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
916 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
918 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
919 rga->version.major, rga->version.minor);
921 pm_runtime_put(rga->dev);
923 /* Create CMD buffer */
924 init_dma_attrs(&cmdlist_dma_attrs);
925 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &cmdlist_dma_attrs);
926 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
927 &rga->cmdbuf_phy, GFP_KERNEL,
931 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
933 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
935 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
936 def_frame.size = def_frame.stride * def_frame.height;
938 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
940 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
943 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
944 vfd->name, video_device_node_name(vfd));
949 video_device_release(vfd);
951 video_unregister_device(rga->vfd);
953 v4l2_device_unregister(&rga->v4l2_dev);
955 pm_runtime_disable(rga->dev);
960 static int rga_remove(struct platform_device *pdev)
962 struct rockchip_rga *rga = platform_get_drvdata(pdev);
963 DEFINE_DMA_ATTRS(attrs);
965 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, &rga->cmdbuf_virt,
966 rga->cmdbuf_phy, &attrs);
968 free_pages((unsigned long)rga->src_mmu_pages, 3);
969 free_pages((unsigned long)rga->dst_mmu_pages, 3);
971 v4l2_info(&rga->v4l2_dev, "Removing\n");
973 v4l2_m2m_release(rga->m2m_dev);
974 video_unregister_device(rga->vfd);
975 v4l2_device_unregister(&rga->v4l2_dev);
976 vb2_dma_sg_cleanup_ctx(rga->alloc_ctx);
978 pm_runtime_disable(rga->dev);
984 static int rga_runtime_suspend(struct device *dev)
986 struct rockchip_rga *rga = dev_get_drvdata(dev);
988 rga_disable_clocks(rga);
993 static int rga_runtime_resume(struct device *dev)
995 struct rockchip_rga *rga = dev_get_drvdata(dev);
997 return rga_enable_clocks(rga);
1001 static const struct dev_pm_ops rga_pm = {
1002 SET_RUNTIME_PM_OPS(rga_runtime_suspend,
1003 rga_runtime_resume, NULL)
1006 static const struct of_device_id rockchip_rga_match[] = {
1008 .compatible = "rockchip,rk3288-rga",
1011 .compatible = "rockchip,rk3399-rga",
1016 MODULE_DEVICE_TABLE(of, rockchip_rga_match);
1018 static struct platform_driver rga_pdrv = {
1020 .remove = rga_remove,
1024 .of_match_table = rockchip_rga_match,
1028 module_platform_driver(rga_pdrv);
1030 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
1031 MODULE_DESCRIPTION("Rockchip Raster 2d Grapphic Acceleration Unit");
1032 MODULE_LICENSE("GPL");