2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include "s5p_mfc_cmd.h"
19 #include "s5p_mfc_common.h"
20 #include "s5p_mfc_debug.h"
21 #include "s5p_mfc_intr.h"
22 #include "s5p_mfc_opr.h"
23 #include "s5p_mfc_pm.h"
24 #include "s5p_mfc_ctrl.h"
26 /* Allocate memory for firmware */
27 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
30 dma_addr_t bank2_dma_addr;
32 dev->fw_size = dev->variant->buf_size->fw;
34 if (dev->fw_virt_addr) {
35 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
39 dev->fw_virt_addr = dma_alloc_coherent(dev->mem_dev_l, dev->fw_size,
40 &dev->bank1, GFP_KERNEL);
42 if (!dev->fw_virt_addr) {
43 mfc_err("Allocating bitprocessor buffer failed\n");
47 if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
48 bank2_virt = dma_alloc_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
49 &bank2_dma_addr, GFP_KERNEL);
52 mfc_err("Allocating bank2 base failed\n");
53 dma_free_coherent(dev->mem_dev_l, dev->fw_size,
54 dev->fw_virt_addr, dev->bank1);
55 dev->fw_virt_addr = NULL;
59 /* Valid buffers passed to MFC encoder with LAST_FRAME command
60 * should not have address of bank2 - MFC will treat it as a null frame.
61 * To avoid such situation we set bank2 address below the pool address.
63 dev->bank2 = bank2_dma_addr - (1 << MFC_BASE_ALIGN_ORDER);
65 dma_free_coherent(dev->mem_dev_r, 1 << MFC_BASE_ALIGN_ORDER,
66 bank2_virt, bank2_dma_addr);
69 /* In this case bank2 can point to the same address as bank1.
70 * Firmware will always occupy the beginning of this area so it is
71 * impossible having a video frame buffer with zero address. */
72 dev->bank2 = dev->bank1;
78 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
80 struct firmware *fw_blob;
83 /* Firmare has to be present as a separate file or compiled
87 for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
88 if (!dev->variant->fw_name[i])
90 err = request_firmware((const struct firmware **)&fw_blob,
91 dev->variant->fw_name[i], dev->v4l2_dev.dev);
93 dev->fw_ver = (enum s5p_mfc_fw_ver) i;
99 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
102 if (fw_blob->size > dev->fw_size) {
103 mfc_err("MFC firmware is too big to be loaded\n");
104 release_firmware(fw_blob);
107 if (!dev->fw_virt_addr) {
108 mfc_err("MFC firmware is not allocated\n");
109 release_firmware(fw_blob);
112 memcpy(dev->fw_virt_addr, fw_blob->data, fw_blob->size);
114 release_firmware(fw_blob);
119 /* Release firmware memory */
120 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
122 /* Before calling this function one has to make sure
123 * that MFC is no longer processing */
124 if (!dev->fw_virt_addr)
126 dma_free_coherent(dev->mem_dev_l, dev->fw_size, dev->fw_virt_addr,
128 dev->fw_virt_addr = NULL;
132 static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
135 unsigned long timeout;
138 mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
139 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
140 /* Check bus status */
142 if (time_after(jiffies, timeout)) {
143 mfc_err("Timeout while resetting MFC.\n");
146 status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
147 } while ((status & 0x2) == 0);
151 /* Reset the device */
152 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
154 unsigned int mc_status;
155 unsigned long timeout;
160 if (IS_MFCV6_PLUS(dev)) {
161 /* Zero Initialization of MFC registers */
162 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
163 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
164 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
166 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
167 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
169 /* check bus reset control before reset */
171 if (s5p_mfc_bus_reset(dev))
174 * set RISC_ON to 0 during power_on & wake_up.
175 * V6 needs RISC_ON set to 0 during reset also.
177 if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
178 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
180 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
181 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
185 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
186 /* All reset except for MC */
187 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
190 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
191 /* Check MC status */
193 if (time_after(jiffies, timeout)) {
194 mfc_err("Timeout while resetting MFC\n");
198 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
200 } while (mc_status & 0x3);
202 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
203 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
210 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
212 if (IS_MFCV6_PLUS(dev)) {
213 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6);
214 mfc_debug(2, "Base Address : %pad\n", &dev->bank1);
216 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
217 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
218 mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
219 &dev->bank1, &dev->bank2);
223 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
225 if (IS_MFCV6_PLUS(dev)) {
226 /* Zero initialization should be done before RESET.
227 * Nothing to do here. */
229 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
230 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
231 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
232 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
236 /* Initialize hardware */
237 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
243 if (!dev->fw_virt_addr) {
244 mfc_err("Firmware memory is not allocated.\n");
249 mfc_debug(2, "MFC reset..\n");
252 ret = s5p_mfc_reset(dev);
254 mfc_err("Failed to reset MFC - timeout\n");
257 mfc_debug(2, "Done MFC reset..\n");
258 /* 1. Set DRAM base Addr */
259 s5p_mfc_init_memctrl(dev);
260 /* 2. Initialize registers of channel I/F */
261 s5p_mfc_clear_cmds(dev);
262 /* 3. Release reset signal to the RISC */
263 s5p_mfc_clean_dev_int_flags(dev);
264 if (IS_MFCV6_PLUS(dev)) {
266 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
269 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
270 mfc_debug(2, "Will now wait for completion of firmware transfer\n");
271 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
272 mfc_err("Failed to load firmware\n");
277 s5p_mfc_clean_dev_int_flags(dev);
278 /* 4. Initialize firmware */
279 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
281 mfc_err("Failed to send command to MFC - timeout\n");
286 mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
287 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
288 mfc_err("Failed to init hardware\n");
294 if (dev->int_err != 0 || dev->int_type !=
295 S5P_MFC_R2H_CMD_SYS_INIT_RET) {
297 mfc_err("Failed to init firmware - error: %d int: %d\n",
298 dev->int_err, dev->int_type);
303 if (IS_MFCV6_PLUS(dev))
304 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
306 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
308 mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
309 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
316 /* Deinitialize hardware */
317 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
322 s5p_mfc_hw_call_void(dev->mfc_ops, release_dev_context_buffer, dev);
327 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
333 s5p_mfc_clean_dev_int_flags(dev);
334 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
336 mfc_err("Failed to send command to MFC - timeout\n");
339 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
340 mfc_err("Failed to sleep\n");
345 if (dev->int_err != 0 || dev->int_type !=
346 S5P_MFC_R2H_CMD_SLEEP_RET) {
348 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
356 static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
360 /* Release reset signal to the RISC */
362 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
364 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
365 mfc_err("Failed to reset MFCV8\n");
368 mfc_debug(2, "Write command to wakeup MFCV8\n");
369 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
371 mfc_err("Failed to send command to MFCV8 - timeout\n");
375 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
376 mfc_err("Failed to wakeup MFC\n");
382 static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
386 /* Send MFC wakeup command */
387 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
389 mfc_err("Failed to send command to MFC - timeout\n");
393 /* Release reset signal to the RISC */
394 if (IS_MFCV6_PLUS(dev)) {
396 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
398 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
401 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
402 mfc_err("Failed to wakeup MFC\n");
408 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
414 mfc_debug(2, "MFC reset..\n");
417 ret = s5p_mfc_reset(dev);
419 mfc_err("Failed to reset MFC - timeout\n");
423 mfc_debug(2, "Done MFC reset..\n");
424 /* 1. Set DRAM base Addr */
425 s5p_mfc_init_memctrl(dev);
426 /* 2. Initialize registers of channel I/F */
427 s5p_mfc_clear_cmds(dev);
428 s5p_mfc_clean_dev_int_flags(dev);
429 /* 3. Send MFC wakeup command and wait for completion*/
431 ret = s5p_mfc_v8_wait_wakeup(dev);
433 ret = s5p_mfc_wait_wakeup(dev);
440 if (dev->int_err != 0 || dev->int_type !=
441 S5P_MFC_R2H_CMD_WAKEUP_RET) {
443 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
451 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
455 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
457 mfc_err("Failed allocating instance buffer\n");
461 if (ctx->type == MFCINST_DECODER) {
462 ret = s5p_mfc_hw_call(dev->mfc_ops,
463 alloc_dec_temp_buffers, ctx);
465 mfc_err("Failed allocating temporary buffers\n");
466 goto err_free_inst_buf;
470 set_work_bit_irqsave(ctx);
471 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
472 if (s5p_mfc_wait_for_done_ctx(ctx,
473 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
474 /* Error or timeout */
475 mfc_err("Error getting instance from hardware\n");
477 goto err_free_desc_buf;
480 mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
484 if (ctx->type == MFCINST_DECODER)
485 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
487 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
492 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
494 ctx->state = MFCINST_RETURN_INST;
495 set_work_bit_irqsave(ctx);
496 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
497 /* Wait until instance is returned or timeout occurred */
498 if (s5p_mfc_wait_for_done_ctx(ctx,
499 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
500 mfc_err("Err returning instance\n");
503 s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx);
504 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
505 if (ctx->type == MFCINST_DECODER)
506 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
508 ctx->inst_no = MFC_NO_INSTANCE_SET;
509 ctx->state = MFCINST_FREE;