drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c

   1 /*
   2  * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
   3  *
   4  * Samsung MFC (Multi Function Codec - FIMV) driver
   5  * This file contains hw related functions.
   6  *
   7  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   8  *              http://www.samsung.com/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #undef DEBUG
  16
  17 #include <linux/delay.h>
  18 #include <linux/mm.h>
  19 #include <linux/io.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/firmware.h>
  22 #include <linux/err.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #include <asm/cacheflush.h>
  27
  28 #include "s5p_mfc_common.h"
  29 #include "s5p_mfc_cmd.h"
  30 #include "s5p_mfc_intr.h"
  31 #include "s5p_mfc_pm.h"
  32 #include "s5p_mfc_debug.h"
  33 #include "s5p_mfc_opr.h"
  34 #include "s5p_mfc_opr_v6.h"
  35
  36 /* #define S5P_MFC_DEBUG_REGWRITE  */
  37 #ifdef S5P_MFC_DEBUG_REGWRITE
  38 #undef writel
  39 #define writel(v, r)                                                    \
  40         do {                                                            \
  41                 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);     \
  42         __raw_writel(v, r);                                             \
  43         } while (0)
  44 #endif /* S5P_MFC_DEBUG_REGWRITE */
  45
  46 #define READL(reg) \
  47         (WARN_ON_ONCE(!(reg)) ? 0 : readl(reg))
  48 #define WRITEL(data, reg) \
  49         (WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg)))
  50
  51 /* Allocate temporary buffers for decoding */
  52 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
  53 {
  54         /* NOP */
  55
  56         return 0;
  57 }
  58
  59 /* Release temproary buffers for decoding */
  60 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
  61 {
  62         /* NOP */
  63 }
  64
  65 /* Allocate codec buffers */
  66 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
  67 {
  68         struct s5p_mfc_dev *dev = ctx->dev;
  69         unsigned int mb_width, mb_height;
  70         int ret;
  71
  72         mb_width = MB_WIDTH(ctx->img_width);
  73         mb_height = MB_HEIGHT(ctx->img_height);
  74
  75         if (ctx->type == MFCINST_DECODER) {
  76                 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
  77                           ctx->luma_size, ctx->chroma_size, ctx->mv_size);
  78                 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
  79         } else if (ctx->type == MFCINST_ENCODER) {
  80                 if (IS_MFCV8(dev))
  81                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  82                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
  83                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  84                 else
  85                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  86                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
  87                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  88
  89                 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
  90                                 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
  91                                 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
  92                 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
  93                                 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
  94                                 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
  95                 if (IS_MFCV8(dev))
  96                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
  97                                                 ctx->img_width, ctx->img_height,
  98                                                 mb_width, mb_height),
  99                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 100                 else
 101                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
 102                                                 ctx->img_width, ctx->img_height,
 103                                                 mb_width, mb_height),
 104                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 105
 106                 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
 107                           ctx->luma_dpb_size, ctx->chroma_dpb_size);
 108         } else {
 109                 return -EINVAL;
 110         }
 111
 112         /* Codecs have different memory requirements */
 113         switch (ctx->codec_mode) {
 114         case S5P_MFC_CODEC_H264_DEC:
 115         case S5P_MFC_CODEC_H264_MVC_DEC:
 116                 if (IS_MFCV8(dev))
 117                         ctx->scratch_buf_size =
 118                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 119                                         mb_width,
 120                                         mb_height);
 121                 else
 122                         ctx->scratch_buf_size =
 123                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
 124                                         mb_width,
 125                                         mb_height);
 126                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 127                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 128                 ctx->bank1.size =
 129                         ctx->scratch_buf_size +
 130                         (ctx->mv_count * ctx->mv_size);
 131                 break;
 132         case S5P_MFC_CODEC_MPEG4_DEC:
 133                 if (IS_MFCV7_PLUS(dev)) {
 134                         ctx->scratch_buf_size =
 135                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 136                                                 mb_width,
 137                                                 mb_height);
 138                 } else {
 139                         ctx->scratch_buf_size =
 140                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
 141                                                 mb_width,
 142                                                 mb_height);
 143                 }
 144
 145                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 146                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 147                 ctx->bank1.size = ctx->scratch_buf_size;
 148                 break;
 149         case S5P_MFC_CODEC_VC1RCV_DEC:
 150         case S5P_MFC_CODEC_VC1_DEC:
 151                 ctx->scratch_buf_size =
 152                         S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
 153                                         mb_width,
 154                                         mb_height);
 155                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 156                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 157                 ctx->bank1.size = ctx->scratch_buf_size;
 158                 break;
 159         case S5P_MFC_CODEC_MPEG2_DEC:
 160                 ctx->bank1.size = 0;
 161                 ctx->bank2.size = 0;
 162                 break;
 163         case S5P_MFC_CODEC_H263_DEC:
 164                 ctx->scratch_buf_size =
 165                         S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
 166                                         mb_width,
 167                                         mb_height);
 168                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 169                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 170                 ctx->bank1.size = ctx->scratch_buf_size;
 171                 break;
 172         case S5P_MFC_CODEC_VP8_DEC:
 173                 if (IS_MFCV8(dev))
 174                         ctx->scratch_buf_size =
 175                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 176                                                 mb_width,
 177                                                 mb_height);
 178                 else
 179                         ctx->scratch_buf_size =
 180                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
 181                                                 mb_width,
 182                                                 mb_height);
 183                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 184                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 185                 ctx->bank1.size = ctx->scratch_buf_size;
 186                 break;
 187         case S5P_MFC_CODEC_H264_ENC:
 188                 if (IS_MFCV8(dev))
 189                         ctx->scratch_buf_size =
 190                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 191                                         mb_width,
 192                                         mb_height);
 193                 else
 194                         ctx->scratch_buf_size =
 195                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
 196                                                 mb_width,
 197                                                 mb_height);
 198                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 199                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 200                 ctx->bank1.size =
 201                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 202                         (ctx->pb_count * (ctx->luma_dpb_size +
 203                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 204                 ctx->bank2.size = 0;
 205                 break;
 206         case S5P_MFC_CODEC_MPEG4_ENC:
 207         case S5P_MFC_CODEC_H263_ENC:
 208                 ctx->scratch_buf_size =
 209                         S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
 210                                         mb_width,
 211                                         mb_height);
 212                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 213                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 214                 ctx->bank1.size =
 215                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 216                         (ctx->pb_count * (ctx->luma_dpb_size +
 217                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 218                 ctx->bank2.size = 0;
 219                 break;
 220         case S5P_MFC_CODEC_VP8_ENC:
 221                 if (IS_MFCV8(dev))
 222                         ctx->scratch_buf_size =
 223                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 224                                         mb_width,
 225                                         mb_height);
 226                 else
 227                         ctx->scratch_buf_size =
 228                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
 229                                                 mb_width,
 230                                                 mb_height);
 231                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 232                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 233                 ctx->bank1.size =
 234                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 235                         (ctx->pb_count * (ctx->luma_dpb_size +
 236                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 237                 ctx->bank2.size = 0;
 238                 break;
 239         default:
 240                 break;
 241         }
 242
 243         /* Allocate only if memory from bank 1 is necessary */
 244         if (ctx->bank1.size > 0) {
 245                 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
 246                 if (ret) {
 247                         mfc_err("Failed to allocate Bank1 memory\n");
 248                         return ret;
 249                 }
 250                 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
 251         }
 252         return 0;
 253 }
 254
 255 /* Release buffers allocated for codec */
 256 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 257 {
 258         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
 259 }
 260
 261 /* Allocate memory for instance data buffer */
 262 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 263 {
 264         struct s5p_mfc_dev *dev = ctx->dev;
 265         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 266         int ret;
 267
 268         mfc_debug_enter();
 269
 270         switch (ctx->codec_mode) {
 271         case S5P_MFC_CODEC_H264_DEC:
 272         case S5P_MFC_CODEC_H264_MVC_DEC:
 273                 ctx->ctx.size = buf_size->h264_dec_ctx;
 274                 break;
 275         case S5P_MFC_CODEC_MPEG4_DEC:
 276         case S5P_MFC_CODEC_H263_DEC:
 277         case S5P_MFC_CODEC_VC1RCV_DEC:
 278         case S5P_MFC_CODEC_VC1_DEC:
 279         case S5P_MFC_CODEC_MPEG2_DEC:
 280         case S5P_MFC_CODEC_VP8_DEC:
 281                 ctx->ctx.size = buf_size->other_dec_ctx;
 282                 break;
 283         case S5P_MFC_CODEC_H264_ENC:
 284                 ctx->ctx.size = buf_size->h264_enc_ctx;
 285                 break;
 286         case S5P_MFC_CODEC_MPEG4_ENC:
 287         case S5P_MFC_CODEC_H263_ENC:
 288         case S5P_MFC_CODEC_VP8_ENC:
 289                 ctx->ctx.size = buf_size->other_enc_ctx;
 290                 break;
 291         default:
 292                 ctx->ctx.size = 0;
 293                 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
 294                 break;
 295         }
 296
 297         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
 298         if (ret) {
 299                 mfc_err("Failed to allocate instance buffer\n");
 300                 return ret;
 301         }
 302
 303         memset(ctx->ctx.virt, 0, ctx->ctx.size);
 304         wmb();
 305
 306         mfc_debug_leave();
 307
 308         return 0;
 309 }
 310
 311 /* Release instance buffer */
 312 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 313 {
 314         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
 315 }
 316
 317 /* Allocate context buffers for SYS_INIT */
 318 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 319 {
 320         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 321         int ret;
 322
 323         mfc_debug_enter();
 324
 325         dev->ctx_buf.size = buf_size->dev_ctx;
 326         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
 327         if (ret) {
 328                 mfc_err("Failed to allocate device context buffer\n");
 329                 return ret;
 330         }
 331
 332         memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
 333         wmb();
 334
 335         mfc_debug_leave();
 336
 337         return 0;
 338 }
 339
 340 /* Release context buffers for SYS_INIT */
 341 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 342 {
 343         s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
 344 }
 345
 346 static int calc_plane(int width, int height)
 347 {
 348         int mbX, mbY;
 349
 350         mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 351         mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
 352
 353         if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
 354                 mbY = (mbY + 1) / 2 * 2;
 355
 356         return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
 357                 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 358 }
 359
 360 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 361 {
 362         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 363         ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 364         mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
 365                         "buffer dimensions: %dx%d\n", ctx->img_width,
 366                         ctx->img_height, ctx->buf_width, ctx->buf_height);
 367
 368         ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
 369         ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
 370         if (IS_MFCV8(ctx->dev)) {
 371                 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 372                 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 373                 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 374         }
 375
 376         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 377                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 378                 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
 379                                 ctx->img_height);
 380                 ctx->mv_size = ALIGN(ctx->mv_size, 16);
 381         } else {
 382                 ctx->mv_size = 0;
 383         }
 384 }
 385
 386 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
 387 {
 388         unsigned int mb_width, mb_height;
 389
 390         mb_width = MB_WIDTH(ctx->img_width);
 391         mb_height = MB_HEIGHT(ctx->img_height);
 392
 393         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 394         ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
 395         ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
 396
 397         /* MFCv7 needs pad bytes for Luma and Chroma */
 398         if (IS_MFCV7_PLUS(ctx->dev)) {
 399                 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 400                 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
 401         }
 402 }
 403
 404 /* Set registers for decoding stream buffer */
 405 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 406                         int buf_addr, unsigned int start_num_byte,
 407                         unsigned int strm_size)
 408 {
 409         struct s5p_mfc_dev *dev = ctx->dev;
 410         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 411         struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
 412
 413         mfc_debug_enter();
 414         mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
 415                 "buf_size: 0x%08x (%d)\n",
 416                 ctx->inst_no, buf_addr, strm_size, strm_size);
 417         WRITEL(strm_size, mfc_regs->d_stream_data_size);
 418         WRITEL(buf_addr, mfc_regs->d_cpb_buffer_addr);
 419         WRITEL(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
 420         WRITEL(start_num_byte, mfc_regs->d_cpb_buffer_offset);
 421
 422         mfc_debug_leave();
 423         return 0;
 424 }
 425
 426 /* Set decoding frame buffer */
 427 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 428 {
 429         unsigned int frame_size, i;
 430         unsigned int frame_size_ch, frame_size_mv;
 431         struct s5p_mfc_dev *dev = ctx->dev;
 432         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 433         size_t buf_addr1;
 434         int buf_size1;
 435         int align_gap;
 436
 437         buf_addr1 = ctx->bank1.dma;
 438         buf_size1 = ctx->bank1.size;
 439
 440         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 441         mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
 442         mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
 443
 444         WRITEL(ctx->total_dpb_count, mfc_regs->d_num_dpb);
 445         WRITEL(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
 446         WRITEL(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
 447
 448         WRITEL(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 449         WRITEL(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 450
 451         if (IS_MFCV8(dev)) {
 452                 WRITEL(ctx->img_width,
 453                         mfc_regs->d_first_plane_dpb_stride_size);
 454                 WRITEL(ctx->img_width,
 455                         mfc_regs->d_second_plane_dpb_stride_size);
 456         }
 457
 458         buf_addr1 += ctx->scratch_buf_size;
 459         buf_size1 -= ctx->scratch_buf_size;
 460
 461         if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
 462                         ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
 463                 WRITEL(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 464                 WRITEL(ctx->mv_count, mfc_regs->d_num_mv);
 465         }
 466
 467         frame_size = ctx->luma_size;
 468         frame_size_ch = ctx->chroma_size;
 469         frame_size_mv = ctx->mv_size;
 470         mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
 471                         frame_size, frame_size_ch, frame_size_mv);
 472
 473         for (i = 0; i < ctx->total_dpb_count; i++) {
 474                 /* Bank2 */
 475                 mfc_debug(2, "Luma %d: %x\n", i,
 476                                         ctx->dst_bufs[i].cookie.raw.luma);
 477                 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
 478                                 mfc_regs->d_first_plane_dpb + i * 4);
 479                 mfc_debug(2, "\tChroma %d: %x\n", i,
 480                                         ctx->dst_bufs[i].cookie.raw.chroma);
 481                 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
 482                                 mfc_regs->d_second_plane_dpb + i * 4);
 483         }
 484         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 485                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 486                 for (i = 0; i < ctx->mv_count; i++) {
 487                         /* To test alignment */
 488                         align_gap = buf_addr1;
 489                         buf_addr1 = ALIGN(buf_addr1, 16);
 490                         align_gap = buf_addr1 - align_gap;
 491                         buf_size1 -= align_gap;
 492
 493                         mfc_debug(2, "\tBuf1: %x, size: %d\n",
 494                                         buf_addr1, buf_size1);
 495                         WRITEL(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
 496                         buf_addr1 += frame_size_mv;
 497                         buf_size1 -= frame_size_mv;
 498                 }
 499         }
 500
 501         mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
 502                         buf_addr1, buf_size1, ctx->total_dpb_count);
 503         if (buf_size1 < 0) {
 504                 mfc_debug(2, "Not enough memory has been allocated.\n");
 505                 return -ENOMEM;
 506         }
 507
 508         WRITEL(ctx->inst_no, mfc_regs->instance_id);
 509         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 510                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 511
 512         mfc_debug(2, "After setting buffers.\n");
 513         return 0;
 514 }
 515
 516 /* Set registers for encoding stream buffer */
 517 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 518                 unsigned long addr, unsigned int size)
 519 {
 520         struct s5p_mfc_dev *dev = ctx->dev;
 521         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 522
 523         WRITEL(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
 524         WRITEL(size, mfc_regs->e_stream_buffer_size);
 525
 526         mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
 527                   addr, size);
 528
 529         return 0;
 530 }
 531
 532 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 533                 unsigned long y_addr, unsigned long c_addr)
 534 {
 535         struct s5p_mfc_dev *dev = ctx->dev;
 536         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 537
 538         WRITEL(y_addr, mfc_regs->e_source_first_plane_addr);
 539         WRITEL(c_addr, mfc_regs->e_source_second_plane_addr);
 540
 541         mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
 542         mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
 543 }
 544
 545 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 546                 unsigned long *y_addr, unsigned long *c_addr)
 547 {
 548         struct s5p_mfc_dev *dev = ctx->dev;
 549         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 550         unsigned long enc_recon_y_addr, enc_recon_c_addr;
 551
 552         *y_addr = READL(mfc_regs->e_encoded_source_first_plane_addr);
 553         *c_addr = READL(mfc_regs->e_encoded_source_second_plane_addr);
 554
 555         enc_recon_y_addr = READL(mfc_regs->e_recon_luma_dpb_addr);
 556         enc_recon_c_addr = READL(mfc_regs->e_recon_chroma_dpb_addr);
 557
 558         mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
 559         mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
 560 }
 561
 562 /* Set encoding ref & codec buffer */
 563 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 564 {
 565         struct s5p_mfc_dev *dev = ctx->dev;
 566         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 567         size_t buf_addr1;
 568         int i, buf_size1;
 569
 570         mfc_debug_enter();
 571
 572         buf_addr1 = ctx->bank1.dma;
 573         buf_size1 = ctx->bank1.size;
 574
 575         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 576
 577         for (i = 0; i < ctx->pb_count; i++) {
 578                 WRITEL(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 579                 buf_addr1 += ctx->luma_dpb_size;
 580                 WRITEL(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 581                 buf_addr1 += ctx->chroma_dpb_size;
 582                 WRITEL(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 583                 buf_addr1 += ctx->me_buffer_size;
 584                 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
 585                         ctx->me_buffer_size);
 586         }
 587
 588         WRITEL(buf_addr1, mfc_regs->e_scratch_buffer_addr);
 589         WRITEL(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
 590         buf_addr1 += ctx->scratch_buf_size;
 591         buf_size1 -= ctx->scratch_buf_size;
 592
 593         WRITEL(buf_addr1, mfc_regs->e_tmv_buffer0);
 594         buf_addr1 += ctx->tmv_buffer_size >> 1;
 595         WRITEL(buf_addr1, mfc_regs->e_tmv_buffer1);
 596         buf_addr1 += ctx->tmv_buffer_size >> 1;
 597         buf_size1 -= ctx->tmv_buffer_size;
 598
 599         mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
 600                         buf_addr1, buf_size1, ctx->pb_count);
 601         if (buf_size1 < 0) {
 602                 mfc_debug(2, "Not enough memory has been allocated.\n");
 603                 return -ENOMEM;
 604         }
 605
 606         WRITEL(ctx->inst_no, mfc_regs->instance_id);
 607         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 608                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 609
 610         mfc_debug_leave();
 611
 612         return 0;
 613 }
 614
 615 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
 616 {
 617         struct s5p_mfc_dev *dev = ctx->dev;
 618         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 619
 620         /* multi-slice control */
 621         /* multi-slice MB number or bit size */
 622         WRITEL(ctx->slice_mode, mfc_regs->e_mslice_mode);
 623         if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 624                 WRITEL(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
 625         } else if (ctx->slice_mode ==
 626                         V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 627                 WRITEL(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
 628         } else {
 629                 WRITEL(0x0, mfc_regs->e_mslice_size_mb);
 630                 WRITEL(0x0, mfc_regs->e_mslice_size_bits);
 631         }
 632
 633         return 0;
 634 }
 635
 636 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
 637 {
 638         struct s5p_mfc_dev *dev = ctx->dev;
 639         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 640         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 641         unsigned int reg = 0;
 642
 643         mfc_debug_enter();
 644
 645         /* width */
 646         WRITEL(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
 647         /* height */
 648         WRITEL(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
 649
 650         /* cropped width */
 651         WRITEL(ctx->img_width, mfc_regs->e_cropped_frame_width);
 652         /* cropped height */
 653         WRITEL(ctx->img_height, mfc_regs->e_cropped_frame_height);
 654         /* cropped offset */
 655         WRITEL(0x0, mfc_regs->e_frame_crop_offset);
 656
 657         /* pictype : IDR period */
 658         reg = 0;
 659         reg |= p->gop_size & 0xFFFF;
 660         WRITEL(reg, mfc_regs->e_gop_config);
 661
 662         /* multi-slice control */
 663         /* multi-slice MB number or bit size */
 664         ctx->slice_mode = p->slice_mode;
 665         reg = 0;
 666         if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 667                 reg |= (0x1 << 3);
 668                 WRITEL(reg, mfc_regs->e_enc_options);
 669                 ctx->slice_size.mb = p->slice_mb;
 670         } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 671                 reg |= (0x1 << 3);
 672                 WRITEL(reg, mfc_regs->e_enc_options);
 673                 ctx->slice_size.bits = p->slice_bit;
 674         } else {
 675                 reg &= ~(0x1 << 3);
 676                 WRITEL(reg, mfc_regs->e_enc_options);
 677         }
 678
 679         s5p_mfc_set_slice_mode(ctx);
 680
 681         /* cyclic intra refresh */
 682         WRITEL(p->intra_refresh_mb, mfc_regs->e_ir_size);
 683         reg = READL(mfc_regs->e_enc_options);
 684         if (p->intra_refresh_mb == 0)
 685                 reg &= ~(0x1 << 4);
 686         else
 687                 reg |= (0x1 << 4);
 688         WRITEL(reg, mfc_regs->e_enc_options);
 689
 690         /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
 691         reg = READL(mfc_regs->e_enc_options);
 692         reg &= ~(0x1 << 9);
 693         WRITEL(reg, mfc_regs->e_enc_options);
 694
 695         /* memory structure cur. frame */
 696         if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
 697                 /* 0: Linear, 1: 2D tiled*/
 698                 reg = READL(mfc_regs->e_enc_options);
 699                 reg &= ~(0x1 << 7);
 700                 WRITEL(reg, mfc_regs->e_enc_options);
 701                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 702                 WRITEL(0x0, mfc_regs->pixel_format);
 703         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
 704                 /* 0: Linear, 1: 2D tiled*/
 705                 reg = READL(mfc_regs->e_enc_options);
 706                 reg &= ~(0x1 << 7);
 707                 WRITEL(reg, mfc_regs->e_enc_options);
 708                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 709                 WRITEL(0x1, mfc_regs->pixel_format);
 710         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
 711                 /* 0: Linear, 1: 2D tiled*/
 712                 reg = READL(mfc_regs->e_enc_options);
 713                 reg |= (0x1 << 7);
 714                 WRITEL(reg, mfc_regs->e_enc_options);
 715                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 716                 WRITEL(0x0, mfc_regs->pixel_format);
 717         }
 718
 719         /* memory structure recon. frame */
 720         /* 0: Linear, 1: 2D tiled */
 721         reg = READL(mfc_regs->e_enc_options);
 722         reg |= (0x1 << 8);
 723         WRITEL(reg, mfc_regs->e_enc_options);
 724
 725         /* padding control & value */
 726         WRITEL(0x0, mfc_regs->e_padding_ctrl);
 727         if (p->pad) {
 728                 reg = 0;
 729                 /** enable */
 730                 reg |= (1 << 31);
 731                 /** cr value */
 732                 reg |= ((p->pad_cr & 0xFF) << 16);
 733                 /** cb value */
 734                 reg |= ((p->pad_cb & 0xFF) << 8);
 735                 /** y value */
 736                 reg |= p->pad_luma & 0xFF;
 737                 WRITEL(reg, mfc_regs->e_padding_ctrl);
 738         }
 739
 740         /* rate control config. */
 741         reg = 0;
 742         /* frame-level rate control */
 743         reg |= ((p->rc_frame & 0x1) << 9);
 744         WRITEL(reg, mfc_regs->e_rc_config);
 745
 746         /* bit rate */
 747         if (p->rc_frame)
 748                 WRITEL(p->rc_bitrate,
 749                         mfc_regs->e_rc_bit_rate);
 750         else
 751                 WRITEL(1, mfc_regs->e_rc_bit_rate);
 752
 753         /* reaction coefficient */
 754         if (p->rc_frame) {
 755                 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
 756                         WRITEL(1, mfc_regs->e_rc_mode);
 757                 else                                      /* loose CBR */
 758                         WRITEL(2, mfc_regs->e_rc_mode);
 759         }
 760
 761         /* seq header ctrl */
 762         reg = READL(mfc_regs->e_enc_options);
 763         reg &= ~(0x1 << 2);
 764         reg |= ((p->seq_hdr_mode & 0x1) << 2);
 765
 766         /* frame skip mode */
 767         reg &= ~(0x3);
 768         reg |= (p->frame_skip_mode & 0x3);
 769         WRITEL(reg, mfc_regs->e_enc_options);
 770
 771         /* 'DROP_CONTROL_ENABLE', disable */
 772         reg = READL(mfc_regs->e_rc_config);
 773         reg &= ~(0x1 << 10);
 774         WRITEL(reg, mfc_regs->e_rc_config);
 775
 776         /* setting for MV range [16, 256] */
 777         reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 778         WRITEL(reg, mfc_regs->e_mv_hor_range);
 779
 780         reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 781         WRITEL(reg, mfc_regs->e_mv_ver_range);
 782
 783         WRITEL(0x0, mfc_regs->e_frame_insertion);
 784         WRITEL(0x0, mfc_regs->e_roi_buffer_addr);
 785         WRITEL(0x0, mfc_regs->e_param_change);
 786         WRITEL(0x0, mfc_regs->e_rc_roi_ctrl);
 787         WRITEL(0x0, mfc_regs->e_picture_tag);
 788
 789         WRITEL(0x0, mfc_regs->e_bit_count_enable);
 790         WRITEL(0x0, mfc_regs->e_max_bit_count);
 791         WRITEL(0x0, mfc_regs->e_min_bit_count);
 792
 793         WRITEL(0x0, mfc_regs->e_metadata_buffer_addr);
 794         WRITEL(0x0, mfc_regs->e_metadata_buffer_size);
 795
 796         mfc_debug_leave();
 797
 798         return 0;
 799 }
 800
 801 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
 802 {
 803         struct s5p_mfc_dev *dev = ctx->dev;
 804         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 805         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 806         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
 807         unsigned int reg = 0;
 808         int i;
 809
 810         mfc_debug_enter();
 811
 812         s5p_mfc_set_enc_params(ctx);
 813
 814         /* pictype : number of B */
 815         reg = READL(mfc_regs->e_gop_config);
 816         reg &= ~(0x3 << 16);
 817         reg |= ((p->num_b_frame & 0x3) << 16);
 818         WRITEL(reg, mfc_regs->e_gop_config);
 819
 820         /* profile & level */
 821         reg = 0;
 822         /** level */
 823         reg |= ((p_h264->level & 0xFF) << 8);
 824         /** profile - 0 ~ 3 */
 825         reg |= p_h264->profile & 0x3F;
 826         WRITEL(reg, mfc_regs->e_picture_profile);
 827
 828         /* rate control config. */
 829         reg = READL(mfc_regs->e_rc_config);
 830         /** macroblock level rate control */
 831         reg &= ~(0x1 << 8);
 832         reg |= ((p->rc_mb & 0x1) << 8);
 833         WRITEL(reg, mfc_regs->e_rc_config);
 834
 835         /** frame QP */
 836         reg &= ~(0x3F);
 837         reg |= p_h264->rc_frame_qp & 0x3F;
 838         WRITEL(reg, mfc_regs->e_rc_config);
 839
 840         /* max & min value of QP */
 841         reg = 0;
 842         /** max QP */
 843         reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
 844         /** min QP */
 845         reg |= p_h264->rc_min_qp & 0x3F;
 846         WRITEL(reg, mfc_regs->e_rc_qp_bound);
 847
 848         /* other QPs */
 849         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
 850         if (!p->rc_frame && !p->rc_mb) {
 851                 reg = 0;
 852                 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
 853                 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
 854                 reg |= p_h264->rc_frame_qp & 0x3F;
 855                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
 856         }
 857
 858         /* frame rate */
 859         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
 860                 reg = 0;
 861                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
 862                 reg |= p->rc_framerate_denom & 0xFFFF;
 863                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
 864         }
 865
 866         /* vbv buffer size */
 867         if (p->frame_skip_mode ==
 868                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
 869                 WRITEL(p_h264->cpb_size & 0xFFFF,
 870                                 mfc_regs->e_vbv_buffer_size);
 871
 872                 if (p->rc_frame)
 873                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
 874         }
 875
 876         /* interlace */
 877         reg = 0;
 878         reg |= ((p_h264->interlace & 0x1) << 3);
 879         WRITEL(reg, mfc_regs->e_h264_options);
 880
 881         /* height */
 882         if (p_h264->interlace) {
 883                 WRITEL(ctx->img_height >> 1,
 884                                 mfc_regs->e_frame_height); /* 32 align */
 885                 /* cropped height */
 886                 WRITEL(ctx->img_height >> 1,
 887                                 mfc_regs->e_cropped_frame_height);
 888         }
 889
 890         /* loop filter ctrl */
 891         reg = READL(mfc_regs->e_h264_options);
 892         reg &= ~(0x3 << 1);
 893         reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
 894         WRITEL(reg, mfc_regs->e_h264_options);
 895
 896         /* loopfilter alpha offset */
 897         if (p_h264->loop_filter_alpha < 0) {
 898                 reg = 0x10;
 899                 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
 900         } else {
 901                 reg = 0x00;
 902                 reg |= (p_h264->loop_filter_alpha & 0xF);
 903         }
 904         WRITEL(reg, mfc_regs->e_h264_lf_alpha_offset);
 905
 906         /* loopfilter beta offset */
 907         if (p_h264->loop_filter_beta < 0) {
 908                 reg = 0x10;
 909                 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
 910         } else {
 911                 reg = 0x00;
 912                 reg |= (p_h264->loop_filter_beta & 0xF);
 913         }
 914         WRITEL(reg, mfc_regs->e_h264_lf_beta_offset);
 915
 916         /* entropy coding mode */
 917         reg = READL(mfc_regs->e_h264_options);
 918         reg &= ~(0x1);
 919         reg |= p_h264->entropy_mode & 0x1;
 920         WRITEL(reg, mfc_regs->e_h264_options);
 921
 922         /* number of ref. picture */
 923         reg = READL(mfc_regs->e_h264_options);
 924         reg &= ~(0x1 << 7);
 925         reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
 926         WRITEL(reg, mfc_regs->e_h264_options);
 927
 928         /* 8x8 transform enable */
 929         reg = READL(mfc_regs->e_h264_options);
 930         reg &= ~(0x3 << 12);
 931         reg |= ((p_h264->_8x8_transform & 0x3) << 12);
 932         WRITEL(reg, mfc_regs->e_h264_options);
 933
 934         /* macroblock adaptive scaling features */
 935         WRITEL(0x0, mfc_regs->e_mb_rc_config);
 936         if (p->rc_mb) {
 937                 reg = 0;
 938                 /** dark region */
 939                 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
 940                 /** smooth region */
 941                 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
 942                 /** static region */
 943                 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
 944                 /** high activity region */
 945                 reg |= p_h264->rc_mb_activity & 0x1;
 946                 WRITEL(reg, mfc_regs->e_mb_rc_config);
 947         }
 948
 949         /* aspect ratio VUI */
 950         READL(mfc_regs->e_h264_options);
 951         reg &= ~(0x1 << 5);
 952         reg |= ((p_h264->vui_sar & 0x1) << 5);
 953         WRITEL(reg, mfc_regs->e_h264_options);
 954
 955         WRITEL(0x0, mfc_regs->e_aspect_ratio);
 956         WRITEL(0x0, mfc_regs->e_extended_sar);
 957         if (p_h264->vui_sar) {
 958                 /* aspect ration IDC */
 959                 reg = 0;
 960                 reg |= p_h264->vui_sar_idc & 0xFF;
 961                 WRITEL(reg, mfc_regs->e_aspect_ratio);
 962                 if (p_h264->vui_sar_idc == 0xFF) {
 963                         /* extended SAR */
 964                         reg = 0;
 965                         reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
 966                         reg |= p_h264->vui_ext_sar_height & 0xFFFF;
 967                         WRITEL(reg, mfc_regs->e_extended_sar);
 968                 }
 969         }
 970
 971         /* intra picture period for H.264 open GOP */
 972         /* control */
 973         READL(mfc_regs->e_h264_options);
 974         reg &= ~(0x1 << 4);
 975         reg |= ((p_h264->open_gop & 0x1) << 4);
 976         WRITEL(reg, mfc_regs->e_h264_options);
 977
 978         /* value */
 979         WRITEL(0x0, mfc_regs->e_h264_i_period);
 980         if (p_h264->open_gop) {
 981                 reg = 0;
 982                 reg |= p_h264->open_gop_size & 0xFFFF;
 983                 WRITEL(reg, mfc_regs->e_h264_i_period);
 984         }
 985
 986         /* 'WEIGHTED_BI_PREDICTION' for B is disable */
 987         READL(mfc_regs->e_h264_options);
 988         reg &= ~(0x3 << 9);
 989         WRITEL(reg, mfc_regs->e_h264_options);
 990
 991         /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
 992         READL(mfc_regs->e_h264_options);
 993         reg &= ~(0x1 << 14);
 994         WRITEL(reg, mfc_regs->e_h264_options);
 995
 996         /* ASO */
 997         READL(mfc_regs->e_h264_options);
 998         reg &= ~(0x1 << 6);
 999         reg |= ((p_h264->aso & 0x1) << 6);
1000         WRITEL(reg, mfc_regs->e_h264_options);
1001
1002         /* hier qp enable */
1003         READL(mfc_regs->e_h264_options);
1004         reg &= ~(0x1 << 8);
1005         reg |= ((p_h264->open_gop & 0x1) << 8);
1006         WRITEL(reg, mfc_regs->e_h264_options);
1007         reg = 0;
1008         if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1009                 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1010                 reg |= p_h264->hier_qp_layer & 0x7;
1011                 WRITEL(reg, mfc_regs->e_h264_num_t_layer);
1012                 /* QP value for each layer */
1013                 for (i = 0; i < p_h264->hier_qp_layer &&
1014                                 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1015                         WRITEL(p_h264->hier_qp_layer_qp[i],
1016                                 mfc_regs->e_h264_hierarchical_qp_layer0
1017                                 + i * 4);
1018                 }
1019         }
1020         /* number of coding layer should be zero when hierarchical is disable */
1021         WRITEL(reg, mfc_regs->e_h264_num_t_layer);
1022
1023         /* frame packing SEI generation */
1024         READL(mfc_regs->e_h264_options);
1025         reg &= ~(0x1 << 25);
1026         reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1027         WRITEL(reg, mfc_regs->e_h264_options);
1028         if (p_h264->sei_frame_packing) {
1029                 reg = 0;
1030                 /** current frame0 flag */
1031                 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1032                 /** arrangement type */
1033                 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1034                 WRITEL(reg, mfc_regs->e_h264_frame_packing_sei_info);
1035         }
1036
1037         if (p_h264->fmo) {
1038                 switch (p_h264->fmo_map_type) {
1039                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1040                         if (p_h264->fmo_slice_grp > 4)
1041                                 p_h264->fmo_slice_grp = 4;
1042                         for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1043                                 WRITEL(p_h264->fmo_run_len[i] - 1,
1044                                         mfc_regs->e_h264_fmo_run_length_minus1_0
1045                                         + i * 4);
1046                         break;
1047                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1048                         if (p_h264->fmo_slice_grp > 4)
1049                                 p_h264->fmo_slice_grp = 4;
1050                         break;
1051                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1052                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1053                         if (p_h264->fmo_slice_grp > 2)
1054                                 p_h264->fmo_slice_grp = 2;
1055                         WRITEL(p_h264->fmo_chg_dir & 0x1,
1056                                 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1057                         /* the valid range is 0 ~ number of macroblocks -1 */
1058                         WRITEL(p_h264->fmo_chg_rate,
1059                         mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1060                         break;
1061                 default:
1062                         mfc_err("Unsupported map type for FMO: %d\n",
1063                                         p_h264->fmo_map_type);
1064                         p_h264->fmo_map_type = 0;
1065                         p_h264->fmo_slice_grp = 1;
1066                         break;
1067                 }
1068
1069                 WRITEL(p_h264->fmo_map_type,
1070                                 mfc_regs->e_h264_fmo_slice_grp_map_type);
1071                 WRITEL(p_h264->fmo_slice_grp - 1,
1072                                 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1073         } else {
1074                 WRITEL(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1075         }
1076
1077         mfc_debug_leave();
1078
1079         return 0;
1080 }
1081
1082 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1083 {
1084         struct s5p_mfc_dev *dev = ctx->dev;
1085         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1086         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1087         struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1088         unsigned int reg = 0;
1089
1090         mfc_debug_enter();
1091
1092         s5p_mfc_set_enc_params(ctx);
1093
1094         /* pictype : number of B */
1095         reg = READL(mfc_regs->e_gop_config);
1096         reg &= ~(0x3 << 16);
1097         reg |= ((p->num_b_frame & 0x3) << 16);
1098         WRITEL(reg, mfc_regs->e_gop_config);
1099
1100         /* profile & level */
1101         reg = 0;
1102         /** level */
1103         reg |= ((p_mpeg4->level & 0xFF) << 8);
1104         /** profile - 0 ~ 1 */
1105         reg |= p_mpeg4->profile & 0x3F;
1106         WRITEL(reg, mfc_regs->e_picture_profile);
1107
1108         /* rate control config. */
1109         reg = READL(mfc_regs->e_rc_config);
1110         /** macroblock level rate control */
1111         reg &= ~(0x1 << 8);
1112         reg |= ((p->rc_mb & 0x1) << 8);
1113         WRITEL(reg, mfc_regs->e_rc_config);
1114
1115         /** frame QP */
1116         reg &= ~(0x3F);
1117         reg |= p_mpeg4->rc_frame_qp & 0x3F;
1118         WRITEL(reg, mfc_regs->e_rc_config);
1119
1120         /* max & min value of QP */
1121         reg = 0;
1122         /** max QP */
1123         reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1124         /** min QP */
1125         reg |= p_mpeg4->rc_min_qp & 0x3F;
1126         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1127
1128         /* other QPs */
1129         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1130         if (!p->rc_frame && !p->rc_mb) {
1131                 reg = 0;
1132                 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1133                 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1134                 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1135                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1136         }
1137
1138         /* frame rate */
1139         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1140                 reg = 0;
1141                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1142                 reg |= p->rc_framerate_denom & 0xFFFF;
1143                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1144         }
1145
1146         /* vbv buffer size */
1147         if (p->frame_skip_mode ==
1148                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1149                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1150
1151                 if (p->rc_frame)
1152                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1153         }
1154
1155         /* Disable HEC */
1156         WRITEL(0x0, mfc_regs->e_mpeg4_options);
1157         WRITEL(0x0, mfc_regs->e_mpeg4_hec_period);
1158
1159         mfc_debug_leave();
1160
1161         return 0;
1162 }
1163
1164 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1165 {
1166         struct s5p_mfc_dev *dev = ctx->dev;
1167         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1168         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1169         struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1170         unsigned int reg = 0;
1171
1172         mfc_debug_enter();
1173
1174         s5p_mfc_set_enc_params(ctx);
1175
1176         /* profile & level */
1177         reg = 0;
1178         /** profile */
1179         reg |= (0x1 << 4);
1180         WRITEL(reg, mfc_regs->e_picture_profile);
1181
1182         /* rate control config. */
1183         reg = READL(mfc_regs->e_rc_config);
1184         /** macroblock level rate control */
1185         reg &= ~(0x1 << 8);
1186         reg |= ((p->rc_mb & 0x1) << 8);
1187         WRITEL(reg, mfc_regs->e_rc_config);
1188
1189         /** frame QP */
1190         reg &= ~(0x3F);
1191         reg |= p_h263->rc_frame_qp & 0x3F;
1192         WRITEL(reg, mfc_regs->e_rc_config);
1193
1194         /* max & min value of QP */
1195         reg = 0;
1196         /** max QP */
1197         reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1198         /** min QP */
1199         reg |= p_h263->rc_min_qp & 0x3F;
1200         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1201
1202         /* other QPs */
1203         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1204         if (!p->rc_frame && !p->rc_mb) {
1205                 reg = 0;
1206                 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1207                 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1208                 reg |= p_h263->rc_frame_qp & 0x3F;
1209                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1210         }
1211
1212         /* frame rate */
1213         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1214                 reg = 0;
1215                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1216                 reg |= p->rc_framerate_denom & 0xFFFF;
1217                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1218         }
1219
1220         /* vbv buffer size */
1221         if (p->frame_skip_mode ==
1222                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1223                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1224
1225                 if (p->rc_frame)
1226                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1227         }
1228
1229         mfc_debug_leave();
1230
1231         return 0;
1232 }
1233
1234 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1235 {
1236         struct s5p_mfc_dev *dev = ctx->dev;
1237         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1238         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1239         struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1240         unsigned int reg = 0;
1241         unsigned int val = 0;
1242
1243         mfc_debug_enter();
1244
1245         s5p_mfc_set_enc_params(ctx);
1246
1247         /* pictype : number of B */
1248         reg = READL(mfc_regs->e_gop_config);
1249         reg &= ~(0x3 << 16);
1250         reg |= ((p->num_b_frame & 0x3) << 16);
1251         WRITEL(reg, mfc_regs->e_gop_config);
1252
1253         /* profile - 0 ~ 3 */
1254         reg = p_vp8->profile & 0x3;
1255         WRITEL(reg, mfc_regs->e_picture_profile);
1256
1257         /* rate control config. */
1258         reg = READL(mfc_regs->e_rc_config);
1259         /** macroblock level rate control */
1260         reg &= ~(0x1 << 8);
1261         reg |= ((p->rc_mb & 0x1) << 8);
1262         WRITEL(reg, mfc_regs->e_rc_config);
1263
1264         /* frame rate */
1265         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1266                 reg = 0;
1267                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1268                 reg |= p->rc_framerate_denom & 0xFFFF;
1269                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1270         }
1271
1272         /* frame QP */
1273         reg &= ~(0x7F);
1274         reg |= p_vp8->rc_frame_qp & 0x7F;
1275         WRITEL(reg, mfc_regs->e_rc_config);
1276
1277         /* other QPs */
1278         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1279         if (!p->rc_frame && !p->rc_mb) {
1280                 reg = 0;
1281                 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1282                 reg |= p_vp8->rc_frame_qp & 0x7F;
1283                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1284         }
1285
1286         /* max QP */
1287         reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1288         /* min QP */
1289         reg |= p_vp8->rc_min_qp & 0x7F;
1290         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1291
1292         /* vbv buffer size */
1293         if (p->frame_skip_mode ==
1294                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1295                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1296
1297                 if (p->rc_frame)
1298                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1299         }
1300
1301         /* VP8 specific params */
1302         reg = 0;
1303         reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1304         switch (p_vp8->num_partitions) {
1305         case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1306                 val = 0;
1307                 break;
1308         case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1309                 val = 2;
1310                 break;
1311         case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1312                 val = 4;
1313                 break;
1314         case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1315                 val = 8;
1316                 break;
1317         }
1318         reg |= (val & 0xF) << 3;
1319         reg |= (p_vp8->num_ref & 0x2);
1320         WRITEL(reg, mfc_regs->e_vp8_options);
1321
1322         mfc_debug_leave();
1323
1324         return 0;
1325 }
1326
1327 /* Initialize decoding */
1328 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1329 {
1330         struct s5p_mfc_dev *dev = ctx->dev;
1331         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1332         unsigned int reg = 0;
1333         int fmo_aso_ctrl = 0;
1334
1335         mfc_debug_enter();
1336         mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1337                         S5P_FIMV_CH_SEQ_HEADER_V6);
1338         mfc_debug(2, "BUFs: %08x %08x %08x\n",
1339                   READL(mfc_regs->d_cpb_buffer_addr),
1340                   READL(mfc_regs->d_cpb_buffer_addr),
1341                   READL(mfc_regs->d_cpb_buffer_addr));
1342
1343         /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1344         reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1345
1346         /* When user sets desplay_delay to 0,
1347          * It works as "display_delay enable" and delay set to 0.
1348          * If user wants display_delay disable, It should be
1349          * set to negative value. */
1350         if (ctx->display_delay >= 0) {
1351                 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1352                 WRITEL(ctx->display_delay, mfc_regs->d_display_delay);
1353         }
1354
1355         if (IS_MFCV7_PLUS(dev)) {
1356                 WRITEL(reg, mfc_regs->d_dec_options);
1357                 reg = 0;
1358         }
1359
1360         /* Setup loop filter, for decoding this is only valid for MPEG4 */
1361         if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1362                 mfc_debug(2, "Set loop filter to: %d\n",
1363                                 ctx->loop_filter_mpeg4);
1364                 reg |= (ctx->loop_filter_mpeg4 <<
1365                                 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1366         }
1367         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1368                 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1369
1370         if (IS_MFCV7_PLUS(dev))
1371                 WRITEL(reg, mfc_regs->d_init_buffer_options);
1372         else
1373                 WRITEL(reg, mfc_regs->d_dec_options);
1374
1375         /* 0: NV12(CbCr), 1: NV21(CrCb) */
1376         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1377                 WRITEL(0x1, mfc_regs->pixel_format);
1378         else
1379                 WRITEL(0x0, mfc_regs->pixel_format);
1380
1381
1382         /* sei parse */
1383         WRITEL(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1384
1385         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1386         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1387                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1388
1389         mfc_debug_leave();
1390         return 0;
1391 }
1392
1393 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1394 {
1395         struct s5p_mfc_dev *dev = ctx->dev;
1396         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1397
1398         if (flush) {
1399                 dev->curr_ctx = ctx->num;
1400                 s5p_mfc_clean_ctx_int_flags(ctx);
1401                 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1402                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1403                                 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1404         }
1405 }
1406
1407 /* Decode a single frame */
1408 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1409                         enum s5p_mfc_decode_arg last_frame)
1410 {
1411         struct s5p_mfc_dev *dev = ctx->dev;
1412         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1413
1414         WRITEL(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1415         WRITEL(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1416
1417         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1418         /* Issue different commands to instance basing on whether it
1419          * is the last frame or not. */
1420         switch (last_frame) {
1421         case 0:
1422                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1423                                 S5P_FIMV_CH_FRAME_START_V6, NULL);
1424                 break;
1425         case 1:
1426                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1427                                 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1428                 break;
1429         default:
1430                 mfc_err("Unsupported last frame arg.\n");
1431                 return -EINVAL;
1432         }
1433
1434         mfc_debug(2, "Decoding a usual frame.\n");
1435         return 0;
1436 }
1437
1438 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1439 {
1440         struct s5p_mfc_dev *dev = ctx->dev;
1441         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1442
1443         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1444                 s5p_mfc_set_enc_params_h264(ctx);
1445         else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1446                 s5p_mfc_set_enc_params_mpeg4(ctx);
1447         else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1448                 s5p_mfc_set_enc_params_h263(ctx);
1449         else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1450                 s5p_mfc_set_enc_params_vp8(ctx);
1451         else {
1452                 mfc_err("Unknown codec for encoding (%x).\n",
1453                         ctx->codec_mode);
1454                 return -EINVAL;
1455         }
1456
1457         /* Set stride lengths for v7 & above */
1458         if (IS_MFCV7_PLUS(dev)) {
1459                 WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1460                 WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1461         }
1462
1463         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1464         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1465                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1466
1467         return 0;
1468 }
1469
1470 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1471 {
1472         struct s5p_mfc_dev *dev = ctx->dev;
1473         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1474         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1475         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1476         int i;
1477
1478         if (p_h264->aso) {
1479                 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1480                         WRITEL(p_h264->aso_slice_order[i],
1481                                 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1482                 }
1483         }
1484         return 0;
1485 }
1486
1487 /* Encode a single frame */
1488 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1489 {
1490         struct s5p_mfc_dev *dev = ctx->dev;
1491         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1492
1493         mfc_debug(2, "++\n");
1494
1495         /* memory structure cur. frame */
1496
1497         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1498                 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1499
1500         s5p_mfc_set_slice_mode(ctx);
1501
1502         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1503         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1504                         S5P_FIMV_CH_FRAME_START_V6, NULL);
1505
1506         mfc_debug(2, "--\n");
1507
1508         return 0;
1509 }
1510
1511 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1512 {
1513         unsigned long flags;
1514         int new_ctx;
1515         int cnt;
1516
1517         spin_lock_irqsave(&dev->condlock, flags);
1518         mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1519                                                         dev->ctx_work_bits);
1520         new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1521         cnt = 0;
1522         while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1523                 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1524                 cnt++;
1525                 if (cnt > MFC_NUM_CONTEXTS) {
1526                         /* No contexts to run */
1527                         spin_unlock_irqrestore(&dev->condlock, flags);
1528                         return -EAGAIN;
1529                 }
1530         }
1531         spin_unlock_irqrestore(&dev->condlock, flags);
1532         return new_ctx;
1533 }
1534
1535 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1536 {
1537         struct s5p_mfc_dev *dev = ctx->dev;
1538         struct s5p_mfc_buf *temp_vb;
1539         unsigned long flags;
1540
1541         spin_lock_irqsave(&dev->irqlock, flags);
1542
1543         /* Frames are being decoded */
1544         if (list_empty(&ctx->src_queue)) {
1545                 mfc_debug(2, "No src buffers.\n");
1546                 spin_unlock_irqrestore(&dev->irqlock, flags);
1547                 return;
1548         }
1549         /* Get the next source buffer */
1550         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1551         temp_vb->flags |= MFC_BUF_FLAG_USED;
1552         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1553                         vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1554         spin_unlock_irqrestore(&dev->irqlock, flags);
1555
1556         dev->curr_ctx = ctx->num;
1557         s5p_mfc_clean_ctx_int_flags(ctx);
1558         s5p_mfc_decode_one_frame_v6(ctx, 1);
1559 }
1560
1561 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1562 {
1563         struct s5p_mfc_dev *dev = ctx->dev;
1564         struct s5p_mfc_buf *temp_vb;
1565         unsigned long flags;
1566         int last_frame = 0;
1567
1568         if (ctx->state == MFCINST_FINISHING) {
1569                 last_frame = MFC_DEC_LAST_FRAME;
1570                 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1571                 dev->curr_ctx = ctx->num;
1572                 s5p_mfc_clean_ctx_int_flags(ctx);
1573                 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1574                 return 0;
1575         }
1576
1577         spin_lock_irqsave(&dev->irqlock, flags);
1578         /* Frames are being decoded */
1579         if (list_empty(&ctx->src_queue)) {
1580                 mfc_debug(2, "No src buffers.\n");
1581                 spin_unlock_irqrestore(&dev->irqlock, flags);
1582                 return -EAGAIN;
1583         }
1584         /* Get the next source buffer */
1585         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1586         temp_vb->flags |= MFC_BUF_FLAG_USED;
1587         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1588                 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1589                         ctx->consumed_stream,
1590                         temp_vb->b->v4l2_planes[0].bytesused);
1591         spin_unlock_irqrestore(&dev->irqlock, flags);
1592
1593         dev->curr_ctx = ctx->num;
1594         s5p_mfc_clean_ctx_int_flags(ctx);
1595         if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1596                 last_frame = 1;
1597                 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1598                 ctx->state = MFCINST_FINISHING;
1599         }
1600         s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1601
1602         return 0;
1603 }
1604
1605 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1606 {
1607         struct s5p_mfc_dev *dev = ctx->dev;
1608         unsigned long flags;
1609         struct s5p_mfc_buf *dst_mb;
1610         struct s5p_mfc_buf *src_mb;
1611         unsigned long src_y_addr, src_c_addr, dst_addr;
1612         /*
1613         unsigned int src_y_size, src_c_size;
1614         */
1615         unsigned int dst_size;
1616
1617         spin_lock_irqsave(&dev->irqlock, flags);
1618
1619         if (list_empty(&ctx->src_queue)) {
1620                 mfc_debug(2, "no src buffers.\n");
1621                 spin_unlock_irqrestore(&dev->irqlock, flags);
1622                 return -EAGAIN;
1623         }
1624
1625         if (list_empty(&ctx->dst_queue)) {
1626                 mfc_debug(2, "no dst buffers.\n");
1627                 spin_unlock_irqrestore(&dev->irqlock, flags);
1628                 return -EAGAIN;
1629         }
1630
1631         src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1632         src_mb->flags |= MFC_BUF_FLAG_USED;
1633         src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1634         src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1635
1636         mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1637         mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1638
1639         s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1640
1641         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1642         dst_mb->flags |= MFC_BUF_FLAG_USED;
1643         dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1644         dst_size = vb2_plane_size(dst_mb->b, 0);
1645
1646         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1647
1648         spin_unlock_irqrestore(&dev->irqlock, flags);
1649
1650         dev->curr_ctx = ctx->num;
1651         s5p_mfc_clean_ctx_int_flags(ctx);
1652         s5p_mfc_encode_one_frame_v6(ctx);
1653
1654         return 0;
1655 }
1656
1657 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1658 {
1659         struct s5p_mfc_dev *dev = ctx->dev;
1660         unsigned long flags;
1661         struct s5p_mfc_buf *temp_vb;
1662
1663         /* Initializing decoding - parsing header */
1664         spin_lock_irqsave(&dev->irqlock, flags);
1665         mfc_debug(2, "Preparing to init decoding.\n");
1666         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1667         mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1668         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1669                 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1670                         temp_vb->b->v4l2_planes[0].bytesused);
1671         spin_unlock_irqrestore(&dev->irqlock, flags);
1672         dev->curr_ctx = ctx->num;
1673         s5p_mfc_clean_ctx_int_flags(ctx);
1674         s5p_mfc_init_decode_v6(ctx);
1675 }
1676
1677 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1678 {
1679         struct s5p_mfc_dev *dev = ctx->dev;
1680         unsigned long flags;
1681         struct s5p_mfc_buf *dst_mb;
1682         unsigned long dst_addr;
1683         unsigned int dst_size;
1684
1685         spin_lock_irqsave(&dev->irqlock, flags);
1686
1687         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1688         dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1689         dst_size = vb2_plane_size(dst_mb->b, 0);
1690         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1691         spin_unlock_irqrestore(&dev->irqlock, flags);
1692         dev->curr_ctx = ctx->num;
1693         s5p_mfc_clean_ctx_int_flags(ctx);
1694         s5p_mfc_init_encode_v6(ctx);
1695 }
1696
1697 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1698 {
1699         struct s5p_mfc_dev *dev = ctx->dev;
1700         int ret;
1701         /* Header was parsed now start processing
1702          * First set the output frame buffers
1703          * s5p_mfc_alloc_dec_buffers(ctx); */
1704
1705         if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1706                 mfc_err("It seems that not all destionation buffers were\n"
1707                         "mmaped.MFC requires that all destination are mmaped\n"
1708                         "before starting processing.\n");
1709                 return -EAGAIN;
1710         }
1711
1712         dev->curr_ctx = ctx->num;
1713         s5p_mfc_clean_ctx_int_flags(ctx);
1714         ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1715         if (ret) {
1716                 mfc_err("Failed to alloc frame mem.\n");
1717                 ctx->state = MFCINST_ERROR;
1718         }
1719         return ret;
1720 }
1721
1722 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1723 {
1724         struct s5p_mfc_dev *dev = ctx->dev;
1725         int ret;
1726
1727         dev->curr_ctx = ctx->num;
1728         s5p_mfc_clean_ctx_int_flags(ctx);
1729         ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1730         if (ret) {
1731                 mfc_err("Failed to alloc frame mem.\n");
1732                 ctx->state = MFCINST_ERROR;
1733         }
1734         return ret;
1735 }
1736
1737 /* Try running an operation on hardware */
1738 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1739 {
1740         struct s5p_mfc_ctx *ctx;
1741         int new_ctx;
1742         unsigned int ret = 0;
1743
1744         mfc_debug(1, "Try run dev: %p\n", dev);
1745
1746         /* Check whether hardware is not running */
1747         if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1748                 /* This is perfectly ok, the scheduled ctx should wait */
1749                 mfc_debug(1, "Couldn't lock HW.\n");
1750                 return;
1751         }
1752
1753         /* Choose the context to run */
1754         new_ctx = s5p_mfc_get_new_ctx(dev);
1755         if (new_ctx < 0) {
1756                 /* No contexts to run */
1757                 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1758                         mfc_err("Failed to unlock hardware.\n");
1759                         return;
1760                 }
1761
1762                 mfc_debug(1, "No ctx is scheduled to be run.\n");
1763                 return;
1764         }
1765
1766         mfc_debug(1, "New context: %d\n", new_ctx);
1767         ctx = dev->ctx[new_ctx];
1768         mfc_debug(1, "Seting new context to %p\n", ctx);
1769         /* Got context to run in ctx */
1770         mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1771                 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1772         mfc_debug(1, "ctx->state=%d\n", ctx->state);
1773         /* Last frame has already been sent to MFC
1774          * Now obtaining frames from MFC buffer */
1775
1776         s5p_mfc_clock_on();
1777         if (ctx->type == MFCINST_DECODER) {
1778                 switch (ctx->state) {
1779                 case MFCINST_FINISHING:
1780                         s5p_mfc_run_dec_last_frames(ctx);
1781                         break;
1782                 case MFCINST_RUNNING:
1783                         ret = s5p_mfc_run_dec_frame(ctx);
1784                         break;
1785                 case MFCINST_INIT:
1786                         s5p_mfc_clean_ctx_int_flags(ctx);
1787                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1788                                         ctx);
1789                         break;
1790                 case MFCINST_RETURN_INST:
1791                         s5p_mfc_clean_ctx_int_flags(ctx);
1792                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1793                                         ctx);
1794                         break;
1795                 case MFCINST_GOT_INST:
1796                         s5p_mfc_run_init_dec(ctx);
1797                         break;
1798                 case MFCINST_HEAD_PARSED:
1799                         ret = s5p_mfc_run_init_dec_buffers(ctx);
1800                         break;
1801                 case MFCINST_FLUSH:
1802                         s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1803                         break;
1804                 case MFCINST_RES_CHANGE_INIT:
1805                         s5p_mfc_run_dec_last_frames(ctx);
1806                         break;
1807                 case MFCINST_RES_CHANGE_FLUSH:
1808                         s5p_mfc_run_dec_last_frames(ctx);
1809                         break;
1810                 case MFCINST_RES_CHANGE_END:
1811                         mfc_debug(2, "Finished remaining frames after resolution change.\n");
1812                         ctx->capture_state = QUEUE_FREE;
1813                         mfc_debug(2, "Will re-init the codec`.\n");
1814                         s5p_mfc_run_init_dec(ctx);
1815                         break;
1816                 default:
1817                         ret = -EAGAIN;
1818                 }
1819         } else if (ctx->type == MFCINST_ENCODER) {
1820                 switch (ctx->state) {
1821                 case MFCINST_FINISHING:
1822                 case MFCINST_RUNNING:
1823                         ret = s5p_mfc_run_enc_frame(ctx);
1824                         break;
1825                 case MFCINST_INIT:
1826                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1827                                         ctx);
1828                         break;
1829                 case MFCINST_RETURN_INST:
1830                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1831                                         ctx);
1832                         break;
1833                 case MFCINST_GOT_INST:
1834                         s5p_mfc_run_init_enc(ctx);
1835                         break;
1836                 case MFCINST_HEAD_PRODUCED:
1837                         ret = s5p_mfc_run_init_enc_buffers(ctx);
1838                         break;
1839                 default:
1840                         ret = -EAGAIN;
1841                 }
1842         } else {
1843                 mfc_err("invalid context type: %d\n", ctx->type);
1844                 ret = -EAGAIN;
1845         }
1846
1847         if (ret) {
1848                 /* Free hardware lock */
1849                 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1850                         mfc_err("Failed to unlock hardware.\n");
1851
1852                 /* This is in deed imporant, as no operation has been
1853                  * scheduled, reduce the clock count as no one will
1854                  * ever do this, because no interrupt related to this try_run
1855                  * will ever come from hardware. */
1856                 s5p_mfc_clock_off();
1857         }
1858 }
1859
1860
1861 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1862 {
1863         struct s5p_mfc_buf *b;
1864         int i;
1865
1866         while (!list_empty(lh)) {
1867                 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1868                 for (i = 0; i < b->b->num_planes; i++)
1869                         vb2_set_plane_payload(b->b, i, 0);
1870                 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1871                 list_del(&b->list);
1872         }
1873 }
1874
1875 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1876 {
1877         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1878         WRITEL(0, mfc_regs->risc2host_command);
1879         WRITEL(0, mfc_regs->risc2host_int);
1880 }
1881
1882 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1883                 unsigned int ofs)
1884 {
1885         s5p_mfc_clock_on();
1886         WRITEL(data, (void *)ofs);
1887         s5p_mfc_clock_off();
1888 }
1889
1890 static unsigned int
1891 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1892 {
1893         int ret;
1894
1895         s5p_mfc_clock_on();
1896         ret = READL((void *)ofs);
1897         s5p_mfc_clock_off();
1898
1899         return ret;
1900 }
1901
1902 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1903 {
1904         return READL(dev->mfc_regs->d_display_first_plane_addr);
1905 }
1906
1907 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1908 {
1909         return READL(dev->mfc_regs->d_decoded_first_plane_addr);
1910 }
1911
1912 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1913 {
1914         return READL(dev->mfc_regs->d_display_status);
1915 }
1916
1917 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1918 {
1919         return READL(dev->mfc_regs->d_decoded_status);
1920 }
1921
1922 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1923 {
1924         return READL(dev->mfc_regs->d_decoded_frame_type) &
1925                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1926 }
1927
1928 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1929 {
1930         struct s5p_mfc_dev *dev = ctx->dev;
1931         return READL(dev->mfc_regs->d_display_frame_type) &
1932                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1933 }
1934
1935 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1936 {
1937         return READL(dev->mfc_regs->d_decoded_nal_size);
1938 }
1939
1940 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1941 {
1942         return READL(dev->mfc_regs->risc2host_command) &
1943                 S5P_FIMV_RISC2HOST_CMD_MASK;
1944 }
1945
1946 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1947 {
1948         return READL(dev->mfc_regs->error_code);
1949 }
1950
1951 static int s5p_mfc_err_dec_v6(unsigned int err)
1952 {
1953         return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1954 }
1955
1956 static int s5p_mfc_err_dspl_v6(unsigned int err)
1957 {
1958         return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1959 }
1960
1961 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1962 {
1963         return READL(dev->mfc_regs->d_display_frame_width);
1964 }
1965
1966 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1967 {
1968         return READL(dev->mfc_regs->d_display_frame_height);
1969 }
1970
1971 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1972 {
1973         return READL(dev->mfc_regs->d_min_num_dpb);
1974 }
1975
1976 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1977 {
1978         return READL(dev->mfc_regs->d_min_num_mv);
1979 }
1980
1981 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1982 {
1983         return READL(dev->mfc_regs->ret_instance_id);
1984 }
1985
1986 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1987 {
1988         return READL(dev->mfc_regs->e_num_dpb);
1989 }
1990
1991 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1992 {
1993         return READL(dev->mfc_regs->e_stream_size);
1994 }
1995
1996 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1997 {
1998         return READL(dev->mfc_regs->e_slice_type);
1999 }
2000
2001 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
2002 {
2003         return READL(dev->mfc_regs->e_picture_count);
2004 }
2005
2006 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
2007 {
2008         struct s5p_mfc_dev *dev = ctx->dev;
2009         return READL(dev->mfc_regs->d_frame_pack_sei_avail);
2010 }
2011
2012 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
2013 {
2014         return READL(dev->mfc_regs->d_mvc_num_views);
2015 }
2016
2017 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
2018 {
2019         return READL(dev->mfc_regs->d_mvc_view_id);
2020 }
2021
2022 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2023 {
2024         return s5p_mfc_read_info_v6(ctx,
2025                 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2026 }
2027
2028 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2029 {
2030         return s5p_mfc_read_info_v6(ctx,
2031                 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2032 }
2033
2034 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2035 {
2036         return s5p_mfc_read_info_v6(ctx,
2037                 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info1);
2038 }
2039
2040 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2041 {
2042         return s5p_mfc_read_info_v6(ctx,
2043                 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info2);
2044 }
2045
2046 static struct s5p_mfc_regs mfc_regs;
2047
2048 /* Initialize registers for MFC v6 onwards */
2049 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2050 {
2051         memset(&mfc_regs, 0, sizeof(mfc_regs));
2052
2053 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2054 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2055         /* codec common registers */
2056         R(risc_on, S5P_FIMV_RISC_ON_V6);
2057         R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2058         R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2059         R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2060         R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2061         R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2062         R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2063         R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2064         R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2065         R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2066         R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2067         R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2068         R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2069         R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2070         R(error_code, S5P_FIMV_ERROR_CODE_V6);
2071
2072         /* decoder registers */
2073         R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2074         R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2075         R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2076         R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2077         R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2078         R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2079         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2080         R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2081         R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2082         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2083         R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2084         R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2085         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2086         R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2087         R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2088         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2089         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2090         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2091         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2092         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2093         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2094         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2095         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2096         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2097         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2098         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2099         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2100         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2101         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2102         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2103         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2104         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2105         R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2106         R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2107         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2108         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2109         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2110         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2111         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2112         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2113         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2114         R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2115         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2116         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2117
2118         /* encoder registers */
2119         R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2120         R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2121         R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2122         R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2123         R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2124         R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2125         R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2126         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2127         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2128         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2129         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2130         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2131         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2132         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2133         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2134         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2135         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2136         R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2137         R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2138         R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2139         R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2140         R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2141         R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2142         R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2143         R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2144         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2145         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2146         R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2147         R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2148         R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2149         R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2150         R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2151         R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2152         R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2153         R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2154         R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2155         R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2156         R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2157         R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2158         R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2159         R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2160         R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2161         R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2162         R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2163         R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2164         R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2165         R(e_encoded_source_first_plane_addr,
2166                         S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2167         R(e_encoded_source_second_plane_addr,
2168                         S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2169         R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2170         R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2171         R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2172         R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2173         R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2174         R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2175         R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2176         R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2177         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2178         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2179         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2180         R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2181         R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2182         R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2183         R(e_h264_fmo_slice_grp_map_type,
2184                         S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2185         R(e_h264_fmo_num_slice_grp_minus1,
2186                         S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2187         R(e_h264_fmo_slice_grp_change_dir,
2188                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2189         R(e_h264_fmo_slice_grp_change_rate_minus1,
2190                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2191         R(e_h264_fmo_run_length_minus1_0,
2192                         S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2193         R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2194         R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2195         R(e_h264_hierarchical_qp_layer0,
2196                         S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2197         R(e_h264_frame_packing_sei_info,
2198                         S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2199
2200         if (!IS_MFCV7_PLUS(dev))
2201                 goto done;
2202
2203         /* Initialize registers used in MFC v7+ */
2204         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2205         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2206         R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2207         R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2208         R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2209         R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2210         R(e_encoded_source_first_plane_addr,
2211                         S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2212         R(e_encoded_source_second_plane_addr,
2213                         S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2214         R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2215
2216         if (!IS_MFCV8(dev))
2217                 goto done;
2218
2219         /* Initialize registers used in MFC v8 only.
2220          * Also, over-write the registers which have
2221          * a different offset for MFC v8. */
2222         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2223         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2224         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2225         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2226         R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2227         R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2228         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2229         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2230         R(d_first_plane_dpb_stride_size,
2231                         S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2232         R(d_second_plane_dpb_stride_size,
2233                         S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2234         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2235         R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2236         R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2237         R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2238         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2239         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2240         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2241         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2242         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2243         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2244         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2245         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2246         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2247         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2248         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2249         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2250         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2251         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2252         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2253         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2254         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2255         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2256         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2257         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2258         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2259         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2260
2261         /* encoder registers */
2262         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2263         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2264         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2265         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2266         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2267         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2268         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2269         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2270         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2271         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2272         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2273         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2274         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2275
2276 done:
2277         return &mfc_regs;
2278 #undef S5P_MFC_REG_ADDR
2279 #undef R
2280 }
2281
2282 /* Initialize opr function pointers for MFC v6 */
2283 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2284         .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2285         .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2286         .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2287         .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2288         .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2289         .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2290         .alloc_dev_context_buffer =
2291                 s5p_mfc_alloc_dev_context_buffer_v6,
2292         .release_dev_context_buffer =
2293                 s5p_mfc_release_dev_context_buffer_v6,
2294         .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2295         .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2296         .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
2297         .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
2298         .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2299         .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2300         .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2301         .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
2302         .init_decode = s5p_mfc_init_decode_v6,
2303         .init_encode = s5p_mfc_init_encode_v6,
2304         .encode_one_frame = s5p_mfc_encode_one_frame_v6,
2305         .try_run = s5p_mfc_try_run_v6,
2306         .cleanup_queue = s5p_mfc_cleanup_queue_v6,
2307         .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2308         .write_info = s5p_mfc_write_info_v6,
2309         .read_info = s5p_mfc_read_info_v6,
2310         .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2311         .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2312         .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2313         .get_dec_status = s5p_mfc_get_dec_status_v6,
2314         .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2315         .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2316         .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2317         .get_int_reason = s5p_mfc_get_int_reason_v6,
2318         .get_int_err = s5p_mfc_get_int_err_v6,
2319         .err_dec = s5p_mfc_err_dec_v6,
2320         .err_dspl = s5p_mfc_err_dspl_v6,
2321         .get_img_width = s5p_mfc_get_img_width_v6,
2322         .get_img_height = s5p_mfc_get_img_height_v6,
2323         .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2324         .get_mv_count = s5p_mfc_get_mv_count_v6,
2325         .get_inst_no = s5p_mfc_get_inst_no_v6,
2326         .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2327         .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2328         .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2329         .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
2330         .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
2331         .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
2332         .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
2333         .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2334         .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2335         .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2336         .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2337 };
2338
2339 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2340 {
2341         return &s5p_mfc_ops_v6;
2342 }