2 * V4L2 Driver for i.MX3x camera host
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/videodev2.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/vmalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/dma/ipu-dma.h>
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-dev.h>
24 #include <media/videobuf2-dma-contig.h>
25 #include <media/soc_camera.h>
26 #include <media/soc_mediabus.h>
28 #include <linux/platform_data/camera-mx3.h>
29 #include <linux/platform_data/dma-imx.h>
31 #define MX3_CAM_DRV_NAME "mx3-camera"
33 /* CMOS Sensor Interface Registers */
34 #define CSI_REG_START 0x60
36 #define CSI_SENS_CONF (0x60 - CSI_REG_START)
37 #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
38 #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
39 #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
40 #define CSI_TST_CTRL (0x70 - CSI_REG_START)
41 #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
42 #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
43 #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
44 #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
45 #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
47 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
48 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
49 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
50 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
51 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
52 #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
53 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
54 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
55 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
56 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
58 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
59 #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60 #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
62 #define MAX_VIDEO_MEM 16
64 struct mx3_camera_buffer {
65 /* common v4l buffer stuff -- must be first */
67 struct list_head queue;
69 /* One descriptot per scatterlist (per frame) */
70 struct dma_async_tx_descriptor *txd;
72 /* We have to "build" a scatterlist ourselves - one element per frame */
73 struct scatterlist sg;
77 * struct mx3_camera_dev - i.MX3x camera (CSI) object
78 * @dev: camera device, to which the coherent buffer is attached
79 * @icd: currently attached camera sensor
80 * @clk: pointer to clock
81 * @base: remapped register base address
82 * @pdata: platform data
83 * @platform_flags: platform flags
84 * @mclk: master clock frequency in Hz
85 * @capture: list of capture videobuffers
86 * @lock: protects video buffer lists
87 * @active: active video buffer
88 * @idmac_channel: array of pointers to IPU DMAC DMA channels
89 * @soc_host: embedded soc_host object
91 struct mx3_camera_dev {
93 * i.MX3x is only supposed to handle one camera on its Camera Sensor
94 * Interface. If anyone ever builds hardware to enable more than one
95 * camera _simultaneously_, they will have to modify this driver too
101 struct mx3_camera_pdata *pdata;
103 unsigned long platform_flags;
105 u16 width_flags; /* max 15 bits */
107 struct list_head capture;
108 spinlock_t lock; /* Protects video buffer lists */
109 struct mx3_camera_buffer *active;
111 struct vb2_alloc_ctx *alloc_ctx;
112 enum v4l2_field field;
115 /* IDMAC / dmaengine interface */
116 struct idmac_channel *idmac_channel[1]; /* We need one channel */
118 struct soc_camera_host soc_host;
121 struct dma_chan_request {
122 struct mx3_camera_dev *mx3_cam;
126 static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
128 return __raw_readl(mx3->base + reg);
131 static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
133 __raw_writel(value, mx3->base + reg);
136 static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb)
138 return container_of(vb, struct mx3_camera_buffer, vb);
141 /* Called from the IPU IDMAC ISR */
142 static void mx3_cam_dma_done(void *arg)
144 struct idmac_tx_desc *desc = to_tx_desc(arg);
145 struct dma_chan *chan = desc->txd.chan;
146 struct idmac_channel *ichannel = to_idmac_chan(chan);
147 struct mx3_camera_dev *mx3_cam = ichannel->client;
149 dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
150 desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
152 spin_lock(&mx3_cam->lock);
153 if (mx3_cam->active) {
154 struct vb2_buffer *vb = &mx3_cam->active->vb;
155 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
157 list_del_init(&buf->queue);
158 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
159 vb->v4l2_buf.field = mx3_cam->field;
160 vb->v4l2_buf.sequence = mx3_cam->sequence++;
161 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
164 if (list_empty(&mx3_cam->capture)) {
165 mx3_cam->active = NULL;
166 spin_unlock(&mx3_cam->lock);
169 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
175 mx3_cam->active = list_entry(mx3_cam->capture.next,
176 struct mx3_camera_buffer, queue);
177 spin_unlock(&mx3_cam->lock);
181 * Videobuf operations
185 * Calculate the __buffer__ (not data) size and number of buffers.
187 static int mx3_videobuf_setup(struct vb2_queue *vq,
188 const struct v4l2_format *fmt,
189 unsigned int *count, unsigned int *num_planes,
190 unsigned int sizes[], void *alloc_ctxs[])
192 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
193 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
194 struct mx3_camera_dev *mx3_cam = ici->priv;
196 if (!mx3_cam->idmac_channel[0])
200 const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd,
201 fmt->fmt.pix.pixelformat);
202 unsigned int bytes_per_line;
208 ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width,
213 bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret);
215 ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line,
216 fmt->fmt.pix.height);
220 sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret);
222 /* Called from VIDIOC_REQBUFS or in compatibility mode */
223 sizes[0] = icd->sizeimage;
226 alloc_ctxs[0] = mx3_cam->alloc_ctx;
228 if (!vq->num_buffers)
229 mx3_cam->sequence = 0;
234 /* If *num_planes != 0, we have already verified *count. */
236 sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024)
237 *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) /
245 static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
247 /* Add more formats as need arises and test possibilities appear... */
249 case V4L2_PIX_FMT_RGB24:
250 return IPU_PIX_FMT_RGB24;
251 case V4L2_PIX_FMT_UYVY:
252 case V4L2_PIX_FMT_RGB565:
254 return IPU_PIX_FMT_GENERIC;
258 static void mx3_videobuf_queue(struct vb2_buffer *vb)
260 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
262 struct mx3_camera_dev *mx3_cam = ici->priv;
263 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
264 struct scatterlist *sg = &buf->sg;
265 struct dma_async_tx_descriptor *txd;
266 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
267 struct idmac_video_param *video = &ichan->params.video;
268 const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt;
272 new_size = icd->sizeimage;
274 if (vb2_plane_size(vb, 0) < new_size) {
275 dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n",
276 vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size);
281 sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0);
282 sg_dma_len(sg) = new_size;
284 txd = dmaengine_prep_slave_sg(
285 &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM,
290 txd->callback_param = txd;
291 txd->callback = mx3_cam_dma_done;
298 vb2_set_plane_payload(vb, 0, new_size);
300 /* This is the configuration of one sg-element */
301 video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc);
303 if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) {
305 * If the IPU DMA channel is configured to transfer generic
306 * 8-bit data, we have to set up the geometry parameters
307 * correctly, according to the current pixel format. The DMA
308 * horizontal parameters in this case are expressed in bytes,
311 video->out_width = icd->bytesperline;
312 video->out_height = icd->user_height;
313 video->out_stride = icd->bytesperline;
316 * For IPU known formats the pixel unit will be managed
317 * successfully by the IPU code
319 video->out_width = icd->user_width;
320 video->out_height = icd->user_height;
321 video->out_stride = icd->user_width;
325 /* helps to see what DMA actually has written */
326 if (vb2_plane_vaddr(vb, 0))
327 memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
330 spin_lock_irq(&mx3_cam->lock);
331 list_add_tail(&buf->queue, &mx3_cam->capture);
333 if (!mx3_cam->active)
334 mx3_cam->active = buf;
336 spin_unlock_irq(&mx3_cam->lock);
338 cookie = txd->tx_submit(txd);
339 dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n",
340 cookie, sg_dma_address(&buf->sg));
345 spin_lock_irq(&mx3_cam->lock);
348 list_del_init(&buf->queue);
350 if (mx3_cam->active == buf)
351 mx3_cam->active = NULL;
353 spin_unlock_irq(&mx3_cam->lock);
355 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
358 static void mx3_videobuf_release(struct vb2_buffer *vb)
360 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
361 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
362 struct mx3_camera_dev *mx3_cam = ici->priv;
363 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
364 struct dma_async_tx_descriptor *txd = buf->txd;
368 "Release%s DMA 0x%08x, queue %sempty\n",
369 mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
370 list_empty(&buf->queue) ? "" : "not ");
372 spin_lock_irqsave(&mx3_cam->lock, flags);
374 if (mx3_cam->active == buf)
375 mx3_cam->active = NULL;
377 /* Doesn't hurt also if the list is empty */
378 list_del_init(&buf->queue);
382 if (mx3_cam->idmac_channel[0])
386 spin_unlock_irqrestore(&mx3_cam->lock, flags);
388 mx3_cam->buf_total -= vb2_plane_size(vb, 0);
391 static int mx3_videobuf_init(struct vb2_buffer *vb)
393 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
394 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
395 struct mx3_camera_dev *mx3_cam = ici->priv;
396 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
399 /* This is for locking debugging only */
400 INIT_LIST_HEAD(&buf->queue);
401 sg_init_table(&buf->sg, 1);
403 mx3_cam->buf_total += vb2_plane_size(vb, 0);
409 static void mx3_stop_streaming(struct vb2_queue *q)
411 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
413 struct mx3_camera_dev *mx3_cam = ici->priv;
414 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
415 struct mx3_camera_buffer *buf, *tmp;
419 dmaengine_pause(&ichan->dma_chan);
421 spin_lock_irqsave(&mx3_cam->lock, flags);
423 mx3_cam->active = NULL;
425 list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
426 list_del_init(&buf->queue);
427 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
430 spin_unlock_irqrestore(&mx3_cam->lock, flags);
433 static struct vb2_ops mx3_videobuf_ops = {
434 .queue_setup = mx3_videobuf_setup,
435 .buf_queue = mx3_videobuf_queue,
436 .buf_cleanup = mx3_videobuf_release,
437 .buf_init = mx3_videobuf_init,
438 .wait_prepare = vb2_ops_wait_prepare,
439 .wait_finish = vb2_ops_wait_finish,
440 .stop_streaming = mx3_stop_streaming,
443 static int mx3_camera_init_videobuf(struct vb2_queue *q,
444 struct soc_camera_device *icd)
446 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
448 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
449 q->io_modes = VB2_MMAP | VB2_USERPTR;
451 q->ops = &mx3_videobuf_ops;
452 q->mem_ops = &vb2_dma_contig_memops;
453 q->buf_struct_size = sizeof(struct mx3_camera_buffer);
454 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
455 q->lock = &ici->host_lock;
457 return vb2_queue_init(q);
460 /* First part of ipu_csi_init_interface() */
461 static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam)
466 /* Set default size: ipu_csi_set_window_size() */
467 csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
468 /* ...and position to 0:0: ipu_csi_set_window_pos() */
469 conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
470 csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
472 /* We use only gated clock synchronisation mode so far */
473 conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
475 /* Set generic data, platform-biggest bus-width */
476 conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
478 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
479 conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
480 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
481 conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
482 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
483 conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
484 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
485 conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
487 if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
488 conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
489 if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
490 conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
491 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
492 conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
493 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
494 conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
495 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
496 conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
497 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
498 conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
500 /* ipu_csi_init_interface() */
501 csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
503 clk_prepare_enable(mx3_cam->clk);
504 rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
505 dev_dbg(mx3_cam->soc_host.v4l2_dev.dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
507 clk_set_rate(mx3_cam->clk, rate);
510 static int mx3_camera_add_device(struct soc_camera_device *icd)
512 dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n",
518 static void mx3_camera_remove_device(struct soc_camera_device *icd)
520 dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n",
524 /* Called with .host_lock held */
525 static int mx3_camera_clock_start(struct soc_camera_host *ici)
527 struct mx3_camera_dev *mx3_cam = ici->priv;
529 mx3_camera_activate(mx3_cam);
531 mx3_cam->buf_total = 0;
536 /* Called with .host_lock held */
537 static void mx3_camera_clock_stop(struct soc_camera_host *ici)
539 struct mx3_camera_dev *mx3_cam = ici->priv;
540 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
543 dma_release_channel(&(*ichan)->dma_chan);
547 clk_disable_unprepare(mx3_cam->clk);
550 static int test_platform_param(struct mx3_camera_dev *mx3_cam,
551 unsigned char buswidth, unsigned long *flags)
554 * If requested data width is supported by the platform, use it or any
555 * possible lower value - i.MX31 is smart enough to shift bits
557 if (buswidth > fls(mx3_cam->width_flags))
561 * Platform specified synchronization and pixel clock polarities are
562 * only a recommendation and are only used during probing. MX3x
563 * camera interface only works in master mode, i.e., uses HSYNC and
564 * VSYNC signals from the sensor
566 *flags = V4L2_MBUS_MASTER |
567 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
568 V4L2_MBUS_HSYNC_ACTIVE_LOW |
569 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
570 V4L2_MBUS_VSYNC_ACTIVE_LOW |
571 V4L2_MBUS_PCLK_SAMPLE_RISING |
572 V4L2_MBUS_PCLK_SAMPLE_FALLING |
573 V4L2_MBUS_DATA_ACTIVE_HIGH |
574 V4L2_MBUS_DATA_ACTIVE_LOW;
579 static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
580 const unsigned int depth)
582 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
583 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
584 struct mx3_camera_dev *mx3_cam = ici->priv;
585 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
586 unsigned long bus_flags, common_flags;
587 int ret = test_platform_param(mx3_cam, depth, &bus_flags);
589 dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret);
594 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
596 common_flags = soc_mbus_config_compatible(&cfg,
599 dev_warn(icd->parent,
600 "Flags incompatible: camera 0x%x, host 0x%lx\n",
601 cfg.flags, bus_flags);
604 } else if (ret != -ENOIOCTLCMD) {
611 static bool chan_filter(struct dma_chan *chan, void *arg)
613 struct dma_chan_request *rq = arg;
614 struct mx3_camera_pdata *pdata;
616 if (!imx_dma_is_ipu(chan))
622 pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
624 return rq->id == chan->chan_id &&
625 pdata->dma_dev == chan->device->dev;
628 static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
630 .fourcc = V4L2_PIX_FMT_SBGGR8,
631 .name = "Bayer BGGR (sRGB) 8 bit",
632 .bits_per_sample = 8,
633 .packing = SOC_MBUS_PACKING_NONE,
634 .order = SOC_MBUS_ORDER_LE,
635 .layout = SOC_MBUS_LAYOUT_PACKED,
637 .fourcc = V4L2_PIX_FMT_GREY,
638 .name = "Monochrome 8 bit",
639 .bits_per_sample = 8,
640 .packing = SOC_MBUS_PACKING_NONE,
641 .order = SOC_MBUS_ORDER_LE,
642 .layout = SOC_MBUS_LAYOUT_PACKED,
646 /* This will be corrected as we get more formats */
647 static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
649 return fmt->packing == SOC_MBUS_PACKING_NONE ||
650 (fmt->bits_per_sample == 8 &&
651 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
652 (fmt->bits_per_sample > 8 &&
653 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
656 static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
657 struct soc_camera_format_xlate *xlate)
659 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
660 struct device *dev = icd->parent;
661 int formats = 0, ret;
663 const struct soc_mbus_pixelfmt *fmt;
665 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
667 /* No more formats */
670 fmt = soc_mbus_get_fmtdesc(code);
672 dev_warn(icd->parent,
673 "Unsupported format code #%u: 0x%x\n", idx, code);
677 /* This also checks support for the requested bits-per-sample */
678 ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
683 case MEDIA_BUS_FMT_SBGGR10_1X10:
686 xlate->host_fmt = &mx3_camera_formats[0];
689 dev_dbg(dev, "Providing format %s using code 0x%x\n",
690 mx3_camera_formats[0].name, code);
693 case MEDIA_BUS_FMT_Y10_1X10:
696 xlate->host_fmt = &mx3_camera_formats[1];
699 dev_dbg(dev, "Providing format %s using code 0x%x\n",
700 mx3_camera_formats[1].name, code);
704 if (!mx3_camera_packing_supported(fmt))
708 /* Generic pass-through */
711 xlate->host_fmt = fmt;
713 dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n",
714 (fmt->fourcc >> (0*8)) & 0xFF,
715 (fmt->fourcc >> (1*8)) & 0xFF,
716 (fmt->fourcc >> (2*8)) & 0xFF,
717 (fmt->fourcc >> (3*8)) & 0xFF);
724 static void configure_geometry(struct mx3_camera_dev *mx3_cam,
725 unsigned int width, unsigned int height,
726 const struct soc_mbus_pixelfmt *fmt)
728 u32 ctrl, width_field, height_field;
730 if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
732 * As the CSI will be configured to output BAYER, here
733 * the width parameter count the number of samples to
734 * capture to complete the whole image width.
736 unsigned int num, den;
737 int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
739 width = width * num / den;
742 /* Setup frame size - this cannot be changed on-the-fly... */
743 width_field = width - 1;
744 height_field = height - 1;
745 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
747 csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
748 csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
750 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
752 /* ...and position */
753 ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
754 /* Sensor does the cropping */
755 csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
758 static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
761 struct dma_chan *chan;
762 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
763 /* We have to use IDMAC_IC_7 for Bayer / generic data */
764 struct dma_chan_request rq = {.mx3_cam = mx3_cam,
768 dma_cap_set(DMA_SLAVE, mask);
769 dma_cap_set(DMA_PRIVATE, mask);
770 chan = dma_request_channel(mask, chan_filter, &rq);
774 *ichan = to_idmac_chan(chan);
775 (*ichan)->client = mx3_cam;
781 * FIXME: learn to use stride != width, then we can keep stride properly aligned
782 * and support arbitrary (even) widths.
784 static inline void stride_align(__u32 *width)
786 if (ALIGN(*width, 8) < 4096)
787 *width = ALIGN(*width, 8);
789 *width = *width & ~7;
793 * As long as we don't implement host-side cropping and scaling, we can use
794 * default g_crop and cropcap from soc_camera.c
796 static int mx3_camera_set_crop(struct soc_camera_device *icd,
797 const struct v4l2_crop *a)
799 struct v4l2_crop a_writable = *a;
800 struct v4l2_rect *rect = &a_writable.c;
801 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
802 struct mx3_camera_dev *mx3_cam = ici->priv;
803 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
804 struct v4l2_mbus_framefmt mf;
807 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
808 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
810 ret = v4l2_subdev_call(sd, video, s_crop, a);
814 /* The capture device might have changed its output sizes */
815 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
819 if (mf.code != icd->current_fmt->code)
823 /* Ouch! We can only handle 8-byte aligned width... */
824 stride_align(&mf.width);
825 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
830 if (mf.width != icd->user_width || mf.height != icd->user_height)
831 configure_geometry(mx3_cam, mf.width, mf.height,
832 icd->current_fmt->host_fmt);
834 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
835 mf.width, mf.height);
837 icd->user_width = mf.width;
838 icd->user_height = mf.height;
843 static int mx3_camera_set_fmt(struct soc_camera_device *icd,
844 struct v4l2_format *f)
846 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
847 struct mx3_camera_dev *mx3_cam = ici->priv;
848 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
849 const struct soc_camera_format_xlate *xlate;
850 struct v4l2_pix_format *pix = &f->fmt.pix;
851 struct v4l2_mbus_framefmt mf;
854 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
856 dev_warn(icd->parent, "Format %x not found\n",
861 stride_align(&pix->width);
862 dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height);
865 * Might have to perform a complete interface initialisation like in
866 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
870 configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
872 mf.width = pix->width;
873 mf.height = pix->height;
874 mf.field = pix->field;
875 mf.colorspace = pix->colorspace;
876 mf.code = xlate->code;
878 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
882 if (mf.code != xlate->code)
885 if (!mx3_cam->idmac_channel[0]) {
886 ret = acquire_dma_channel(mx3_cam);
891 pix->width = mf.width;
892 pix->height = mf.height;
893 pix->field = mf.field;
894 mx3_cam->field = mf.field;
895 pix->colorspace = mf.colorspace;
896 icd->current_fmt = xlate;
898 dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height);
903 static int mx3_camera_try_fmt(struct soc_camera_device *icd,
904 struct v4l2_format *f)
906 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
907 const struct soc_camera_format_xlate *xlate;
908 struct v4l2_pix_format *pix = &f->fmt.pix;
909 struct v4l2_mbus_framefmt mf;
910 __u32 pixfmt = pix->pixelformat;
913 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
914 if (pixfmt && !xlate) {
915 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
919 /* limit to MX3 hardware capabilities */
920 if (pix->height > 4096)
922 if (pix->width > 4096)
925 /* limit to sensor capabilities */
926 mf.width = pix->width;
927 mf.height = pix->height;
928 mf.field = pix->field;
929 mf.colorspace = pix->colorspace;
930 mf.code = xlate->code;
932 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
936 pix->width = mf.width;
937 pix->height = mf.height;
938 pix->colorspace = mf.colorspace;
942 pix->field = V4L2_FIELD_NONE;
944 case V4L2_FIELD_NONE:
947 dev_err(icd->parent, "Field type %d unsupported.\n",
955 static int mx3_camera_reqbufs(struct soc_camera_device *icd,
956 struct v4l2_requestbuffers *p)
961 static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
963 struct soc_camera_device *icd = file->private_data;
965 return vb2_poll(&icd->vb2_vidq, file, pt);
968 static int mx3_camera_querycap(struct soc_camera_host *ici,
969 struct v4l2_capability *cap)
971 /* cap->name is set by the firendly caller:-> */
972 strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
973 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
974 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
979 static int mx3_camera_set_bus_param(struct soc_camera_device *icd)
981 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
982 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
983 struct mx3_camera_dev *mx3_cam = ici->priv;
984 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
985 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
986 unsigned long bus_flags, common_flags;
988 const struct soc_mbus_pixelfmt *fmt;
991 const struct soc_camera_format_xlate *xlate;
992 struct device *dev = icd->parent;
994 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
998 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1000 dev_warn(dev, "Format %x not found\n", pixfmt);
1004 buswidth = fmt->bits_per_sample;
1005 ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
1007 dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
1012 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1014 common_flags = soc_mbus_config_compatible(&cfg,
1016 if (!common_flags) {
1017 dev_warn(icd->parent,
1018 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1019 cfg.flags, bus_flags);
1022 } else if (ret != -ENOIOCTLCMD) {
1025 common_flags = bus_flags;
1028 dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n",
1029 cfg.flags, bus_flags, common_flags);
1031 /* Make choices, based on platform preferences */
1032 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1033 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1034 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
1035 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1037 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1040 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1041 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1042 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
1043 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1045 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1048 if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) &&
1049 (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) {
1050 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
1051 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH;
1053 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW;
1056 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1057 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1058 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
1059 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1061 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1064 cfg.flags = common_flags;
1065 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1066 if (ret < 0 && ret != -ENOIOCTLCMD) {
1067 dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n",
1073 * So far only gated clock mode is supported. Add a line
1074 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1075 * below and select the required mode when supporting other
1076 * synchronisation protocols.
1078 sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
1079 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
1080 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
1081 (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
1082 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
1083 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
1084 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
1086 /* TODO: Support RGB and YUV formats */
1088 /* This has been set in mx3_camera_activate(), but we clear it above */
1089 sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
1091 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1092 sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
1093 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1094 sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
1095 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1096 sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
1097 if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)
1098 sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
1100 /* Just do what we're asked to do */
1101 switch (xlate->host_fmt->bits_per_sample) {
1103 dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1106 dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1109 dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1113 * Actually it can only be 15 now, default is just to silence
1117 dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1120 csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
1122 dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
1127 static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
1128 .owner = THIS_MODULE,
1129 .add = mx3_camera_add_device,
1130 .remove = mx3_camera_remove_device,
1131 .clock_start = mx3_camera_clock_start,
1132 .clock_stop = mx3_camera_clock_stop,
1133 .set_crop = mx3_camera_set_crop,
1134 .set_fmt = mx3_camera_set_fmt,
1135 .try_fmt = mx3_camera_try_fmt,
1136 .get_formats = mx3_camera_get_formats,
1137 .init_videobuf2 = mx3_camera_init_videobuf,
1138 .reqbufs = mx3_camera_reqbufs,
1139 .poll = mx3_camera_poll,
1140 .querycap = mx3_camera_querycap,
1141 .set_bus_param = mx3_camera_set_bus_param,
1144 static int mx3_camera_probe(struct platform_device *pdev)
1146 struct mx3_camera_pdata *pdata = pdev->dev.platform_data;
1147 struct mx3_camera_dev *mx3_cam;
1148 struct resource *res;
1151 struct soc_camera_host *soc_host;
1153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 base = devm_ioremap_resource(&pdev->dev, res);
1156 return PTR_ERR(base);
1161 mx3_cam = devm_kzalloc(&pdev->dev, sizeof(*mx3_cam), GFP_KERNEL);
1163 dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
1167 mx3_cam->clk = devm_clk_get(&pdev->dev, NULL);
1168 if (IS_ERR(mx3_cam->clk))
1169 return PTR_ERR(mx3_cam->clk);
1171 mx3_cam->pdata = pdata;
1172 mx3_cam->platform_flags = pdata->flags;
1173 if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) {
1175 * Platform hasn't set available data widths. This is bad.
1176 * Warn and use a default.
1178 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1179 "data widths, using default 8 bit\n");
1180 mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
1182 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
1183 mx3_cam->width_flags = 1 << 3;
1184 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
1185 mx3_cam->width_flags |= 1 << 7;
1186 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
1187 mx3_cam->width_flags |= 1 << 9;
1188 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
1189 mx3_cam->width_flags |= 1 << 14;
1191 mx3_cam->mclk = pdata->mclk_10khz * 10000;
1192 if (!mx3_cam->mclk) {
1193 dev_warn(&pdev->dev,
1194 "mclk_10khz == 0! Please, fix your platform data. "
1195 "Using default 20MHz\n");
1196 mx3_cam->mclk = 20000000;
1199 /* list of video-buffers */
1200 INIT_LIST_HEAD(&mx3_cam->capture);
1201 spin_lock_init(&mx3_cam->lock);
1203 mx3_cam->base = base;
1205 soc_host = &mx3_cam->soc_host;
1206 soc_host->drv_name = MX3_CAM_DRV_NAME;
1207 soc_host->ops = &mx3_soc_camera_host_ops;
1208 soc_host->priv = mx3_cam;
1209 soc_host->v4l2_dev.dev = &pdev->dev;
1210 soc_host->nr = pdev->id;
1212 mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1213 if (IS_ERR(mx3_cam->alloc_ctx))
1214 return PTR_ERR(mx3_cam->alloc_ctx);
1216 if (pdata->asd_sizes) {
1217 soc_host->asd = pdata->asd;
1218 soc_host->asd_sizes = pdata->asd_sizes;
1221 err = soc_camera_host_register(soc_host);
1225 /* IDMAC interface */
1231 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1235 static int mx3_camera_remove(struct platform_device *pdev)
1237 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1238 struct mx3_camera_dev *mx3_cam = container_of(soc_host,
1239 struct mx3_camera_dev, soc_host);
1241 soc_camera_host_unregister(soc_host);
1244 * The channel has either not been allocated,
1245 * or should have been released
1247 if (WARN_ON(mx3_cam->idmac_channel[0]))
1248 dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
1250 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1257 static struct platform_driver mx3_camera_driver = {
1259 .name = MX3_CAM_DRV_NAME,
1261 .probe = mx3_camera_probe,
1262 .remove = mx3_camera_remove,
1265 module_platform_driver(mx3_camera_driver);
1267 MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1268 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1269 MODULE_LICENSE("GPL v2");
1270 MODULE_VERSION("0.2.3");
1271 MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);