2 * Copyright (c) 2013 Texas Instruments Inc.
4 * David Griego, <dagriego@biglakesoftware.com>
5 * Dale Farnsworth, <dale@farnsworth.org>
6 * Archit Taneja, <archit@ti.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
13 #ifndef __TI_VPE_REGS_H
14 #define __TI_VPE_REGS_H
16 /* VPE register offsets and field selectors */
18 /* VPE top level regs */
19 #define VPE_PID 0x0000
20 #define VPE_PID_MINOR_MASK 0x3f
21 #define VPE_PID_MINOR_SHIFT 0
22 #define VPE_PID_CUSTOM_MASK 0x03
23 #define VPE_PID_CUSTOM_SHIFT 6
24 #define VPE_PID_MAJOR_MASK 0x07
25 #define VPE_PID_MAJOR_SHIFT 8
26 #define VPE_PID_RTL_MASK 0x1f
27 #define VPE_PID_RTL_SHIFT 11
28 #define VPE_PID_FUNC_MASK 0xfff
29 #define VPE_PID_FUNC_SHIFT 16
30 #define VPE_PID_SCHEME_MASK 0x03
31 #define VPE_PID_SCHEME_SHIFT 30
33 #define VPE_SYSCONFIG 0x0010
34 #define VPE_SYSCONFIG_IDLE_MASK 0x03
35 #define VPE_SYSCONFIG_IDLE_SHIFT 2
36 #define VPE_SYSCONFIG_STANDBY_MASK 0x03
37 #define VPE_SYSCONFIG_STANDBY_SHIFT 4
38 #define VPE_FORCE_IDLE_MODE 0
39 #define VPE_NO_IDLE_MODE 1
40 #define VPE_SMART_IDLE_MODE 2
41 #define VPE_SMART_IDLE_WAKEUP_MODE 3
42 #define VPE_FORCE_STANDBY_MODE 0
43 #define VPE_NO_STANDBY_MODE 1
44 #define VPE_SMART_STANDBY_MODE 2
45 #define VPE_SMART_STANDBY_WAKEUP_MODE 3
47 #define VPE_INT0_STATUS0_RAW_SET 0x0020
48 #define VPE_INT0_STATUS0_RAW VPE_INT0_STATUS0_RAW_SET
49 #define VPE_INT0_STATUS0_CLR 0x0028
50 #define VPE_INT0_STATUS0 VPE_INT0_STATUS0_CLR
51 #define VPE_INT0_ENABLE0_SET 0x0030
52 #define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET
53 #define VPE_INT0_ENABLE0_CLR 0x0038
54 #define VPE_INT0_LIST0_COMPLETE (1 << 0)
55 #define VPE_INT0_LIST0_NOTIFY (1 << 1)
56 #define VPE_INT0_LIST1_COMPLETE (1 << 2)
57 #define VPE_INT0_LIST1_NOTIFY (1 << 3)
58 #define VPE_INT0_LIST2_COMPLETE (1 << 4)
59 #define VPE_INT0_LIST2_NOTIFY (1 << 5)
60 #define VPE_INT0_LIST3_COMPLETE (1 << 6)
61 #define VPE_INT0_LIST3_NOTIFY (1 << 7)
62 #define VPE_INT0_LIST4_COMPLETE (1 << 8)
63 #define VPE_INT0_LIST4_NOTIFY (1 << 9)
64 #define VPE_INT0_LIST5_COMPLETE (1 << 10)
65 #define VPE_INT0_LIST5_NOTIFY (1 << 11)
66 #define VPE_INT0_LIST6_COMPLETE (1 << 12)
67 #define VPE_INT0_LIST6_NOTIFY (1 << 13)
68 #define VPE_INT0_LIST7_COMPLETE (1 << 14)
69 #define VPE_INT0_LIST7_NOTIFY (1 << 15)
70 #define VPE_INT0_DESCRIPTOR (1 << 16)
71 #define VPE_DEI_FMD_INT (1 << 18)
73 #define VPE_INT0_STATUS1_RAW_SET 0x0024
74 #define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET
75 #define VPE_INT0_STATUS1_CLR 0x002c
76 #define VPE_INT0_STATUS1 VPE_INT0_STATUS1_CLR
77 #define VPE_INT0_ENABLE1_SET 0x0034
78 #define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET
79 #define VPE_INT0_ENABLE1_CLR 0x003c
80 #define VPE_INT0_CHANNEL_GROUP0 (1 << 0)
81 #define VPE_INT0_CHANNEL_GROUP1 (1 << 1)
82 #define VPE_INT0_CHANNEL_GROUP2 (1 << 2)
83 #define VPE_INT0_CHANNEL_GROUP3 (1 << 3)
84 #define VPE_INT0_CHANNEL_GROUP4 (1 << 4)
85 #define VPE_INT0_CHANNEL_GROUP5 (1 << 5)
86 #define VPE_INT0_CLIENT (1 << 7)
87 #define VPE_DEI_ERROR_INT (1 << 16)
88 #define VPE_DS1_UV_ERROR_INT (1 << 22)
90 #define VPE_INTC_EOI 0x00a0
92 #define VPE_CLK_ENABLE 0x0100
93 #define VPE_VPEDMA_CLK_ENABLE (1 << 0)
94 #define VPE_DATA_PATH_CLK_ENABLE (1 << 1)
96 #define VPE_CLK_RESET 0x0104
97 #define VPE_VPDMA_CLK_RESET_MASK 0x1
98 #define VPE_VPDMA_CLK_RESET_SHIFT 0
99 #define VPE_DATA_PATH_CLK_RESET_MASK 0x1
100 #define VPE_DATA_PATH_CLK_RESET_SHIFT 1
101 #define VPE_MAIN_RESET_MASK 0x1
102 #define VPE_MAIN_RESET_SHIFT 31
104 #define VPE_CLK_FORMAT_SELECT 0x010c
105 #define VPE_CSC_SRC_SELECT_MASK 0x03
106 #define VPE_CSC_SRC_SELECT_SHIFT 0
107 #define VPE_RGB_OUT_SELECT (1 << 8)
108 #define VPE_DS_SRC_SELECT_MASK 0x07
109 #define VPE_DS_SRC_SELECT_SHIFT 9
110 #define VPE_DS_BYPASS (1 << 16)
111 #define VPE_COLOR_SEPARATE_422 (1 << 18)
113 #define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT)
114 #define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT)
116 #define VPE_CLK_RANGE_MAP 0x011c
117 #define VPE_RANGE_RANGE_MAP_Y_MASK 0x07
118 #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0
119 #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07
120 #define VPE_RANGE_RANGE_MAP_UV_SHIFT 3
121 #define VPE_RANGE_MAP_ON (1 << 6)
122 #define VPE_RANGE_REDUCTION_ON (1 << 28)
124 /* VPE chrominance upsampler regs */
125 #define VPE_US1_R0 0x0304
126 #define VPE_US2_R0 0x0404
127 #define VPE_US3_R0 0x0504
128 #define VPE_US_C1_MASK 0x3fff
129 #define VPE_US_C1_SHIFT 2
130 #define VPE_US_C0_MASK 0x3fff
131 #define VPE_US_C0_SHIFT 18
132 #define VPE_US_MODE_MASK 0x03
133 #define VPE_US_MODE_SHIFT 16
134 #define VPE_ANCHOR_FID0_C1_MASK 0x3fff
135 #define VPE_ANCHOR_FID0_C1_SHIFT 2
136 #define VPE_ANCHOR_FID0_C0_MASK 0x3fff
137 #define VPE_ANCHOR_FID0_C0_SHIFT 18
139 #define VPE_US1_R1 0x0308
140 #define VPE_US2_R1 0x0408
141 #define VPE_US3_R1 0x0508
142 #define VPE_ANCHOR_FID0_C3_MASK 0x3fff
143 #define VPE_ANCHOR_FID0_C3_SHIFT 2
144 #define VPE_ANCHOR_FID0_C2_MASK 0x3fff
145 #define VPE_ANCHOR_FID0_C2_SHIFT 18
147 #define VPE_US1_R2 0x030c
148 #define VPE_US2_R2 0x040c
149 #define VPE_US3_R2 0x050c
150 #define VPE_INTERP_FID0_C1_MASK 0x3fff
151 #define VPE_INTERP_FID0_C1_SHIFT 2
152 #define VPE_INTERP_FID0_C0_MASK 0x3fff
153 #define VPE_INTERP_FID0_C0_SHIFT 18
155 #define VPE_US1_R3 0x0310
156 #define VPE_US2_R3 0x0410
157 #define VPE_US3_R3 0x0510
158 #define VPE_INTERP_FID0_C3_MASK 0x3fff
159 #define VPE_INTERP_FID0_C3_SHIFT 2
160 #define VPE_INTERP_FID0_C2_MASK 0x3fff
161 #define VPE_INTERP_FID0_C2_SHIFT 18
163 #define VPE_US1_R4 0x0314
164 #define VPE_US2_R4 0x0414
165 #define VPE_US3_R4 0x0514
166 #define VPE_ANCHOR_FID1_C1_MASK 0x3fff
167 #define VPE_ANCHOR_FID1_C1_SHIFT 2
168 #define VPE_ANCHOR_FID1_C0_MASK 0x3fff
169 #define VPE_ANCHOR_FID1_C0_SHIFT 18
171 #define VPE_US1_R5 0x0318
172 #define VPE_US2_R5 0x0418
173 #define VPE_US3_R5 0x0518
174 #define VPE_ANCHOR_FID1_C3_MASK 0x3fff
175 #define VPE_ANCHOR_FID1_C3_SHIFT 2
176 #define VPE_ANCHOR_FID1_C2_MASK 0x3fff
177 #define VPE_ANCHOR_FID1_C2_SHIFT 18
179 #define VPE_US1_R6 0x031c
180 #define VPE_US2_R6 0x041c
181 #define VPE_US3_R6 0x051c
182 #define VPE_INTERP_FID1_C1_MASK 0x3fff
183 #define VPE_INTERP_FID1_C1_SHIFT 2
184 #define VPE_INTERP_FID1_C0_MASK 0x3fff
185 #define VPE_INTERP_FID1_C0_SHIFT 18
187 #define VPE_US1_R7 0x0320
188 #define VPE_US2_R7 0x0420
189 #define VPE_US3_R7 0x0520
190 #define VPE_INTERP_FID0_C3_MASK 0x3fff
191 #define VPE_INTERP_FID0_C3_SHIFT 2
192 #define VPE_INTERP_FID0_C2_MASK 0x3fff
193 #define VPE_INTERP_FID0_C2_SHIFT 18
195 /* VPE de-interlacer regs */
196 #define VPE_DEI_FRAME_SIZE 0x0600
197 #define VPE_DEI_WIDTH_MASK 0x07ff
198 #define VPE_DEI_WIDTH_SHIFT 0
199 #define VPE_DEI_HEIGHT_MASK 0x07ff
200 #define VPE_DEI_HEIGHT_SHIFT 16
201 #define VPE_DEI_INTERLACE_BYPASS (1 << 29)
202 #define VPE_DEI_FIELD_FLUSH (1 << 30)
203 #define VPE_DEI_PROGRESSIVE (1 << 31)
205 #define VPE_MDT_BYPASS 0x0604
206 #define VPE_MDT_TEMPMAX_BYPASS (1 << 0)
207 #define VPE_MDT_SPATMAX_BYPASS (1 << 1)
209 #define VPE_MDT_SF_THRESHOLD 0x0608
210 #define VPE_MDT_SF_SC_THR1_MASK 0xff
211 #define VPE_MDT_SF_SC_THR1_SHIFT 0
212 #define VPE_MDT_SF_SC_THR2_MASK 0xff
213 #define VPE_MDT_SF_SC_THR2_SHIFT 0
214 #define VPE_MDT_SF_SC_THR3_MASK 0xff
215 #define VPE_MDT_SF_SC_THR3_SHIFT 0
217 #define VPE_EDI_CONFIG 0x060c
218 #define VPE_EDI_INP_MODE_MASK 0x03
219 #define VPE_EDI_INP_MODE_SHIFT 0
220 #define VPE_EDI_ENABLE_3D (1 << 2)
221 #define VPE_EDI_ENABLE_CHROMA_3D (1 << 3)
222 #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff
223 #define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8
224 #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff
225 #define VPE_EDI_DIR_COR_LOWER_THR_SHIFT 16
226 #define VPE_EDI_COR_SCALE_FACTOR_MASK 0xff
227 #define VPE_EDI_COR_SCALE_FACTOR_SHIFT 23
229 #define VPE_DEI_EDI_LUT_R0 0x0610
230 #define VPE_EDI_LUT0_MASK 0x1f
231 #define VPE_EDI_LUT0_SHIFT 0
232 #define VPE_EDI_LUT1_MASK 0x1f
233 #define VPE_EDI_LUT1_SHIFT 8
234 #define VPE_EDI_LUT2_MASK 0x1f
235 #define VPE_EDI_LUT2_SHIFT 16
236 #define VPE_EDI_LUT3_MASK 0x1f
237 #define VPE_EDI_LUT3_SHIFT 24
239 #define VPE_DEI_EDI_LUT_R1 0x0614
240 #define VPE_EDI_LUT0_MASK 0x1f
241 #define VPE_EDI_LUT0_SHIFT 0
242 #define VPE_EDI_LUT1_MASK 0x1f
243 #define VPE_EDI_LUT1_SHIFT 8
244 #define VPE_EDI_LUT2_MASK 0x1f
245 #define VPE_EDI_LUT2_SHIFT 16
246 #define VPE_EDI_LUT3_MASK 0x1f
247 #define VPE_EDI_LUT3_SHIFT 24
249 #define VPE_DEI_EDI_LUT_R2 0x0618
250 #define VPE_EDI_LUT4_MASK 0x1f
251 #define VPE_EDI_LUT4_SHIFT 0
252 #define VPE_EDI_LUT5_MASK 0x1f
253 #define VPE_EDI_LUT5_SHIFT 8
254 #define VPE_EDI_LUT6_MASK 0x1f
255 #define VPE_EDI_LUT6_SHIFT 16
256 #define VPE_EDI_LUT7_MASK 0x1f
257 #define VPE_EDI_LUT7_SHIFT 24
259 #define VPE_DEI_EDI_LUT_R3 0x061c
260 #define VPE_EDI_LUT8_MASK 0x1f
261 #define VPE_EDI_LUT8_SHIFT 0
262 #define VPE_EDI_LUT9_MASK 0x1f
263 #define VPE_EDI_LUT9_SHIFT 8
264 #define VPE_EDI_LUT10_MASK 0x1f
265 #define VPE_EDI_LUT10_SHIFT 16
266 #define VPE_EDI_LUT11_MASK 0x1f
267 #define VPE_EDI_LUT11_SHIFT 24
269 #define VPE_DEI_FMD_WINDOW_R0 0x0620
270 #define VPE_FMD_WINDOW_MINX_MASK 0x07ff
271 #define VPE_FMD_WINDOW_MINX_SHIFT 0
272 #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff
273 #define VPE_FMD_WINDOW_MAXX_SHIFT 16
274 #define VPE_FMD_WINDOW_ENABLE (1 << 31)
276 #define VPE_DEI_FMD_WINDOW_R1 0x0624
277 #define VPE_FMD_WINDOW_MINY_MASK 0x07ff
278 #define VPE_FMD_WINDOW_MINY_SHIFT 0
279 #define VPE_FMD_WINDOW_MAXY_MASK 0x07ff
280 #define VPE_FMD_WINDOW_MAXY_SHIFT 16
282 #define VPE_DEI_FMD_CONTROL_R0 0x0628
283 #define VPE_FMD_ENABLE (1 << 0)
284 #define VPE_FMD_LOCK (1 << 1)
285 #define VPE_FMD_JAM_DIR (1 << 2)
286 #define VPE_FMD_BED_ENABLE (1 << 3)
287 #define VPE_FMD_CAF_FIELD_THR_MASK 0xff
288 #define VPE_FMD_CAF_FIELD_THR_SHIFT 16
289 #define VPE_FMD_CAF_LINE_THR_MASK 0xff
290 #define VPE_FMD_CAF_LINE_THR_SHIFT 24
292 #define VPE_DEI_FMD_CONTROL_R1 0x062c
293 #define VPE_FMD_CAF_THR_MASK 0x000fffff
294 #define VPE_FMD_CAF_THR_SHIFT 0
296 #define VPE_DEI_FMD_STATUS_R0 0x0630
297 #define VPE_FMD_CAF_MASK 0x000fffff
298 #define VPE_FMD_CAF_SHIFT 0
299 #define VPE_FMD_RESET (1 << 24)
301 #define VPE_DEI_FMD_STATUS_R1 0x0634
302 #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff
303 #define VPE_FMD_FIELD_DIFF_SHIFT 0
305 #define VPE_DEI_FMD_STATUS_R2 0x0638
306 #define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
307 #define VPE_FMD_FRAME_DIFF_SHIFT 0
309 /* VPE scaler regs */
310 #define VPE_SC_MP_SC0 0x0700
311 #define VPE_INTERLACE_O (1 << 0)
312 #define VPE_LINEAR (1 << 1)
313 #define VPE_SC_BYPASS (1 << 2)
314 #define VPE_INVT_FID (1 << 3)
315 #define VPE_USE_RAV (1 << 4)
316 #define VPE_ENABLE_EV (1 << 5)
317 #define VPE_AUTO_HS (1 << 6)
318 #define VPE_DCM_2X (1 << 7)
319 #define VPE_DCM_4X (1 << 8)
320 #define VPE_HP_BYPASS (1 << 9)
321 #define VPE_INTERLACE_I (1 << 10)
322 #define VPE_ENABLE_SIN2_VER_INTP (1 << 11)
323 #define VPE_Y_PK_EN (1 << 14)
324 #define VPE_TRIM (1 << 15)
325 #define VPE_SELFGEN_FID (1 << 16)
327 #define VPE_SC_MP_SC1 0x0704
328 #define VPE_ROW_ACC_INC_MASK 0x07ffffff
329 #define VPE_ROW_ACC_INC_SHIFT 0
331 #define VPE_SC_MP_SC2 0x0708
332 #define VPE_ROW_ACC_OFFSET_MASK 0x0fffffff
333 #define VPE_ROW_ACC_OFFSET_SHIFT 0
335 #define VPE_SC_MP_SC3 0x070c
336 #define VPE_ROW_ACC_OFFSET_B_MASK 0x0fffffff
337 #define VPE_ROW_ACC_OFFSET_B_SHIFT 0
339 #define VPE_SC_MP_SC4 0x0710
340 #define VPE_TAR_H_MASK 0x07ff
341 #define VPE_TAR_H_SHIFT 0
342 #define VPE_TAR_W_MASK 0x07ff
343 #define VPE_TAR_W_SHIFT 12
344 #define VPE_LIN_ACC_INC_U_MASK 0x07
345 #define VPE_LIN_ACC_INC_U_SHIFT 24
346 #define VPE_NLIN_ACC_INIT_U_MASK 0x07
347 #define VPE_NLIN_ACC_INIT_U_SHIFT 28
349 #define VPE_SC_MP_SC5 0x0714
350 #define VPE_SRC_H_MASK 0x07ff
351 #define VPE_SRC_H_SHIFT 0
352 #define VPE_SRC_W_MASK 0x07ff
353 #define VPE_SRC_W_SHIFT 12
354 #define VPE_NLIN_ACC_INC_U_MASK 0x07
355 #define VPE_NLIN_ACC_INC_U_SHIFT 24
357 #define VPE_SC_MP_SC6 0x0718
358 #define VPE_ROW_ACC_INIT_RAV_MASK 0x03ff
359 #define VPE_ROW_ACC_INIT_RAV_SHIFT 0
360 #define VPE_ROW_ACC_INIT_RAV_B_MASK 0x03ff
361 #define VPE_ROW_ACC_INIT_RAV_B_SHIFT 10
363 #define VPE_SC_MP_SC8 0x0720
364 #define VPE_NLIN_LEFT_MASK 0x07ff
365 #define VPE_NLIN_LEFT_SHIFT 0
366 #define VPE_NLIN_RIGHT_MASK 0x07ff
367 #define VPE_NLIN_RIGHT_SHIFT 12
369 #define VPE_SC_MP_SC9 0x0724
370 #define VPE_LIN_ACC_INC VPE_SC_MP_SC9
372 #define VPE_SC_MP_SC10 0x0728
373 #define VPE_NLIN_ACC_INIT VPE_SC_MP_SC10
375 #define VPE_SC_MP_SC11 0x072c
376 #define VPE_NLIN_ACC_INC VPE_SC_MP_SC11
378 #define VPE_SC_MP_SC12 0x0730
379 #define VPE_COL_ACC_OFFSET_MASK 0x01ffffff
380 #define VPE_COL_ACC_OFFSET_SHIFT 0
382 #define VPE_SC_MP_SC13 0x0734
383 #define VPE_SC_FACTOR_RAV_MASK 0x03ff
384 #define VPE_SC_FACTOR_RAV_SHIFT 0
385 #define VPE_CHROMA_INTP_THR_MASK 0x03ff
386 #define VPE_CHROMA_INTP_THR_SHIFT 12
387 #define VPE_DELTA_CHROMA_THR_MASK 0x0f
388 #define VPE_DELTA_CHROMA_THR_SHIFT 24
390 #define VPE_SC_MP_SC17 0x0744
391 #define VPE_EV_THR_MASK 0x03ff
392 #define VPE_EV_THR_SHIFT 12
393 #define VPE_DELTA_LUMA_THR_MASK 0x0f
394 #define VPE_DELTA_LUMA_THR_SHIFT 24
395 #define VPE_DELTA_EV_THR_MASK 0x0f
396 #define VPE_DELTA_EV_THR_SHIFT 28
398 #define VPE_SC_MP_SC18 0x0748
399 #define VPE_HS_FACTOR_MASK 0x03ff
400 #define VPE_HS_FACTOR_SHIFT 0
401 #define VPE_CONF_DEFAULT_MASK 0x01ff
402 #define VPE_CONF_DEFAULT_SHIFT 16
404 #define VPE_SC_MP_SC19 0x074c
405 #define VPE_HPF_COEFF0_MASK 0xff
406 #define VPE_HPF_COEFF0_SHIFT 0
407 #define VPE_HPF_COEFF1_MASK 0xff
408 #define VPE_HPF_COEFF1_SHIFT 8
409 #define VPE_HPF_COEFF2_MASK 0xff
410 #define VPE_HPF_COEFF2_SHIFT 16
411 #define VPE_HPF_COEFF3_MASK 0xff
412 #define VPE_HPF_COEFF3_SHIFT 23
414 #define VPE_SC_MP_SC20 0x0750
415 #define VPE_HPF_COEFF4_MASK 0xff
416 #define VPE_HPF_COEFF4_SHIFT 0
417 #define VPE_HPF_COEFF5_MASK 0xff
418 #define VPE_HPF_COEFF5_SHIFT 8
419 #define VPE_HPF_NORM_SHIFT_MASK 0x07
420 #define VPE_HPF_NORM_SHIFT_SHIFT 16
421 #define VPE_NL_LIMIT_MASK 0x1ff
422 #define VPE_NL_LIMIT_SHIFT 20
424 #define VPE_SC_MP_SC21 0x0754
425 #define VPE_NL_LO_THR_MASK 0x01ff
426 #define VPE_NL_LO_THR_SHIFT 0
427 #define VPE_NL_LO_SLOPE_MASK 0xff
428 #define VPE_NL_LO_SLOPE_SHIFT 16
430 #define VPE_SC_MP_SC22 0x0758
431 #define VPE_NL_HI_THR_MASK 0x01ff
432 #define VPE_NL_HI_THR_SHIFT 0
433 #define VPE_NL_HI_SLOPE_SH_MASK 0x07
434 #define VPE_NL_HI_SLOPE_SH_SHIFT 16
436 #define VPE_SC_MP_SC23 0x075c
437 #define VPE_GRADIENT_THR_MASK 0x07ff
438 #define VPE_GRADIENT_THR_SHIFT 0
439 #define VPE_GRADIENT_THR_RANGE_MASK 0x0f
440 #define VPE_GRADIENT_THR_RANGE_SHIFT 12
441 #define VPE_MIN_GY_THR_MASK 0xff
442 #define VPE_MIN_GY_THR_SHIFT 16
443 #define VPE_MIN_GY_THR_RANGE_MASK 0x0f
444 #define VPE_MIN_GY_THR_RANGE_SHIFT 28
446 #define VPE_SC_MP_SC24 0x0760
447 #define VPE_ORG_H_MASK 0x07ff
448 #define VPE_ORG_H_SHIFT 0
449 #define VPE_ORG_W_MASK 0x07ff
450 #define VPE_ORG_W_SHIFT 16
452 #define VPE_SC_MP_SC25 0x0764
453 #define VPE_OFF_H_MASK 0x07ff
454 #define VPE_OFF_H_SHIFT 0
455 #define VPE_OFF_W_MASK 0x07ff
456 #define VPE_OFF_W_SHIFT 16
458 /* VPE color space converter regs */
459 #define VPE_CSC_CSC00 0x5700
460 #define VPE_CSC_A0_MASK 0x1fff
461 #define VPE_CSC_A0_SHIFT 0
462 #define VPE_CSC_B0_MASK 0x1fff
463 #define VPE_CSC_B0_SHIFT 16
465 #define VPE_CSC_CSC01 0x5704
466 #define VPE_CSC_C0_MASK 0x1fff
467 #define VPE_CSC_C0_SHIFT 0
468 #define VPE_CSC_A1_MASK 0x1fff
469 #define VPE_CSC_A1_SHIFT 16
471 #define VPE_CSC_CSC02 0x5708
472 #define VPE_CSC_B1_MASK 0x1fff
473 #define VPE_CSC_B1_SHIFT 0
474 #define VPE_CSC_C1_MASK 0x1fff
475 #define VPE_CSC_C1_SHIFT 16
477 #define VPE_CSC_CSC03 0x570c
478 #define VPE_CSC_A2_MASK 0x1fff
479 #define VPE_CSC_A2_SHIFT 0
480 #define VPE_CSC_B2_MASK 0x1fff
481 #define VPE_CSC_B2_SHIFT 16
483 #define VPE_CSC_CSC04 0x5710
484 #define VPE_CSC_C2_MASK 0x1fff
485 #define VPE_CSC_C2_SHIFT 0
486 #define VPE_CSC_D0_MASK 0x0fff
487 #define VPE_CSC_D0_SHIFT 16
489 #define VPE_CSC_CSC05 0x5714
490 #define VPE_CSC_D1_MASK 0x0fff
491 #define VPE_CSC_D1_SHIFT 0
492 #define VPE_CSC_D2_MASK 0x0fff
493 #define VPE_CSC_D2_SHIFT 16
494 #define VPE_CSC_BYPASS (1 << 28)