2 * Elonics E4000 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "e4000_priv.h"
23 /* write multiple registers */
24 static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
28 struct i2c_msg msg[1] = {
30 .addr = priv->cfg->i2c_addr,
38 memcpy(&buf[1], val, len);
40 ret = i2c_transfer(priv->i2c, msg, 1);
44 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
45 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
51 /* read multiple registers */
52 static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
56 struct i2c_msg msg[2] = {
58 .addr = priv->cfg->i2c_addr,
63 .addr = priv->cfg->i2c_addr,
70 ret = i2c_transfer(priv->i2c, msg, 2);
72 memcpy(val, buf, len);
75 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
76 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
83 /* write single register */
84 static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
86 return e4000_wr_regs(priv, reg, &val, 1);
89 /* read single register */
90 static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
92 return e4000_rd_regs(priv, reg, val, 1);
95 static int e4000_init(struct dvb_frontend *fe)
97 struct e4000_priv *priv = fe->tuner_priv;
100 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
102 if (fe->ops.i2c_gate_ctrl)
103 fe->ops.i2c_gate_ctrl(fe, 1);
105 /* dummy I2C to ensure I2C wakes up */
106 ret = e4000_wr_reg(priv, 0x02, 0x40);
109 ret = e4000_wr_reg(priv, 0x00, 0x01);
113 /* disable output clock */
114 ret = e4000_wr_reg(priv, 0x06, 0x00);
118 ret = e4000_wr_reg(priv, 0x7a, 0x96);
122 /* configure gains */
123 ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
127 ret = e4000_wr_reg(priv, 0x82, 0x00);
131 ret = e4000_wr_reg(priv, 0x24, 0x05);
135 ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
139 ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
144 * TODO: Implement DC offset control correctly.
145 * DC offsets has quite much effect for received signal quality in case
146 * of direct conversion tuners (Zero-IF). Surely we will now lose few
147 * decimals or even decibels from SNR...
149 /* DC offset control */
150 ret = e4000_wr_reg(priv, 0x2d, 0x0c);
155 ret = e4000_wr_reg(priv, 0x1a, 0x17);
159 ret = e4000_wr_reg(priv, 0x1f, 0x1a);
163 if (fe->ops.i2c_gate_ctrl)
164 fe->ops.i2c_gate_ctrl(fe, 0);
168 if (fe->ops.i2c_gate_ctrl)
169 fe->ops.i2c_gate_ctrl(fe, 0);
171 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
175 static int e4000_sleep(struct dvb_frontend *fe)
177 struct e4000_priv *priv = fe->tuner_priv;
180 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
182 if (fe->ops.i2c_gate_ctrl)
183 fe->ops.i2c_gate_ctrl(fe, 1);
185 ret = e4000_wr_reg(priv, 0x00, 0x00);
189 if (fe->ops.i2c_gate_ctrl)
190 fe->ops.i2c_gate_ctrl(fe, 0);
194 if (fe->ops.i2c_gate_ctrl)
195 fe->ops.i2c_gate_ctrl(fe, 0);
197 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
201 static int e4000_set_params(struct dvb_frontend *fe)
203 struct e4000_priv *priv = fe->tuner_priv;
204 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
205 int ret, i, sigma_delta;
209 dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
210 "bandwidth_hz=%d\n", __func__,
211 c->delivery_system, c->frequency, c->bandwidth_hz);
213 if (fe->ops.i2c_gate_ctrl)
214 fe->ops.i2c_gate_ctrl(fe, 1);
216 /* gain control manual */
217 ret = e4000_wr_reg(priv, 0x1a, 0x00);
222 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
223 if (c->frequency <= e4000_pll_lut[i].freq)
227 if (i == ARRAY_SIZE(e4000_pll_lut))
231 * Note: Currently f_VCO overflows when c->frequency is 1 073 741 824 Hz
234 f_VCO = c->frequency * e4000_pll_lut[i].mul;
235 sigma_delta = 0x10000UL * (f_VCO % priv->cfg->clock) / priv->cfg->clock;
236 buf[0] = f_VCO / priv->cfg->clock;
237 buf[1] = (sigma_delta >> 0) & 0xff;
238 buf[2] = (sigma_delta >> 8) & 0xff;
240 buf[4] = e4000_pll_lut[i].div;
242 dev_dbg(&priv->i2c->dev, "%s: f_VCO=%u pll div=%d sigma_delta=%04x\n",
243 __func__, f_VCO, buf[0], sigma_delta);
245 ret = e4000_wr_regs(priv, 0x09, buf, 5);
249 /* LNA filter (RF filter) */
250 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
251 if (c->frequency <= e400_lna_filter_lut[i].freq)
255 if (i == ARRAY_SIZE(e400_lna_filter_lut))
258 ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
263 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
264 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
268 if (i == ARRAY_SIZE(e4000_if_filter_lut))
271 buf[0] = e4000_if_filter_lut[i].reg11_val;
272 buf[1] = e4000_if_filter_lut[i].reg12_val;
274 ret = e4000_wr_regs(priv, 0x11, buf, 2);
279 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
280 if (c->frequency <= e4000_band_lut[i].freq)
284 if (i == ARRAY_SIZE(e4000_band_lut))
287 ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
291 ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
295 /* gain control auto */
296 ret = e4000_wr_reg(priv, 0x1a, 0x17);
300 if (fe->ops.i2c_gate_ctrl)
301 fe->ops.i2c_gate_ctrl(fe, 0);
305 if (fe->ops.i2c_gate_ctrl)
306 fe->ops.i2c_gate_ctrl(fe, 0);
308 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
312 static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
314 struct e4000_priv *priv = fe->tuner_priv;
316 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
318 *frequency = 0; /* Zero-IF */
323 static int e4000_release(struct dvb_frontend *fe)
325 struct e4000_priv *priv = fe->tuner_priv;
327 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
329 kfree(fe->tuner_priv);
334 static const struct dvb_tuner_ops e4000_tuner_ops = {
336 .name = "Elonics E4000",
337 .frequency_min = 174000000,
338 .frequency_max = 862000000,
341 .release = e4000_release,
344 .sleep = e4000_sleep,
345 .set_params = e4000_set_params,
347 .get_if_frequency = e4000_get_if_frequency,
350 struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
351 struct i2c_adapter *i2c, const struct e4000_config *cfg)
353 struct e4000_priv *priv;
357 if (fe->ops.i2c_gate_ctrl)
358 fe->ops.i2c_gate_ctrl(fe, 1);
360 priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
363 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
370 /* check if the tuner is there */
371 ret = e4000_rd_reg(priv, 0x02, &chip_id);
375 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
380 /* put sleep as chip seems to be in normal mode by default */
381 ret = e4000_wr_reg(priv, 0x00, 0x00);
385 dev_info(&priv->i2c->dev,
386 "%s: Elonics E4000 successfully identified\n",
389 fe->tuner_priv = priv;
390 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
391 sizeof(struct dvb_tuner_ops));
393 if (fe->ops.i2c_gate_ctrl)
394 fe->ops.i2c_gate_ctrl(fe, 0);
398 if (fe->ops.i2c_gate_ctrl)
399 fe->ops.i2c_gate_ctrl(fe, 0);
401 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
405 EXPORT_SYMBOL(e4000_attach);
407 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
408 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
409 MODULE_LICENSE("GPL");