2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
40 #include "cx231xx-dif.h"
42 #define TUNER_MODE_FM_RADIO 0
43 /******************************************************************************
44 -: BLOCK ARRANGEMENT :-
45 I2S block ----------------------|
48 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
49 [video & audio] | [Audio]
54 *******************************************************************************/
55 /******************************************************************************
58 ******************************************************************************/
59 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
65 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
70 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
75 void initGPIO(struct cx231xx *dev)
77 u32 _gpio_direction = 0;
81 _gpio_direction = _gpio_direction & 0xFC0003FF;
82 _gpio_direction = _gpio_direction | 0x03FDFC00;
83 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
85 verve_read_byte(dev, 0x07, &val);
86 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
87 verve_write_byte(dev, 0x07, 0xF4);
88 verve_read_byte(dev, 0x07, &val);
89 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
91 cx231xx_capture_start(dev, 1, Vbi);
93 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
94 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
97 void uninitGPIO(struct cx231xx *dev)
99 u8 value[4] = { 0, 0, 0, 0 };
101 cx231xx_capture_start(dev, 0, Vbi);
102 verve_write_byte(dev, 0x07, 0x14);
103 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
107 /******************************************************************************
108 * A F E - B L O C K C O N T R O L functions *
109 * [ANALOG FRONT END] *
110 ******************************************************************************/
111 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
113 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
117 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
122 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
128 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
132 u8 afe_power_status = 0;
135 /* super block initialize */
136 temp = (u8) (ref_count & 0xff);
137 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
141 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
145 temp = (u8) ((ref_count & 0x300) >> 8);
147 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
151 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
156 while (afe_power_status != 0x18) {
157 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
160 ": Init Super Block failed in send cmd\n");
164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
165 afe_power_status &= 0xff;
168 ": Init Super Block failed in receive cmd\n");
174 ": Init Super Block force break in loop !!!!\n");
183 /* start tuning filter */
184 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
191 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
196 int cx231xx_afe_init_channels(struct cx231xx *dev)
200 /* power up all 3 channels, clear pd_buffer */
201 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
205 /* Enable quantizer calibration */
206 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
208 /* channel initialize, force modulator (fb) reset */
209 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
213 /* start quantilizer calibration */
214 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
219 /* exit modulator (fb) reset */
220 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
224 /* enable the pre_clamp in each channel for single-ended input */
225 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
229 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
230 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
231 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
233 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
235 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
237 /* dynamic element matching off */
238 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
245 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
250 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
251 c_value &= (~(0x50));
252 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
258 The Analog Front End in Cx231xx has 3 channels. These
259 channels are used to share between different inputs
260 like tuner, s-video and composite inputs.
262 channel 1 ----- pin 1 to pin4(in reg is 1-4)
263 channel 2 ----- pin 5 to pin8(in reg is 5-8)
264 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
266 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
268 u8 ch1_setting = (u8) input_mux;
269 u8 ch2_setting = (u8) (input_mux >> 8);
270 u8 ch3_setting = (u8) (input_mux >> 16);
274 if (ch1_setting != 0) {
275 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
276 value &= ~INPUT_SEL_MASK;
277 value |= (ch1_setting - 1) << 4;
279 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
282 if (ch2_setting != 0) {
283 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
284 value &= ~INPUT_SEL_MASK;
285 value |= (ch2_setting - 1) << 4;
287 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
290 /* For ch3_setting, the value to put in the register is
291 7 less than the input number */
292 if (ch3_setting != 0) {
293 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
294 value &= ~INPUT_SEL_MASK;
295 value |= (ch3_setting - 1) << 4;
297 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
303 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
308 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
309 * Currently, only baseband works.
313 case AFE_MODE_LOW_IF:
314 cx231xx_Setup_AFE_for_LowIF(dev);
316 case AFE_MODE_BASEBAND:
317 status = cx231xx_afe_setup_AFE_for_baseband(dev);
319 case AFE_MODE_EU_HI_IF:
320 /* SetupAFEforEuHiIF(); */
322 case AFE_MODE_US_HI_IF:
323 /* SetupAFEforUsHiIF(); */
325 case AFE_MODE_JAPAN_HI_IF:
326 /* SetupAFEforJapanHiIF(); */
330 if ((mode != dev->afe_mode) &&
331 (dev->video_input == CX231XX_VMUX_TELEVISION))
332 status = cx231xx_afe_adjust_ref_count(dev,
333 CX231XX_VMUX_TELEVISION);
335 dev->afe_mode = mode;
340 int cx231xx_afe_update_power_control(struct cx231xx *dev,
343 u8 afe_power_status = 0;
346 switch (dev->model) {
347 case CX231XX_BOARD_CNXT_CARRAERA:
348 case CX231XX_BOARD_CNXT_RDE_250:
349 case CX231XX_BOARD_CNXT_SHELBY:
350 case CX231XX_BOARD_CNXT_RDU_250:
351 case CX231XX_BOARD_CNXT_RDE_253S:
352 case CX231XX_BOARD_CNXT_RDU_253S:
353 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
354 case CX231XX_BOARD_HAUPPAUGE_EXETER:
355 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
359 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
360 case CX231XX_BOARD_OTG102:
361 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
362 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
363 FLD_PWRDN_ENABLE_PLL)) {
364 status = afe_write_byte(dev, SUP_BLK_PWRDN,
365 FLD_PWRDN_TUNING_BIAS |
366 FLD_PWRDN_ENABLE_PLL);
367 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
379 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
380 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
382 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
387 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
389 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
392 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
394 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
395 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
396 FLD_PWRDN_ENABLE_PLL)) {
397 status = afe_write_byte(dev, SUP_BLK_PWRDN,
398 FLD_PWRDN_TUNING_BIAS |
399 FLD_PWRDN_ENABLE_PLL);
400 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
413 cx231xx_info("Invalid AV mode input\n");
418 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
419 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
420 FLD_PWRDN_ENABLE_PLL)) {
421 status = afe_write_byte(dev, SUP_BLK_PWRDN,
422 FLD_PWRDN_TUNING_BIAS |
423 FLD_PWRDN_ENABLE_PLL);
424 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
436 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
437 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
439 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
444 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
446 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
449 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
451 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
452 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
453 FLD_PWRDN_ENABLE_PLL)) {
454 status = afe_write_byte(dev, SUP_BLK_PWRDN,
455 FLD_PWRDN_TUNING_BIAS |
456 FLD_PWRDN_ENABLE_PLL);
457 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
470 cx231xx_info("Invalid AV mode input\n");
478 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
484 dev->video_input = video_input;
486 if (video_input == CX231XX_VMUX_TELEVISION) {
487 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
491 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
492 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
496 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
498 switch (input_mode) {
500 dev->afe_ref_count = 0x23C;
503 dev->afe_ref_count = 0x24C;
506 dev->afe_ref_count = 0x258;
509 dev->afe_ref_count = 0x260;
515 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
520 /******************************************************************************
521 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
522 ******************************************************************************/
523 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
525 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
529 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
534 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
540 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
542 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
546 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
548 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
551 int cx231xx_check_fw(struct cx231xx *dev)
555 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
563 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
567 switch (INPUT(input)->type) {
568 case CX231XX_VMUX_COMPOSITE1:
569 case CX231XX_VMUX_SVIDEO:
570 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
571 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
573 status = cx231xx_set_power_mode(dev,
574 POLARIS_AVMODE_ENXTERNAL_AV);
576 cx231xx_errdev("%s: set_power_mode : Failed to"
577 " set Power - errCode [%d]!\n",
582 status = cx231xx_set_decoder_video_input(dev,
586 case CX231XX_VMUX_TELEVISION:
587 case CX231XX_VMUX_CABLE:
588 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
589 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
591 status = cx231xx_set_power_mode(dev,
592 POLARIS_AVMODE_ANALOGT_TV);
594 cx231xx_errdev("%s: set_power_mode:Failed"
595 " to set Power - errCode [%d]!\n",
600 if (dev->tuner_type == TUNER_NXP_TDA18271)
601 status = cx231xx_set_decoder_video_input(dev,
602 CX231XX_VMUX_TELEVISION,
605 status = cx231xx_set_decoder_video_input(dev,
606 CX231XX_VMUX_COMPOSITE1,
611 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
612 __func__, INPUT(input)->type);
616 /* save the selection */
617 dev->video_input = input;
622 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
623 u8 pin_type, u8 input)
628 if (pin_type != dev->video_input) {
629 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
631 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
632 "AFE input mux - errCode [%d]!\n",
638 /* call afe block to set video inputs */
639 status = cx231xx_afe_set_input_mux(dev, input);
641 cx231xx_errdev("%s: set_input_mux :Failed to set"
642 " AFE input mux - errCode [%d]!\n",
648 case CX231XX_VMUX_COMPOSITE1:
649 status = vid_blk_read_word(dev, AFE_CTRL, &value);
650 value |= (0 << 13) | (1 << 4);
653 /* set [24:23] [22:15] to 0 */
654 value &= (~(0x1ff8000));
655 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
657 status = vid_blk_write_word(dev, AFE_CTRL, value);
659 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
661 status = vid_blk_write_word(dev, OUT_CTRL1, value);
663 /* Set output mode */
664 status = cx231xx_read_modify_write_i2c_dword(dev,
668 dev->board.output_mode);
670 /* Tell DIF object to go to baseband mode */
671 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
673 cx231xx_errdev("%s: cx231xx_dif set to By pass"
674 " mode- errCode [%d]!\n",
679 /* Read the DFE_CTRL1 register */
680 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
682 /* enable the VBI_GATE_EN */
683 value |= FLD_VBI_GATE_EN;
685 /* Enable the auto-VGA enable */
686 value |= FLD_VGA_AUTO_EN;
689 status = vid_blk_write_word(dev, DFE_CTRL1, value);
691 /* Disable auto config of registers */
692 status = cx231xx_read_modify_write_i2c_dword(dev,
694 MODE_CTRL, FLD_ACFG_DIS,
695 cx231xx_set_field(FLD_ACFG_DIS, 1));
697 /* Set CVBS input mode */
698 status = cx231xx_read_modify_write_i2c_dword(dev,
700 MODE_CTRL, FLD_INPUT_MODE,
701 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
703 case CX231XX_VMUX_SVIDEO:
704 /* Disable the use of DIF */
706 status = vid_blk_read_word(dev, AFE_CTRL, &value);
708 /* set [24:23] [22:15] to 0 */
709 value &= (~(0x1ff8000));
710 /* set FUNC_MODE[24:23] = 2
711 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
713 status = vid_blk_write_word(dev, AFE_CTRL, value);
715 /* Tell DIF object to go to baseband mode */
716 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
718 cx231xx_errdev("%s: cx231xx_dif set to By pass"
719 " mode- errCode [%d]!\n",
724 /* Read the DFE_CTRL1 register */
725 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
727 /* enable the VBI_GATE_EN */
728 value |= FLD_VBI_GATE_EN;
730 /* Enable the auto-VGA enable */
731 value |= FLD_VGA_AUTO_EN;
734 status = vid_blk_write_word(dev, DFE_CTRL1, value);
736 /* Disable auto config of registers */
737 status = cx231xx_read_modify_write_i2c_dword(dev,
739 MODE_CTRL, FLD_ACFG_DIS,
740 cx231xx_set_field(FLD_ACFG_DIS, 1));
742 /* Set YC input mode */
743 status = cx231xx_read_modify_write_i2c_dword(dev,
747 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
750 status = vid_blk_read_word(dev, AFE_CTRL, &value);
751 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
753 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
754 This sets them to use video
755 rather than audio. Only one of the two will be in use. */
756 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
758 status = vid_blk_write_word(dev, AFE_CTRL, value);
760 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
762 case CX231XX_VMUX_TELEVISION:
763 case CX231XX_VMUX_CABLE:
765 /* TODO: Test if this is also needed for xc2028/xc3028 */
766 if (dev->board.tuner_type == TUNER_XC5000) {
767 /* Disable the use of DIF */
769 status = vid_blk_read_word(dev, AFE_CTRL, &value);
770 value |= (0 << 13) | (1 << 4);
773 /* set [24:23] [22:15] to 0 */
774 value &= (~(0x1FF8000));
775 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
777 status = vid_blk_write_word(dev, AFE_CTRL, value);
779 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
781 status = vid_blk_write_word(dev, OUT_CTRL1, value);
783 /* Set output mode */
784 status = cx231xx_read_modify_write_i2c_dword(dev,
786 OUT_CTRL1, FLD_OUT_MODE,
787 dev->board.output_mode);
789 /* Tell DIF object to go to baseband mode */
790 status = cx231xx_dif_set_standard(dev,
793 cx231xx_errdev("%s: cx231xx_dif set to By pass"
794 " mode- errCode [%d]!\n",
799 /* Read the DFE_CTRL1 register */
800 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
802 /* enable the VBI_GATE_EN */
803 value |= FLD_VBI_GATE_EN;
805 /* Enable the auto-VGA enable */
806 value |= FLD_VGA_AUTO_EN;
809 status = vid_blk_write_word(dev, DFE_CTRL1, value);
811 /* Disable auto config of registers */
812 status = cx231xx_read_modify_write_i2c_dword(dev,
814 MODE_CTRL, FLD_ACFG_DIS,
815 cx231xx_set_field(FLD_ACFG_DIS, 1));
817 /* Set CVBS input mode */
818 status = cx231xx_read_modify_write_i2c_dword(dev,
820 MODE_CTRL, FLD_INPUT_MODE,
821 cx231xx_set_field(FLD_INPUT_MODE,
824 /* Enable the DIF for the tuner */
826 /* Reinitialize the DIF */
827 status = cx231xx_dif_set_standard(dev, dev->norm);
829 cx231xx_errdev("%s: cx231xx_dif set to By pass"
830 " mode- errCode [%d]!\n",
835 /* Make sure bypass is cleared */
836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
838 /* Clear the bypass bit */
839 value &= ~FLD_DIF_DIF_BYPASS;
841 /* Enable the use of the DIF block */
842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
844 /* Read the DFE_CTRL1 register */
845 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
847 /* Disable the VBI_GATE_EN */
848 value &= ~FLD_VBI_GATE_EN;
850 /* Enable the auto-VGA enable, AGC, and
851 set the skip count to 2 */
852 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
855 status = vid_blk_write_word(dev, DFE_CTRL1, value);
857 /* Wait until AGC locks up */
860 /* Disable the auto-VGA enable AGC */
861 value &= ~(FLD_VGA_AUTO_EN);
864 status = vid_blk_write_word(dev, DFE_CTRL1, value);
866 /* Enable Polaris B0 AGC output */
867 status = vid_blk_read_word(dev, PIN_CTRL, &value);
868 value |= (FLD_OEF_AGC_RF) |
869 (FLD_OEF_AGC_IFVGA) |
871 status = vid_blk_write_word(dev, PIN_CTRL, value);
873 /* Set output mode */
874 status = cx231xx_read_modify_write_i2c_dword(dev,
876 OUT_CTRL1, FLD_OUT_MODE,
877 dev->board.output_mode);
879 /* Disable auto config of registers */
880 status = cx231xx_read_modify_write_i2c_dword(dev,
882 MODE_CTRL, FLD_ACFG_DIS,
883 cx231xx_set_field(FLD_ACFG_DIS, 1));
885 /* Set CVBS input mode */
886 status = cx231xx_read_modify_write_i2c_dword(dev,
888 MODE_CTRL, FLD_INPUT_MODE,
889 cx231xx_set_field(FLD_INPUT_MODE,
892 /* Set some bits in AFE_CTRL so that channel 2 or 3
893 * is ready to receive audio */
894 /* Clear clamp for channels 2 and 3 (bit 16-17) */
895 /* Clear droop comp (bit 19-20) */
896 /* Set VGA_SEL (for audio control) (bit 7-8) */
897 status = vid_blk_read_word(dev, AFE_CTRL, &value);
899 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
900 value &= (~(FLD_FUNC_MODE));
903 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
905 status = vid_blk_write_word(dev, AFE_CTRL, value);
907 if (dev->tuner_type == TUNER_NXP_TDA18271) {
908 status = vid_blk_read_word(dev, PIN_CTRL,
910 status = vid_blk_write_word(dev, PIN_CTRL,
911 (value & 0xFFFFFFEF));
920 /* Set raw VBI mode */
921 status = cx231xx_read_modify_write_i2c_dword(dev,
923 OUT_CTRL1, FLD_VBIHACTRAW_EN,
924 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
926 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
929 status = vid_blk_write_word(dev, OUT_CTRL1, value);
935 void cx231xx_enable656(struct cx231xx *dev)
938 /*enable TS1 data[0:7] as output to export 656*/
940 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
942 /*enable TS1 clock as output to export 656*/
944 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
947 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
949 EXPORT_SYMBOL_GPL(cx231xx_enable656);
951 void cx231xx_disable656(struct cx231xx *dev)
955 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
957 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
960 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
962 EXPORT_SYMBOL_GPL(cx231xx_disable656);
965 * Handle any video-mode specific overrides that are different
966 * on a per video standards basis after touching the MODE_CTRL
967 * register which resets many values for autodetect
969 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
973 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
974 (unsigned int)dev->norm);
976 /* Change the DFE_CTRL3 bp_percent to fix flagging */
977 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
979 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
980 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
982 /* Move the close caption lines out of active video,
983 adjust the active video start point */
984 status = cx231xx_read_modify_write_i2c_dword(dev,
987 FLD_VBLANK_CNT, 0x18);
988 status = cx231xx_read_modify_write_i2c_dword(dev,
993 status = cx231xx_read_modify_write_i2c_dword(dev,
999 status = cx231xx_read_modify_write_i2c_dword(dev,
1000 VID_BLK_I2C_ADDRESS,
1004 (FLD_HBLANK_CNT, 0x79));
1006 } else if (dev->norm & V4L2_STD_SECAM) {
1007 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1008 status = cx231xx_read_modify_write_i2c_dword(dev,
1009 VID_BLK_I2C_ADDRESS,
1011 FLD_VBLANK_CNT, 0x20);
1012 status = cx231xx_read_modify_write_i2c_dword(dev,
1013 VID_BLK_I2C_ADDRESS,
1019 status = cx231xx_read_modify_write_i2c_dword(dev,
1020 VID_BLK_I2C_ADDRESS,
1026 /* Adjust the active video horizontal start point */
1027 status = cx231xx_read_modify_write_i2c_dword(dev,
1028 VID_BLK_I2C_ADDRESS,
1032 (FLD_HBLANK_CNT, 0x85));
1034 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1035 status = cx231xx_read_modify_write_i2c_dword(dev,
1036 VID_BLK_I2C_ADDRESS,
1038 FLD_VBLANK_CNT, 0x20);
1039 status = cx231xx_read_modify_write_i2c_dword(dev,
1040 VID_BLK_I2C_ADDRESS,
1046 status = cx231xx_read_modify_write_i2c_dword(dev,
1047 VID_BLK_I2C_ADDRESS,
1053 /* Adjust the active video horizontal start point */
1054 status = cx231xx_read_modify_write_i2c_dword(dev,
1055 VID_BLK_I2C_ADDRESS,
1059 (FLD_HBLANK_CNT, 0x85));
1066 int cx231xx_unmute_audio(struct cx231xx *dev)
1068 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1070 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1072 static int stopAudioFirmware(struct cx231xx *dev)
1074 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1077 static int restartAudioFirmware(struct cx231xx *dev)
1079 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1082 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1085 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1087 switch (INPUT(input)->amux) {
1088 case CX231XX_AMUX_VIDEO:
1089 ainput = AUDIO_INPUT_TUNER_TV;
1091 case CX231XX_AMUX_LINE_IN:
1092 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1093 ainput = AUDIO_INPUT_LINE;
1099 status = cx231xx_set_audio_decoder_input(dev, ainput);
1104 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1105 enum AUDIO_INPUT audio_input)
1112 /* Put it in soft reset */
1113 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1115 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1117 switch (audio_input) {
1118 case AUDIO_INPUT_LINE:
1119 /* setup AUD_IO control from Merlin paralle output */
1120 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1121 AUD_CHAN_SRC_PARALLEL);
1122 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1124 /* setup input to Merlin, SRC2 connect to AC97
1125 bypass upsample-by-2, slave mode, sony mode, left justify
1126 adr 091c, dat 01000000 */
1127 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1129 status = vid_blk_write_word(dev, AC97_CTL,
1130 (dwval | FLD_AC97_UP2X_BYPASS));
1132 /* select the parallel1 and SRC3 */
1133 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1134 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1135 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1136 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1138 /* unmute all, AC97 in, independence mode
1139 adr 08d0, data 0x00063073 */
1140 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1141 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1143 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1144 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1145 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1146 (dwval | FLD_PATH1_AVC_THRESHOLD));
1148 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1149 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1150 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1151 (dwval | FLD_PATH1_SC_THRESHOLD));
1154 case AUDIO_INPUT_TUNER_TV:
1156 status = stopAudioFirmware(dev);
1157 /* Setup SRC sources and clocks */
1158 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1159 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1160 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1161 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1162 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1163 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1164 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1165 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1166 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1167 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1168 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1169 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1170 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1171 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1173 /* Setup the AUD_IO control */
1174 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1175 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1176 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1177 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1178 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1179 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1181 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1183 /* setAudioStandard(_audio_standard); */
1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1186 status = restartAudioFirmware(dev);
1188 switch (dev->board.tuner_type) {
1190 /* SIF passthrough at 28.6363 MHz sample rate */
1191 status = cx231xx_read_modify_write_i2c_dword(dev,
1192 VID_BLK_I2C_ADDRESS,
1195 cx231xx_set_field(FLD_SIF_EN, 1));
1197 case TUNER_NXP_TDA18271:
1198 /* Normal mode: SIF passthrough at 14.32 MHz */
1199 status = cx231xx_read_modify_write_i2c_dword(dev,
1200 VID_BLK_I2C_ADDRESS,
1203 cx231xx_set_field(FLD_SIF_EN, 0));
1206 /* This is just a casual suggestion to people adding
1207 new boards in case they use a tuner type we don't
1208 currently know about */
1209 printk(KERN_INFO "Unknown tuner type configuring SIF");
1214 case AUDIO_INPUT_TUNER_FM:
1215 /* use SIF for FM radio
1217 setAudioStandard(_audio_standard);
1221 case AUDIO_INPUT_MUTE:
1222 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1226 /* Take it out of soft reset */
1227 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1229 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1234 /******************************************************************************
1235 * C H I P Specific C O N T R O L functions *
1236 ******************************************************************************/
1237 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1242 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1243 value |= (~dev->board.ctl_pin_status_mask);
1244 status = vid_blk_write_word(dev, PIN_CTRL, value);
1249 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1250 u8 analog_or_digital)
1254 /* first set the direction to output */
1255 status = cx231xx_set_gpio_direction(dev,
1257 agc_analog_digital_select_gpio, 1);
1259 /* 0 - demod ; 1 - Analog mode */
1260 status = cx231xx_set_gpio_value(dev,
1261 dev->board.agc_analog_digital_select_gpio,
1267 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3)
1269 u8 value[4] = { 0, 0, 0, 0 };
1271 bool current_is_port_3;
1273 if (dev->board.dont_use_port_3)
1275 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1276 PWR_CTL_EN, value, 4);
1280 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false;
1282 /* Just return, if already using the right port */
1283 if (current_is_port_3 == is_port_3)
1287 value[0] |= I2C_DEMOD_EN;
1289 value[0] &= ~I2C_DEMOD_EN;
1291 cx231xx_info("Changing the i2c master port to %d\n",
1294 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1295 PWR_CTL_EN, value, 4);
1300 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3);
1302 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1308 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1309 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1310 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1312 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1313 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1314 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1318 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1324 vid_blk_write_word(dev, 0x104, value);
1326 for (i = 0x100; i < 0x140; i++) {
1327 vid_blk_read_word(dev, i, &value);
1328 cx231xx_info("reg0x%x=0x%x\n", i, value);
1332 for (i = 0x300; i < 0x400; i++) {
1333 vid_blk_read_word(dev, i, &value);
1334 cx231xx_info("reg0x%x=0x%x\n", i, value);
1338 for (i = 0x400; i < 0x440; i++) {
1339 vid_blk_read_word(dev, i, &value);
1340 cx231xx_info("reg0x%x=0x%x\n", i, value);
1344 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1345 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1346 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1347 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1348 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1351 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1353 u8 value[4] = { 0, 0, 0, 0 };
1354 cx231xx_info("cx231xx_dump_SC_reg!\n");
1356 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1358 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1359 value[1], value[2], value[3]);
1360 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1362 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1363 value[1], value[2], value[3]);
1364 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1366 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1367 value[1], value[2], value[3]);
1368 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1370 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1371 value[1], value[2], value[3]);
1373 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1375 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1376 value[1], value[2], value[3]);
1377 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1379 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1380 value[1], value[2], value[3]);
1381 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1383 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1384 value[1], value[2], value[3]);
1385 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1387 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1388 value[1], value[2], value[3]);
1390 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1392 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1393 value[1], value[2], value[3]);
1394 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1396 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1397 value[1], value[2], value[3]);
1398 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1400 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1401 value[1], value[2], value[3]);
1402 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1404 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1405 value[1], value[2], value[3]);
1407 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1409 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1410 value[1], value[2], value[3]);
1411 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1413 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1414 value[1], value[2], value[3]);
1415 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1417 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1418 value[1], value[2], value[3]);
1419 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1421 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1422 value[1], value[2], value[3]);
1424 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1426 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1427 value[1], value[2], value[3]);
1428 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1430 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1431 value[1], value[2], value[3]);
1436 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1441 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1442 value = (value & 0xFE)|0x01;
1443 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1445 afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1446 value = (value & 0xFE)|0x00;
1447 afe_write_byte(dev, ADC_STATUS2_CH3, value);
1451 config colibri to lo-if mode
1453 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1454 the diff IF input by half,
1456 for low-if agc defect
1459 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1460 value = (value & 0xFC)|0x00;
1461 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1463 afe_read_byte(dev, ADC_INPUT_CH3, &value);
1464 value = (value & 0xF9)|0x02;
1465 afe_write_byte(dev, ADC_INPUT_CH3, value);
1467 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1468 value = (value & 0xFB)|0x04;
1469 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1471 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1472 value = (value & 0xFC)|0x03;
1473 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1475 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1476 value = (value & 0xFB)|0x04;
1477 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1479 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1480 value = (value & 0xF8)|0x06;
1481 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1483 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1484 value = (value & 0x8F)|0x40;
1485 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1487 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1488 value = (value & 0xDF)|0x20;
1489 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1492 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1493 u8 spectral_invert, u32 mode)
1495 u32 colibri_carrier_offset = 0;
1496 u32 func_mode = 0x01; /* Device has a DIF if this function is called */
1498 u8 value[4] = { 0, 0, 0, 0 };
1500 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1501 value[0] = (u8) 0x6F;
1502 value[1] = (u8) 0x6F;
1503 value[2] = (u8) 0x6F;
1504 value[3] = (u8) 0x6F;
1505 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1506 PWR_CTL_EN, value, 4);
1508 /*Set colibri for low IF*/
1509 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1511 /* Set C2HH for low IF operation.*/
1512 standard = dev->norm;
1513 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1514 func_mode, standard);
1516 /* Get colibri offsets.*/
1517 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1520 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1521 colibri_carrier_offset, standard);
1523 /* Set the band Pass filter for DIF*/
1524 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset),
1525 spectral_invert, mode);
1528 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1530 u32 colibri_carrier_offset = 0;
1532 if (mode == TUNER_MODE_FM_RADIO) {
1533 colibri_carrier_offset = 1100000;
1534 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) {
1535 colibri_carrier_offset = 4832000; /*4.83MHz */
1536 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1537 colibri_carrier_offset = 2700000; /*2.70MHz */
1538 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1539 | V4L2_STD_SECAM)) {
1540 colibri_carrier_offset = 2100000; /*2.10MHz */
1543 return colibri_carrier_offset;
1546 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1547 u8 spectral_invert, u32 mode)
1549 unsigned long pll_freq_word;
1550 u32 dif_misc_ctrl_value = 0;
1551 u64 pll_freq_u64 = 0;
1554 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1555 if_freq, spectral_invert, mode);
1558 if (mode == TUNER_MODE_FM_RADIO) {
1559 pll_freq_word = 0x905A1CAC;
1560 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1562 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1563 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1564 pll_freq_word = if_freq;
1565 pll_freq_u64 = (u64)pll_freq_word << 28L;
1566 do_div(pll_freq_u64, 50000000);
1567 pll_freq_word = (u32)pll_freq_u64;
1568 /*pll_freq_word = 0x3463497;*/
1569 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1571 if (spectral_invert) {
1573 /* Enable Spectral Invert*/
1574 vid_blk_read_word(dev, DIF_MISC_CTRL,
1575 &dif_misc_ctrl_value);
1576 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1577 vid_blk_write_word(dev, DIF_MISC_CTRL,
1578 dif_misc_ctrl_value);
1581 /* Disable Spectral Invert*/
1582 vid_blk_read_word(dev, DIF_MISC_CTRL,
1583 &dif_misc_ctrl_value);
1584 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1585 vid_blk_write_word(dev, DIF_MISC_CTRL,
1586 dif_misc_ctrl_value);
1589 if_freq = (if_freq/100000)*100000;
1591 if (if_freq < 3000000)
1594 if (if_freq > 16000000)
1598 cx231xx_info("Enter IF=%zd\n",
1599 ARRAY_SIZE(Dif_set_array));
1600 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) {
1601 if (Dif_set_array[i].if_freq == if_freq) {
1602 vid_blk_write_word(dev,
1603 Dif_set_array[i].register_address, Dif_set_array[i].value);
1608 /******************************************************************************
1609 * D I F - B L O C K C O N T R O L functions *
1610 ******************************************************************************/
1611 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1612 u32 function_mode, u32 standard)
1617 if (mode == V4L2_TUNER_RADIO) {
1619 /* lo if big signal */
1620 status = cx231xx_reg_mask_write(dev,
1621 VID_BLK_I2C_ADDRESS, 32,
1622 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1623 /* FUNC_MODE = DIF */
1624 status = cx231xx_reg_mask_write(dev,
1625 VID_BLK_I2C_ADDRESS, 32,
1626 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1628 status = cx231xx_reg_mask_write(dev,
1629 VID_BLK_I2C_ADDRESS, 32,
1630 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1632 status = cx231xx_reg_mask_write(dev,
1633 VID_BLK_I2C_ADDRESS, 32,
1634 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1635 } else if (standard != DIF_USE_BASEBAND) {
1636 if (standard & V4L2_STD_MN) {
1637 /* lo if big signal */
1638 status = cx231xx_reg_mask_write(dev,
1639 VID_BLK_I2C_ADDRESS, 32,
1640 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1641 /* FUNC_MODE = DIF */
1642 status = cx231xx_reg_mask_write(dev,
1643 VID_BLK_I2C_ADDRESS, 32,
1644 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1647 status = cx231xx_reg_mask_write(dev,
1648 VID_BLK_I2C_ADDRESS, 32,
1649 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1651 status = cx231xx_reg_mask_write(dev,
1652 VID_BLK_I2C_ADDRESS, 32,
1653 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1654 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1655 status = cx231xx_reg_mask_write(dev,
1656 VID_BLK_I2C_ADDRESS, 32,
1657 AUD_IO_CTRL, 0, 31, 0x00000003);
1658 } else if ((standard == V4L2_STD_PAL_I) |
1659 (standard & V4L2_STD_PAL_D) |
1660 (standard & V4L2_STD_SECAM)) {
1662 /* lo if big signal */
1663 status = cx231xx_reg_mask_write(dev,
1664 VID_BLK_I2C_ADDRESS, 32,
1665 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1666 /* FUNC_MODE = DIF */
1667 status = cx231xx_reg_mask_write(dev,
1668 VID_BLK_I2C_ADDRESS, 32,
1669 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1672 status = cx231xx_reg_mask_write(dev,
1673 VID_BLK_I2C_ADDRESS, 32,
1674 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1676 status = cx231xx_reg_mask_write(dev,
1677 VID_BLK_I2C_ADDRESS, 32,
1678 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1680 /* default PAL BG */
1682 /* lo if big signal */
1683 status = cx231xx_reg_mask_write(dev,
1684 VID_BLK_I2C_ADDRESS, 32,
1685 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1686 /* FUNC_MODE = DIF */
1687 status = cx231xx_reg_mask_write(dev,
1688 VID_BLK_I2C_ADDRESS, 32,
1689 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1692 status = cx231xx_reg_mask_write(dev,
1693 VID_BLK_I2C_ADDRESS, 32,
1694 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1696 status = cx231xx_reg_mask_write(dev,
1697 VID_BLK_I2C_ADDRESS, 32,
1698 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1705 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1708 u32 dif_misc_ctrl_value = 0;
1711 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1713 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1714 if (standard != DIF_USE_BASEBAND)
1715 dev->norm = standard;
1717 switch (dev->model) {
1718 case CX231XX_BOARD_CNXT_CARRAERA:
1719 case CX231XX_BOARD_CNXT_RDE_250:
1720 case CX231XX_BOARD_CNXT_SHELBY:
1721 case CX231XX_BOARD_CNXT_RDU_250:
1722 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1723 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1724 case CX231XX_BOARD_OTG102:
1727 case CX231XX_BOARD_CNXT_RDE_253S:
1728 case CX231XX_BOARD_CNXT_RDU_253S:
1729 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
1730 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
1737 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1738 func_mode, standard);
1740 if (standard == DIF_USE_BASEBAND) { /* base band */
1741 /* There is a different SRC_PHASE_INC value
1742 for baseband vs. DIF */
1743 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1744 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1745 &dif_misc_ctrl_value);
1746 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1747 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1748 dif_misc_ctrl_value);
1749 } else if (standard & V4L2_STD_PAL_D) {
1750 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1751 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1752 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1753 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1754 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1755 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1756 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1757 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1759 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1761 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1763 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1765 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1766 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1767 DIF_AGC_IF_INT_CURRENT, 0, 31,
1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1770 DIF_AGC_RF_CURRENT, 0, 31,
1772 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1773 DIF_VIDEO_AGC_CTRL, 0, 31,
1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_VID_AUD_OVERRIDE, 0, 31,
1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1780 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1781 DIF_COMP_FLT_CTRL, 0, 31,
1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1784 DIF_SRC_PHASE_INC, 0, 31,
1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1787 DIF_SRC_GAIN_CONTROL, 0, 31,
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1791 /* Save the Spec Inversion value */
1792 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1793 dif_misc_ctrl_value |= 0x3a023F11;
1794 } else if (standard & V4L2_STD_PAL_I) {
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1798 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1799 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1800 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1804 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1806 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1808 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1811 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1812 DIF_AGC_IF_INT_CURRENT, 0, 31,
1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1815 DIF_AGC_RF_CURRENT, 0, 31,
1817 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1818 DIF_VIDEO_AGC_CTRL, 0, 31,
1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1821 DIF_VID_AUD_OVERRIDE, 0, 31,
1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1824 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1825 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1826 DIF_COMP_FLT_CTRL, 0, 31,
1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1829 DIF_SRC_PHASE_INC, 0, 31,
1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1832 DIF_SRC_GAIN_CONTROL, 0, 31,
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1836 /* Save the Spec Inversion value */
1837 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1838 dif_misc_ctrl_value |= 0x3a033F11;
1839 } else if (standard & V4L2_STD_PAL_M) {
1840 /* improved Low Frequency Phase Noise */
1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1843 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1844 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1845 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1846 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1848 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1850 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1852 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1854 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1855 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1857 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1859 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1861 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1863 /* Save the Spec Inversion value */
1864 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1865 dif_misc_ctrl_value |= 0x3A0A3F10;
1866 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1867 /* improved Low Frequency Phase Noise */
1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1872 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1873 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1875 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1877 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1879 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1881 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1883 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1885 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1887 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1889 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1891 /* Save the Spec Inversion value */
1892 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1893 dif_misc_ctrl_value = 0x3A093F10;
1894 } else if (standard &
1895 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1896 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1898 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1899 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1900 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1901 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1902 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1903 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1904 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1905 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1907 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1909 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1911 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1913 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1914 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1915 DIF_AGC_IF_INT_CURRENT, 0, 31,
1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1918 DIF_AGC_RF_CURRENT, 0, 31,
1920 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1921 DIF_VID_AUD_OVERRIDE, 0, 31,
1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1924 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1926 DIF_COMP_FLT_CTRL, 0, 31,
1928 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1929 DIF_SRC_PHASE_INC, 0, 31,
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 DIF_SRC_GAIN_CONTROL, 0, 31,
1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1935 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1936 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1937 DIF_VIDEO_AGC_CTRL, 0, 31,
1940 /* Save the Spec Inversion value */
1941 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1942 dif_misc_ctrl_value |= 0x3a023F11;
1943 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1944 /* Is it SECAM_L1? */
1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1946 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1947 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1948 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1950 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1952 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1954 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1956 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1960 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1961 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1962 DIF_AGC_IF_INT_CURRENT, 0, 31,
1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1965 DIF_AGC_RF_CURRENT, 0, 31,
1967 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1968 DIF_VID_AUD_OVERRIDE, 0, 31,
1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1971 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1973 DIF_COMP_FLT_CTRL, 0, 31,
1975 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1976 DIF_SRC_PHASE_INC, 0, 31,
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 DIF_SRC_GAIN_CONTROL, 0, 31,
1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1982 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1983 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1984 DIF_VIDEO_AGC_CTRL, 0, 31,
1987 /* Save the Spec Inversion value */
1988 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1989 dif_misc_ctrl_value |= 0x3a023F11;
1991 } else if (standard & V4L2_STD_NTSC_M) {
1992 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1993 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
1995 /* For NTSC the centre frequency of video coming out of
1996 sidewinder is around 7.1MHz or 3.6MHz depending on the
1997 spectral inversion. so for a non spectrally inverted channel
1998 the pll freq word is 0x03420c49
2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2003 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2004 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2005 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2006 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2008 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2010 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2012 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2014 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2016 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2018 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2020 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2023 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2024 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2026 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2028 /* Save the Spec Inversion value */
2029 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2030 dif_misc_ctrl_value |= 0x3a003F10;
2032 /* default PAL BG */
2033 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2034 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2035 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2036 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2037 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2038 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2039 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2040 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2042 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2044 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2046 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2048 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2049 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2050 DIF_AGC_IF_INT_CURRENT, 0, 31,
2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2053 DIF_AGC_RF_CURRENT, 0, 31,
2055 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2056 DIF_VIDEO_AGC_CTRL, 0, 31,
2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2059 DIF_VID_AUD_OVERRIDE, 0, 31,
2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2062 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2063 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2064 DIF_COMP_FLT_CTRL, 0, 31,
2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2067 DIF_SRC_PHASE_INC, 0, 31,
2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2070 DIF_SRC_GAIN_CONTROL, 0, 31,
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2074 /* Save the Spec Inversion value */
2075 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2076 dif_misc_ctrl_value |= 0x3a013F11;
2079 /* The AGC values should be the same for all standards,
2080 AUD_SRC_SEL[19] should always be disabled */
2081 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2083 /* It is still possible to get Set Standard calls even when we
2085 This is done to override the value for FM. */
2086 if (dev->active_mode == V4L2_TUNER_RADIO)
2087 dif_misc_ctrl_value = 0x7a080000;
2089 /* Write the calculated value for misc ontrol register */
2090 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2095 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2100 /* Set the RF and IF k_agc values to 3 */
2101 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2102 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2103 dwval |= 0x33000000;
2105 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2110 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2114 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2116 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2117 * SECAM L/B/D standards */
2118 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2119 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2121 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2122 V4L2_STD_SECAM_D)) {
2123 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2124 dwval &= ~FLD_DIF_IF_REF;
2125 dwval |= 0x88000300;
2127 dwval |= 0x88000000;
2129 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2130 dwval &= ~FLD_DIF_IF_REF;
2131 dwval |= 0xCC000300;
2133 dwval |= 0x44000000;
2136 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2138 return status == sizeof(dwval) ? 0 : -EIO;
2141 /******************************************************************************
2142 * I 2 S - B L O C K C O N T R O L functions *
2143 ******************************************************************************/
2144 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2149 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2150 CH_PWR_CTRL1, 1, &value, 1);
2151 /* enables clock to delta-sigma and decimation filter */
2153 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2154 CH_PWR_CTRL1, 1, value, 1);
2155 /* power up all channel */
2156 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2157 CH_PWR_CTRL2, 1, 0x00, 1);
2162 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2163 enum AV_MODE avmode)
2168 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2169 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2170 CH_PWR_CTRL2, 1, &value, 1);
2172 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2173 CH_PWR_CTRL2, 1, value, 1);
2175 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2176 CH_PWR_CTRL2, 1, 0x00, 1);
2182 /* set i2s_blk for audio input types */
2183 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2187 switch (audio_input) {
2188 case CX231XX_AMUX_LINE_IN:
2189 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2190 CH_PWR_CTRL2, 1, 0x00, 1);
2191 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2192 CH_PWR_CTRL1, 1, 0x80, 1);
2194 case CX231XX_AMUX_VIDEO:
2199 dev->ctl_ainput = audio_input;
2204 /******************************************************************************
2205 * P O W E R C O N T R O L functions *
2206 ******************************************************************************/
2207 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2209 u8 value[4] = { 0, 0, 0, 0 };
2213 if (dev->power_mode != mode)
2214 dev->power_mode = mode;
2216 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2221 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2226 tmp = le32_to_cpu(*((u32 *) value));
2229 case POLARIS_AVMODE_ENXTERNAL_AV:
2231 tmp &= (~PWR_MODE_MASK);
2234 value[0] = (u8) tmp;
2235 value[1] = (u8) (tmp >> 8);
2236 value[2] = (u8) (tmp >> 16);
2237 value[3] = (u8) (tmp >> 24);
2238 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2239 PWR_CTL_EN, value, 4);
2240 msleep(PWR_SLEEP_INTERVAL);
2243 value[0] = (u8) tmp;
2244 value[1] = (u8) (tmp >> 8);
2245 value[2] = (u8) (tmp >> 16);
2246 value[3] = (u8) (tmp >> 24);
2248 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2250 msleep(PWR_SLEEP_INTERVAL);
2252 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2253 value[0] = (u8) tmp;
2254 value[1] = (u8) (tmp >> 8);
2255 value[2] = (u8) (tmp >> 16);
2256 value[3] = (u8) (tmp >> 24);
2257 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2258 PWR_CTL_EN, value, 4);
2260 /* reset state of xceive tuner */
2261 dev->xc_fw_load_done = 0;
2264 case POLARIS_AVMODE_ANALOGT_TV:
2266 tmp |= PWR_DEMOD_EN;
2267 tmp |= (I2C_DEMOD_EN);
2268 value[0] = (u8) tmp;
2269 value[1] = (u8) (tmp >> 8);
2270 value[2] = (u8) (tmp >> 16);
2271 value[3] = (u8) (tmp >> 24);
2272 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2273 PWR_CTL_EN, value, 4);
2274 msleep(PWR_SLEEP_INTERVAL);
2276 if (!(tmp & PWR_TUNER_EN)) {
2277 tmp |= (PWR_TUNER_EN);
2278 value[0] = (u8) tmp;
2279 value[1] = (u8) (tmp >> 8);
2280 value[2] = (u8) (tmp >> 16);
2281 value[3] = (u8) (tmp >> 24);
2282 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2283 PWR_CTL_EN, value, 4);
2284 msleep(PWR_SLEEP_INTERVAL);
2287 if (!(tmp & PWR_AV_EN)) {
2289 value[0] = (u8) tmp;
2290 value[1] = (u8) (tmp >> 8);
2291 value[2] = (u8) (tmp >> 16);
2292 value[3] = (u8) (tmp >> 24);
2293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2294 PWR_CTL_EN, value, 4);
2295 msleep(PWR_SLEEP_INTERVAL);
2297 if (!(tmp & PWR_ISO_EN)) {
2299 value[0] = (u8) tmp;
2300 value[1] = (u8) (tmp >> 8);
2301 value[2] = (u8) (tmp >> 16);
2302 value[3] = (u8) (tmp >> 24);
2303 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2304 PWR_CTL_EN, value, 4);
2305 msleep(PWR_SLEEP_INTERVAL);
2308 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2309 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2310 value[0] = (u8) tmp;
2311 value[1] = (u8) (tmp >> 8);
2312 value[2] = (u8) (tmp >> 16);
2313 value[3] = (u8) (tmp >> 24);
2314 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2315 PWR_CTL_EN, value, 4);
2316 msleep(PWR_SLEEP_INTERVAL);
2319 if (dev->board.tuner_type != TUNER_ABSENT) {
2321 cx231xx_enable_i2c_port_3(dev, true);
2323 /* reset the Tuner */
2324 if (dev->board.tuner_gpio)
2325 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2327 if (dev->cx231xx_reset_analog_tuner)
2328 dev->cx231xx_reset_analog_tuner(dev);
2333 case POLARIS_AVMODE_DIGITAL:
2334 if (!(tmp & PWR_TUNER_EN)) {
2335 tmp |= (PWR_TUNER_EN);
2336 value[0] = (u8) tmp;
2337 value[1] = (u8) (tmp >> 8);
2338 value[2] = (u8) (tmp >> 16);
2339 value[3] = (u8) (tmp >> 24);
2340 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2341 PWR_CTL_EN, value, 4);
2342 msleep(PWR_SLEEP_INTERVAL);
2344 if (!(tmp & PWR_AV_EN)) {
2346 value[0] = (u8) tmp;
2347 value[1] = (u8) (tmp >> 8);
2348 value[2] = (u8) (tmp >> 16);
2349 value[3] = (u8) (tmp >> 24);
2350 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2351 PWR_CTL_EN, value, 4);
2352 msleep(PWR_SLEEP_INTERVAL);
2354 if (!(tmp & PWR_ISO_EN)) {
2356 value[0] = (u8) tmp;
2357 value[1] = (u8) (tmp >> 8);
2358 value[2] = (u8) (tmp >> 16);
2359 value[3] = (u8) (tmp >> 24);
2360 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2361 PWR_CTL_EN, value, 4);
2362 msleep(PWR_SLEEP_INTERVAL);
2365 tmp &= (~PWR_AV_MODE);
2366 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2367 value[0] = (u8) tmp;
2368 value[1] = (u8) (tmp >> 8);
2369 value[2] = (u8) (tmp >> 16);
2370 value[3] = (u8) (tmp >> 24);
2371 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2372 PWR_CTL_EN, value, 4);
2373 msleep(PWR_SLEEP_INTERVAL);
2375 if (!(tmp & PWR_DEMOD_EN)) {
2376 tmp |= PWR_DEMOD_EN;
2377 value[0] = (u8) tmp;
2378 value[1] = (u8) (tmp >> 8);
2379 value[2] = (u8) (tmp >> 16);
2380 value[3] = (u8) (tmp >> 24);
2381 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2382 PWR_CTL_EN, value, 4);
2383 msleep(PWR_SLEEP_INTERVAL);
2386 if (dev->board.tuner_type != TUNER_ABSENT) {
2389 * Hauppauge Exeter seems to need to do something different!
2391 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER)
2392 cx231xx_enable_i2c_port_3(dev, false);
2394 cx231xx_enable_i2c_port_3(dev, true);
2396 /* reset the Tuner */
2397 if (dev->board.tuner_gpio)
2398 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2400 if (dev->cx231xx_reset_analog_tuner)
2401 dev->cx231xx_reset_analog_tuner(dev);
2409 msleep(PWR_SLEEP_INTERVAL);
2411 /* For power saving, only enable Pwr_resetout_n
2412 when digital TV is selected. */
2413 if (mode == POLARIS_AVMODE_DIGITAL) {
2414 tmp |= PWR_RESETOUT_EN;
2415 value[0] = (u8) tmp;
2416 value[1] = (u8) (tmp >> 8);
2417 value[2] = (u8) (tmp >> 16);
2418 value[3] = (u8) (tmp >> 24);
2419 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2420 PWR_CTL_EN, value, 4);
2421 msleep(PWR_SLEEP_INTERVAL);
2424 /* update power control for afe */
2425 status = cx231xx_afe_update_power_control(dev, mode);
2427 /* update power control for i2s_blk */
2428 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2430 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2436 int cx231xx_power_suspend(struct cx231xx *dev)
2438 u8 value[4] = { 0, 0, 0, 0 };
2442 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2447 tmp = le32_to_cpu(*((u32 *) value));
2448 tmp &= (~PWR_MODE_MASK);
2450 value[0] = (u8) tmp;
2451 value[1] = (u8) (tmp >> 8);
2452 value[2] = (u8) (tmp >> 16);
2453 value[3] = (u8) (tmp >> 24);
2454 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2460 /******************************************************************************
2461 * S T R E A M C O N T R O L functions *
2462 ******************************************************************************/
2463 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2465 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2469 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2470 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2475 tmp = le32_to_cpu(*((u32 *) value));
2477 value[0] = (u8) tmp;
2478 value[1] = (u8) (tmp >> 8);
2479 value[2] = (u8) (tmp >> 16);
2480 value[3] = (u8) (tmp >> 24);
2482 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2488 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2490 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2494 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2496 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2500 tmp = le32_to_cpu(*((u32 *) value));
2502 value[0] = (u8) tmp;
2503 value[1] = (u8) (tmp >> 8);
2504 value[2] = (u8) (tmp >> 16);
2505 value[3] = (u8) (tmp >> 24);
2507 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2513 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2517 u8 val[4] = { 0, 0, 0, 0 };
2519 if (dev->udev->speed == USB_SPEED_HIGH) {
2520 switch (media_type) {
2522 cx231xx_info("%s: Audio enter HANC\n", __func__);
2524 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2528 cx231xx_info("%s: set vanc registers\n", __func__);
2529 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2533 cx231xx_info("%s: set hanc registers\n", __func__);
2535 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2539 cx231xx_info("%s: set video registers\n", __func__);
2540 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2543 case TS1_serial_mode:
2544 cx231xx_info("%s: set ts1 registers", __func__);
2546 if (dev->board.has_417) {
2547 cx231xx_info(" MPEG\n");
2548 value &= 0xFFFFFFFC;
2551 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2557 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2558 TS1_CFG_REG, val, 4);
2564 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2565 TS1_LENGTH_REG, val, 4);
2568 cx231xx_info(" BDA\n");
2569 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2570 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2574 case TS1_parallel_mode:
2575 cx231xx_info("%s: set ts1 parallel mode registers\n",
2577 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2578 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2582 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2588 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2592 struct pcb_config *pcb_config;
2594 /* get EP for media type */
2595 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2597 if (pcb_config->config_num) {
2598 switch (media_type) {
2600 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2603 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2606 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2609 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2611 case TS1_serial_mode:
2612 case TS1_parallel_mode:
2613 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2616 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2622 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2627 /* enable video capture */
2629 rc = cx231xx_start_stream(dev, ep_mask);
2631 /* disable video capture */
2633 rc = cx231xx_stop_stream(dev, ep_mask);
2638 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2640 /*****************************************************************************
2641 * G P I O B I T control functions *
2642 ******************************************************************************/
2643 static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val)
2647 gpio_val = cpu_to_le32(gpio_val);
2648 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0);
2653 static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val)
2658 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1);
2659 *gpio_val = le32_to_cpu(tmp);
2665 * cx231xx_set_gpio_direction
2666 * Sets the direction of the GPIO pin to input or output
2669 * pin_number : The GPIO Pin number to program the direction for
2671 * pin_value : The Direction of the GPIO Pin under reference.
2672 * 0 = Input direction
2673 * 1 = Output direction
2675 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2676 int pin_number, int pin_value)
2681 /* Check for valid pin_number - if 32 , bail out */
2682 if (pin_number >= 32)
2687 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2689 value = dev->gpio_dir | (1 << pin_number);
2691 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val);
2693 /* cache the value for future */
2694 dev->gpio_dir = value;
2700 * cx231xx_set_gpio_value
2701 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2702 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2705 * pin_number : The GPIO Pin number to program the direction for
2706 * pin_value : The value of the GPIO Pin under reference.
2710 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2715 /* Check for valid pin_number - if 0xFF , bail out */
2716 if (pin_number >= 32)
2719 /* first do a sanity check - if the Pin is not output, make it output */
2720 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2721 /* It was in input mode */
2722 value = dev->gpio_dir | (1 << pin_number);
2723 dev->gpio_dir = value;
2724 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2730 value = dev->gpio_val & (~(1 << pin_number));
2732 value = dev->gpio_val | (1 << pin_number);
2734 /* store the value */
2735 dev->gpio_val = value;
2737 /* toggle bit0 of GP_IO */
2738 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2743 /*****************************************************************************
2744 * G P I O I2C related functions *
2745 ******************************************************************************/
2746 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2750 /* set SCL to output 1 ; set SDA to output 1 */
2751 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2752 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2753 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2754 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2756 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2760 /* set SCL to output 1; set SDA to output 0 */
2761 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2762 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2764 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2768 /* set SCL to output 0; set SDA to output 0 */
2769 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2770 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2772 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2779 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2783 /* set SCL to output 0; set SDA to output 0 */
2784 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2785 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2787 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2788 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2790 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2794 /* set SCL to output 1; set SDA to output 0 */
2795 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2796 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2798 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2802 /* set SCL to input ,release SCL cable control
2803 set SDA to input ,release SDA cable control */
2804 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2805 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2808 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2815 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2820 /* set SCL to output ; set SDA to output */
2821 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2822 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2824 for (i = 0; i < 8; i++) {
2825 if (((data << i) & 0x80) == 0) {
2826 /* set SCL to output 0; set SDA to output 0 */
2827 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2828 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2829 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2832 /* set SCL to output 1; set SDA to output 0 */
2833 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2834 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2837 /* set SCL to output 0; set SDA to output 0 */
2838 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2839 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2842 /* set SCL to output 0; set SDA to output 1 */
2843 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2844 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2845 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2848 /* set SCL to output 1; set SDA to output 1 */
2849 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2850 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2853 /* set SCL to output 0; set SDA to output 1 */
2854 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2855 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2862 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2866 u32 gpio_logic_value = 0;
2870 for (i = 0; i < 8; i++) { /* send write I2c addr */
2872 /* set SCL to output 0; set SDA to input */
2873 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2877 /* set SCL to output 1; set SDA to input */
2878 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2879 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2882 /* get SDA data bit */
2883 gpio_logic_value = dev->gpio_val;
2884 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2886 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2887 value |= (1 << (8 - i - 1));
2889 dev->gpio_val = gpio_logic_value;
2892 /* set SCL to output 0,finish the read latest SCL signal.
2893 !!!set SDA to input, never to modify SDA direction at
2895 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2896 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2898 /* store the value */
2899 *buf = value & 0xff;
2904 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2907 u32 gpio_logic_value = 0;
2911 /* clock stretch; set SCL to input; set SDA to input;
2912 get SCL value till SCL = 1 */
2913 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2914 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2916 gpio_logic_value = dev->gpio_val;
2917 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2921 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2924 } while (((dev->gpio_val &
2925 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2929 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2934 * through clock stretch, slave has given a SCL signal,
2935 * so the SDA data can be directly read.
2937 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val);
2939 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2940 dev->gpio_val = gpio_logic_value;
2941 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2944 dev->gpio_val = gpio_logic_value;
2945 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2948 /* read SDA end, set the SCL to output 0, after this operation,
2949 SDA direction can be changed. */
2950 dev->gpio_val = gpio_logic_value;
2951 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2952 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2953 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2958 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2962 /* set SDA to ouput */
2963 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2964 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2966 /* set SCL = 0 (output); set SDA = 0 (output) */
2967 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2968 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2969 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2971 /* set SCL = 1 (output); set SDA = 0 (output) */
2972 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2973 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2975 /* set SCL = 0 (output); set SDA = 0 (output) */
2976 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2977 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2979 /* set SDA to input,and then the slave will read data from SDA. */
2980 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2981 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2986 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2990 /* set scl to output ; set sda to input */
2991 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2992 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2993 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2995 /* set scl to output 0; set sda to input */
2996 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
2999 /* set scl to output 1; set sda to input */
3000 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3001 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val);
3006 /*****************************************************************************
3007 * G P I O I2C related functions *
3008 ******************************************************************************/
3009 /* cx231xx_gpio_i2c_read
3010 * Function to read data from gpio based I2C interface
3012 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3018 mutex_lock(&dev->gpio_i2c_lock);
3021 status = cx231xx_gpio_i2c_start(dev);
3023 /* write dev_addr */
3024 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3027 status = cx231xx_gpio_i2c_read_ack(dev);
3030 for (i = 0; i < len; i++) {
3033 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3035 if ((i + 1) != len) {
3036 /* only do write ack if we more length */
3037 status = cx231xx_gpio_i2c_write_ack(dev);
3041 /* write NAK - inform reads are complete */
3042 status = cx231xx_gpio_i2c_write_nak(dev);
3045 status = cx231xx_gpio_i2c_end(dev);
3047 /* release the lock */
3048 mutex_unlock(&dev->gpio_i2c_lock);
3053 /* cx231xx_gpio_i2c_write
3054 * Function to write data to gpio based I2C interface
3056 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3061 mutex_lock(&dev->gpio_i2c_lock);
3064 cx231xx_gpio_i2c_start(dev);
3066 /* write dev_addr */
3067 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3070 cx231xx_gpio_i2c_read_ack(dev);
3072 for (i = 0; i < len; i++) {
3074 cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3077 cx231xx_gpio_i2c_read_ack(dev);
3081 cx231xx_gpio_i2c_end(dev);
3083 /* release the lock */
3084 mutex_unlock(&dev->gpio_i2c_lock);