drivers/media/video/rk_camsys/camsys_soc_rk3288.c

   1 #include "camsys_soc_priv.h"
   2 #include "camsys_soc_rk3288.h"
   3
   4
   5 struct mipiphy_hsfreqrange_s {
   6     unsigned int range_l;
   7     unsigned int range_h;
   8     unsigned char cfg_bit;
   9 };
  10
  11 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
  12     {80,90,0x00},
  13     {90,100,0x10},
  14     {100,110,0x20},
  15     {110,130,0x01},
  16     {130,140,0x11},
  17     {140,150,0x21},
  18     {150,170,0x02},
  19     {170,180,0x12},
  20     {180,200,0x22},
  21     {200,220,0x03},
  22     {220,240,0x13},
  23     {240,250,0x23},
  24     {250,270,0x4},
  25     {270,300,0x14},
  26     {300,330,0x5},
  27     {330,360,0x15},
  28     {360,400,0x25},
  29     {400,450,0x06},
  30     {450,500,0x16},
  31     {500,550,0x07},
  32     {550,600,0x17},
  33     {600,650,0x08},
  34     {650,700,0x18},
  35     {700,750,0x09},
  36     {750,800,0x19},
  37     {800,850,0x29},
  38     {850,900,0x39},
  39     {900,950,0x0a},
  40     {950,1000,0x1a}
  41
  42 };
  43
  44
  45 static int camsys_rk3288_mipiphy0_wr_reg(unsigned char addr, unsigned char data)
  46 {
  47     //TESTCLK=1
  48     write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
  49     //TESTEN =1,TESTDIN=addr
  50     write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
  51     //TESTCLK=0
  52         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
  53
  54     if(data != 0xff){ //write data ?
  55         //TESTEN =0,TESTDIN=data
  56         write_grf_reg(GRF_SOC_CON14_OFFSET, (( data << DPHY_RX0_TESTDIN_OFFSET)|DPHY_RX0_TESTDIN_MASK |DPHY_RX0_TESTEN_MASK));
  57
  58         //TESTCLK=1
  59         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
  60     }
  61     return 0;
  62 }
  63 #if 0
  64 static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr)
  65 {
  66     return read_grf_reg(GRF_SOC_STATUS21);
  67 }
  68 #endif
  69 static int camsys_rk3288_mipiphy1_wr_reg(unsigned int phy_virt,unsigned char addr, unsigned char data)
  70 {
  71
  72     write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,(0x00010000|addr));    //TESTEN =1,TESTDIN=addr
  73     write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000000);         //TESTCLK=0
  74     write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,(0x00000000|data));    //TESTEN =0,TESTDIN=data
  75     write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002);         //TESTCLK=1
  76
  77     return 0;
  78 }
  79
  80 static int camsys_rk3288_mipiphy1_rd_reg(unsigned int phy_virt,unsigned char addr)
  81 {
  82     return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1)&0xff00))>>8);
  83 }
  84
  85 static int camsys_rk3288_mipihpy_cfg (camsys_mipiphy_soc_para_t *para)
  86 {
  87     unsigned char hsfreqrange=0xff,i;
  88     struct mipiphy_hsfreqrange_s *hsfreqrange_p;
  89     unsigned int phy_virt, phy_index;
  90     unsigned int *base;
  91
  92     phy_index = para->phy->phy_index;
  93     if (para->camsys_dev->mipiphy[phy_index].reg!=NULL) {
  94         phy_virt  = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
  95     } else {
  96         phy_virt = 0x00;
  97     }
  98
  99     if ((para->phy->bit_rate == 0) || (para->phy->data_en_bit == 0)) {
 100         if (para->phy->phy_index == 0) {
 101             base = (unsigned int *)para->camsys_dev->devmems.registermem->vir_base;
 102             *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4) &= ~(0x0f<<8);
 103             camsys_trace(1, "mipi phy 0 standby!");
 104         } else if (para->phy->phy_index == 1) {
 105             write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000000);           //SHUTDOWNZ=0
 106             write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000000);               //RSTZ=0
 107
 108             camsys_trace(1, "mipi phy 1 standby!");
 109         }
 110
 111         return 0;
 112     }
 113
 114
 115     hsfreqrange_p = mipiphy_hsfreqrange;
 116     for (i=0; i<(sizeof(mipiphy_hsfreqrange)/sizeof(struct mipiphy_hsfreqrange_s)); i++) {
 117
 118         if ((para->phy->bit_rate > hsfreqrange_p->range_l) && (para->phy->bit_rate <= hsfreqrange_p->range_h)) {
 119             hsfreqrange = hsfreqrange_p->cfg_bit;
 120             break;
 121         }
 122         hsfreqrange_p++;
 123     }
 124
 125     if (hsfreqrange == 0xff) {
 126         camsys_err("mipi phy config bitrate %d Mbps isn't supported!",para->phy->bit_rate);
 127         hsfreqrange = 0x00;
 128     }
 129     hsfreqrange <<= 1;
 130
 131     if (para->phy->phy_index == 0) {
 132         write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (para->phy->phy_index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
 133
 134         //  set lane num
 135         write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_ENABLE_MASK | (para->phy->data_en_bit << DPHY_RX0_ENABLE_OFFSET_BITS));
 136         //  set lan turndisab as 1
 137         write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_TURN_DISABLE_MASK | (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
 138         write_grf_reg(GRF_SOC_CON10_OFFSET, (0x0<<4)|(0xf<<20));
 139         //  set lan turnrequest as 0
 140         write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_RX0_TURN_REQUEST_MASK | (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
 141
 142         //phy start
 143         {
 144             write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK); //TESTCLK=1
 145             write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK |DPHY_RX0_TESTCLR);   //TESTCLR=1
 146             udelay(100);
 147             write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK); //TESTCLR=0  zyc
 148             udelay(100);
 149
 150             //set clock lane
 151             camsys_rk3288_mipiphy0_wr_reg(0x34,0x15);
 152             if (para->phy->data_en_bit >= 0x00)
 153                 camsys_rk3288_mipiphy0_wr_reg(0x44,hsfreqrange);
 154             if (para->phy->data_en_bit >= 0x01)
 155                 camsys_rk3288_mipiphy0_wr_reg(0x54,hsfreqrange);
 156             if (para->phy->data_en_bit >= 0x04) {
 157                 camsys_rk3288_mipiphy0_wr_reg(0x84,hsfreqrange);
 158                 camsys_rk3288_mipiphy0_wr_reg(0x94,hsfreqrange);
 159             }
 160
 161             //Normal operation
 162             camsys_rk3288_mipiphy0_wr_reg(0x0,-1);
 163             write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);    //TESTCLK=1
 164             write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN_MASK));                     //TESTEN =0
 165         }
 166
 167         base = (unsigned int *)para->camsys_dev->devmems.registermem->vir_base;
 168         *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4) |= (0x0f<<8);
 169
 170     } else if (para->phy->phy_index == 1){
 171
 172         write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (para->phy->phy_index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
 173         write_grf_reg(GRF_SOC_CON6_OFFSET, DSI_CSI_TESTBUS_SEL_MASK | (1<<DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
 174
 175         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
 176         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
 177         write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
 178
 179         //  set lane num
 180         write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_ENABLE_MASK | (para->phy->data_en_bit << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
 181         //  set lan turndisab as 1
 182         write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_TURN_DISABLE_MASK | (0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
 183         //  set lan turnrequest as 0
 184         write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_TX1RX1_TURN_REQUEST_MASK | (0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
 185
 186         //phy1 start
 187         {
 188             write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000000);           //SHUTDOWNZ=0
 189             write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000000);               //RSTZ=0
 190             write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002);          //TESTCLK=1
 191             write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000003);          //TESTCLR=1 TESTCLK=1
 192             udelay(100);
 193             write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002);          //TESTCLR=0 TESTCLK=1
 194             udelay(100);
 195
 196             //set clock lane
 197             camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x34,0x15);
 198             if (para->phy->data_en_bit >= 0x00)
 199                 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x44,hsfreqrange);
 200             if (para->phy->data_en_bit >= 0x01)
 201                 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x54,hsfreqrange);
 202             if (para->phy->data_en_bit >= 0x04) {
 203                 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x84,hsfreqrange);
 204                 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x94,hsfreqrange);
 205             }
 206
 207             camsys_rk3288_mipiphy1_rd_reg(phy_virt,0x0);
 208             write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002);       //TESTCLK=1
 209             write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,0x00000000);       //TESTEN =0
 210             write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000001);        //SHUTDOWNZ=1
 211             write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000001);            //RSTZ=1
 212         }
 213     } else {
 214         camsys_err("mipi phy index %d is invalidate!",para->phy->phy_index);
 215         goto fail;
 216     }
 217
 218     camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x  bit_rate: %dMbps)",para->phy->phy_index,para->phy->data_en_bit, para->phy->bit_rate);
 219
 220
 221     return 0;
 222
 223 fail:
 224     return -1;
 225 }
 226
 227