drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_mtd.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/mtd/nand.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36 #include <linux/platform_data/mtd-onenand-omap2.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  68
  69 /* GPMC ECC control settings */
  70 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  71 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  72 #define GPMC_ECC_CTRL_ECCREG1           0x001
  73 #define GPMC_ECC_CTRL_ECCREG2           0x002
  74 #define GPMC_ECC_CTRL_ECCREG3           0x003
  75 #define GPMC_ECC_CTRL_ECCREG4           0x004
  76 #define GPMC_ECC_CTRL_ECCREG5           0x005
  77 #define GPMC_ECC_CTRL_ECCREG6           0x006
  78 #define GPMC_ECC_CTRL_ECCREG7           0x007
  79 #define GPMC_ECC_CTRL_ECCREG8           0x008
  80 #define GPMC_ECC_CTRL_ECCREG9           0x009
  81
  82 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  83
  84 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  85 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  86 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  87 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  90
  91 #define GPMC_CS0_OFFSET         0x60
  92 #define GPMC_CS_SIZE            0x30
  93 #define GPMC_BCH_SIZE           0x10
  94
  95 #define GPMC_MEM_END            0x3FFFFFFF
  96
  97 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  98 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  99
 100 #define CS_NUM_SHIFT            24
 101 #define ENABLE_PREFETCH         (0x1 << 7)
 102 #define DMA_MPU_MODE            2
 103
 104 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 105 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 106
 107 #define GPMC_HAS_WR_ACCESS              0x1
 108 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 109 #define GPMC_HAS_MUX_AAD                0x4
 110
 111 #define GPMC_NR_WAITPINS                4
 112
 113 #define GPMC_CS_CONFIG1         0x00
 114 #define GPMC_CS_CONFIG2         0x04
 115 #define GPMC_CS_CONFIG3         0x08
 116 #define GPMC_CS_CONFIG4         0x0c
 117 #define GPMC_CS_CONFIG5         0x10
 118 #define GPMC_CS_CONFIG6         0x14
 119 #define GPMC_CS_CONFIG7         0x18
 120 #define GPMC_CS_NAND_COMMAND    0x1c
 121 #define GPMC_CS_NAND_ADDRESS    0x20
 122 #define GPMC_CS_NAND_DATA       0x24
 123
 124 /* Control Commands */
 125 #define GPMC_CONFIG_RDY_BSY     0x00000001
 126 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 127 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 128 #define GPMC_SET_IRQ_STATUS     0x00000004
 129
 130 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 131 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 132 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 133 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 135 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 136 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 138 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 139 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 140 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 141 #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
 142 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 143 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 144 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 145 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 146 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 147 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 148 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 149 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 150 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 151 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 152 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 153 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 154
 155 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 156 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 157 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 158 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 159 /* All CONFIG7 bits except reserved bits */
 160 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 161                                          GPMC_CONFIG7_CSVALID_MASK |     \
 162                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 163
 164 #define GPMC_DEVICETYPE_NOR             0
 165 #define GPMC_DEVICETYPE_NAND            2
 166 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 167 #define WR_RD_PIN_MONITORING            0x00600000
 168
 169 #define GPMC_ENABLE_IRQ         0x0000000d
 170
 171 /* ECC commands */
 172 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 173 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 174 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 175
 176 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 177  */
 178 #define GPMC_NR_IRQ             2
 179
 180 struct gpmc_cs_data {
 181         const char *name;
 182
 183 #define GPMC_CS_RESERVED        (1 << 0)
 184         u32 flags;
 185
 186         struct resource mem;
 187 };
 188
 189 struct gpmc_client_irq  {
 190         unsigned                irq;
 191         u32                     bitmask;
 192 };
 193
 194 /* Structure to save gpmc cs context */
 195 struct gpmc_cs_config {
 196         u32 config1;
 197         u32 config2;
 198         u32 config3;
 199         u32 config4;
 200         u32 config5;
 201         u32 config6;
 202         u32 config7;
 203         int is_valid;
 204 };
 205
 206 /*
 207  * Structure to save/restore gpmc context
 208  * to support core off on OMAP3
 209  */
 210 struct omap3_gpmc_regs {
 211         u32 sysconfig;
 212         u32 irqenable;
 213         u32 timeout_ctrl;
 214         u32 config;
 215         u32 prefetch_config1;
 216         u32 prefetch_config2;
 217         u32 prefetch_control;
 218         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 219 };
 220
 221 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 222 static struct irq_chip gpmc_irq_chip;
 223 static int gpmc_irq_start;
 224
 225 static struct resource  gpmc_mem_root;
 226 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 227 static DEFINE_SPINLOCK(gpmc_mem_lock);
 228 /* Define chip-selects as reserved by default until probe completes */
 229 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 230 static unsigned int gpmc_nr_waitpins;
 231 static struct device *gpmc_dev;
 232 static int gpmc_irq;
 233 static resource_size_t phys_base, mem_size;
 234 static unsigned gpmc_capability;
 235 static void __iomem *gpmc_base;
 236
 237 static struct clk *gpmc_l3_clk;
 238
 239 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 240
 241 static void gpmc_write_reg(int idx, u32 val)
 242 {
 243         writel_relaxed(val, gpmc_base + idx);
 244 }
 245
 246 static u32 gpmc_read_reg(int idx)
 247 {
 248         return readl_relaxed(gpmc_base + idx);
 249 }
 250
 251 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 252 {
 253         void __iomem *reg_addr;
 254
 255         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 256         writel_relaxed(val, reg_addr);
 257 }
 258
 259 static u32 gpmc_cs_read_reg(int cs, int idx)
 260 {
 261         void __iomem *reg_addr;
 262
 263         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 264         return readl_relaxed(reg_addr);
 265 }
 266
 267 /* TODO: Add support for gpmc_fck to clock framework and use it */
 268 static unsigned long gpmc_get_fclk_period(void)
 269 {
 270         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 271
 272         rate /= 1000;
 273         rate = 1000000000 / rate;       /* In picoseconds */
 274
 275         return rate;
 276 }
 277
 278 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 279 {
 280         unsigned long tick_ps;
 281
 282         /* Calculate in picosecs to yield more exact results */
 283         tick_ps = gpmc_get_fclk_period();
 284
 285         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 286 }
 287
 288 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 289 {
 290         unsigned long tick_ps;
 291
 292         /* Calculate in picosecs to yield more exact results */
 293         tick_ps = gpmc_get_fclk_period();
 294
 295         return (time_ps + tick_ps - 1) / tick_ps;
 296 }
 297
 298 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 299 {
 300         return ticks * gpmc_get_fclk_period() / 1000;
 301 }
 302
 303 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 304 {
 305         return ticks * gpmc_get_fclk_period();
 306 }
 307
 308 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 309 {
 310         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 311
 312         return ticks * gpmc_get_fclk_period();
 313 }
 314
 315 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 316 {
 317         u32 l;
 318
 319         l = gpmc_cs_read_reg(cs, reg);
 320         if (value)
 321                 l |= mask;
 322         else
 323                 l &= ~mask;
 324         gpmc_cs_write_reg(cs, reg, l);
 325 }
 326
 327 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 328 {
 329         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 330                            GPMC_CONFIG1_TIME_PARA_GRAN,
 331                            p->time_para_granularity);
 332         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 333                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 334         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 335                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 336         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 337                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 338         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 339                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 340         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 341                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 342                            p->cycle2cyclesamecsen);
 343         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 344                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 345                            p->cycle2cyclediffcsen);
 346 }
 347
 348 #ifdef DEBUG
 349 /**
 350  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 351  * @cs:      Chip Select Region
 352  * @reg:     GPMC_CS_CONFIGn register offset.
 353  * @st_bit:  Start Bit
 354  * @end_bit: End Bit. Must be >= @st_bit.
 355  * @name:    DTS node name, w/o "gpmc,"
 356  * @raw:     Raw Format Option.
 357  *           raw format:  gpmc,name = <value>
 358  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 359  *           Where x ns -- y ns result in the same tick value.
 360  * @noval:   Parameter values equal to 0 are not printed.
 361  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 362  * @return:  Specified timing parameter (after optional @shift).
 363  *
 364  */
 365 static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 366                                bool raw, bool noval, int shift,
 367                                const char *name)
 368 {
 369         u32 l;
 370         int nr_bits;
 371         int mask;
 372
 373         l = gpmc_cs_read_reg(cs, reg);
 374         nr_bits = end_bit - st_bit + 1;
 375         mask = (1 << nr_bits) - 1;
 376         l = (l >> st_bit) & mask;
 377         if (shift)
 378                 l = (shift << l);
 379         if (noval && (l == 0))
 380                 return 0;
 381         if (!raw) {
 382                 /* DTS tick format for timings in ns */
 383                 unsigned int time_ns;
 384                 unsigned int time_ns_min = 0;
 385
 386                 if (l)
 387                         time_ns_min = gpmc_ticks_to_ns(l - 1) + 1;
 388                 time_ns = gpmc_ticks_to_ns(l);
 389                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks */\n",
 390                         name, time_ns, time_ns_min, time_ns, l);
 391         } else {
 392                 /* raw format */
 393                 pr_info("gpmc,%s = <%u>\n", name, l);
 394         }
 395
 396         return l;
 397 }
 398
 399 #define GPMC_PRINT_CONFIG(cs, config) \
 400         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 401                 gpmc_cs_read_reg(cs, config))
 402 #define GPMC_GET_RAW(reg, st, end, field) \
 403         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
 404 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 405         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
 406 #define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
 407         get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
 408 #define GPMC_GET_TICKS(reg, st, end, field) \
 409         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
 410
 411 static void gpmc_show_regs(int cs, const char *desc)
 412 {
 413         pr_info("gpmc cs%i %s:\n", cs, desc);
 414         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 415         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 416         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 417         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 418         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 419         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 420 }
 421
 422 /*
 423  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 424  * see commit c9fb809.
 425  */
 426 static void gpmc_cs_show_timings(int cs, const char *desc)
 427 {
 428         gpmc_show_regs(cs, desc);
 429
 430         pr_info("gpmc cs%i access configuration:\n", cs);
 431         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 432         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 433         GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
 434         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 435         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 436         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 437         GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
 438         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 439         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 440         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 441         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 442         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 443
 444         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 445
 446         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 447
 448         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 449         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 450
 451         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 452         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 453
 454         pr_info("gpmc cs%i timings configuration:\n", cs);
 455         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 456         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 457         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 458
 459         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 460         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 461         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 462
 463         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 464         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 465         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 466         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 467
 468         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 469         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 470         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 471
 472         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 473
 474         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 475         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 476
 477         GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
 478         GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
 479
 480         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 481         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 482 }
 483 #else
 484 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 485 {
 486 }
 487 #endif
 488
 489 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 490                                int time, const char *name)
 491 {
 492         u32 l;
 493         int ticks, mask, nr_bits;
 494
 495         if (time == 0)
 496                 ticks = 0;
 497         else
 498                 ticks = gpmc_ns_to_ticks(time);
 499         nr_bits = end_bit - st_bit + 1;
 500         mask = (1 << nr_bits) - 1;
 501
 502         if (ticks > mask) {
 503                 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
 504                        __func__, cs, name, time, ticks, mask);
 505
 506                 return -1;
 507         }
 508
 509         l = gpmc_cs_read_reg(cs, reg);
 510 #ifdef DEBUG
 511         printk(KERN_INFO
 512                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 513                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 514                         (l >> st_bit) & mask, time);
 515 #endif
 516         l &= ~(mask << st_bit);
 517         l |= ticks << st_bit;
 518         gpmc_cs_write_reg(cs, reg, l);
 519
 520         return 0;
 521 }
 522
 523 #define GPMC_SET_ONE(reg, st, end, field) \
 524         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 525                         t->field, #field) < 0)                  \
 526                 return -1
 527
 528 int gpmc_calc_divider(unsigned int sync_clk)
 529 {
 530         int div;
 531         u32 l;
 532
 533         l = sync_clk + (gpmc_get_fclk_period() - 1);
 534         div = l / gpmc_get_fclk_period();
 535         if (div > 4)
 536                 return -1;
 537         if (div <= 0)
 538                 div = 1;
 539
 540         return div;
 541 }
 542
 543 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 544 {
 545         int div;
 546         u32 l;
 547
 548         gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
 549         div = gpmc_calc_divider(t->sync_clk);
 550         if (div < 0)
 551                 return div;
 552
 553         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 554         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 555         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 556
 557         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 558         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 559         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 560
 561         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 562         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 563         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 564         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 565
 566         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 567         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 568         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 569
 570         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 571
 572         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 573         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 574
 575         GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
 576         GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
 577
 578         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 579                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 580         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 581                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 582
 583         /* caller is expected to have initialized CONFIG1 to cover
 584          * at least sync vs async
 585          */
 586         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 587         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 588 #ifdef DEBUG
 589                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 590                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 591 #endif
 592                 l &= ~0x03;
 593                 l |= (div - 1);
 594                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 595         }
 596
 597         gpmc_cs_bool_timings(cs, &t->bool_timings);
 598         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 599
 600         return 0;
 601 }
 602
 603 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 604 {
 605         u32 l;
 606         u32 mask;
 607
 608         /*
 609          * Ensure that base address is aligned on a
 610          * boundary equal to or greater than size.
 611          */
 612         if (base & (size - 1))
 613                 return -EINVAL;
 614
 615         base >>= GPMC_CHUNK_SHIFT;
 616         mask = (1 << GPMC_SECTION_SHIFT) - size;
 617         mask >>= GPMC_CHUNK_SHIFT;
 618         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 619
 620         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 621         l &= ~GPMC_CONFIG7_MASK;
 622         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 623         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 624         l |= GPMC_CONFIG7_CSVALID;
 625         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 626
 627         return 0;
 628 }
 629
 630 static void gpmc_cs_enable_mem(int cs)
 631 {
 632         u32 l;
 633
 634         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 635         l |= GPMC_CONFIG7_CSVALID;
 636         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 637 }
 638
 639 static void gpmc_cs_disable_mem(int cs)
 640 {
 641         u32 l;
 642
 643         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 644         l &= ~GPMC_CONFIG7_CSVALID;
 645         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 646 }
 647
 648 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 649 {
 650         u32 l;
 651         u32 mask;
 652
 653         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 654         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 655         mask = (l >> 8) & 0x0f;
 656         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 657 }
 658
 659 static int gpmc_cs_mem_enabled(int cs)
 660 {
 661         u32 l;
 662
 663         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 664         return l & GPMC_CONFIG7_CSVALID;
 665 }
 666
 667 static void gpmc_cs_set_reserved(int cs, int reserved)
 668 {
 669         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 670
 671         gpmc->flags |= GPMC_CS_RESERVED;
 672 }
 673
 674 static bool gpmc_cs_reserved(int cs)
 675 {
 676         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 677
 678         return gpmc->flags & GPMC_CS_RESERVED;
 679 }
 680
 681 static void gpmc_cs_set_name(int cs, const char *name)
 682 {
 683         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 684
 685         gpmc->name = name;
 686 }
 687
 688 static const char *gpmc_cs_get_name(int cs)
 689 {
 690         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 691
 692         return gpmc->name;
 693 }
 694
 695 static unsigned long gpmc_mem_align(unsigned long size)
 696 {
 697         int order;
 698
 699         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 700         order = GPMC_CHUNK_SHIFT - 1;
 701         do {
 702                 size >>= 1;
 703                 order++;
 704         } while (size);
 705         size = 1 << order;
 706         return size;
 707 }
 708
 709 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 710 {
 711         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 712         struct resource *res = &gpmc->mem;
 713         int r;
 714
 715         size = gpmc_mem_align(size);
 716         spin_lock(&gpmc_mem_lock);
 717         res->start = base;
 718         res->end = base + size - 1;
 719         r = request_resource(&gpmc_mem_root, res);
 720         spin_unlock(&gpmc_mem_lock);
 721
 722         return r;
 723 }
 724
 725 static int gpmc_cs_delete_mem(int cs)
 726 {
 727         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 728         struct resource *res = &gpmc->mem;
 729         int r;
 730
 731         spin_lock(&gpmc_mem_lock);
 732         r = release_resource(res);
 733         res->start = 0;
 734         res->end = 0;
 735         spin_unlock(&gpmc_mem_lock);
 736
 737         return r;
 738 }
 739
 740 /**
 741  * gpmc_cs_remap - remaps a chip-select physical base address
 742  * @cs:         chip-select to remap
 743  * @base:       physical base address to re-map chip-select to
 744  *
 745  * Re-maps a chip-select to a new physical base address specified by
 746  * "base". Returns 0 on success and appropriate negative error code
 747  * on failure.
 748  */
 749 static int gpmc_cs_remap(int cs, u32 base)
 750 {
 751         int ret;
 752         u32 old_base, size;
 753
 754         if (cs > gpmc_cs_num) {
 755                 pr_err("%s: requested chip-select is disabled\n", __func__);
 756                 return -ENODEV;
 757         }
 758
 759         /*
 760          * Make sure we ignore any device offsets from the GPMC partition
 761          * allocated for the chip select and that the new base confirms
 762          * to the GPMC 16MB minimum granularity.
 763          */
 764         base &= ~(SZ_16M - 1);
 765
 766         gpmc_cs_get_memconf(cs, &old_base, &size);
 767         if (base == old_base)
 768                 return 0;
 769
 770         ret = gpmc_cs_delete_mem(cs);
 771         if (ret < 0)
 772                 return ret;
 773
 774         ret = gpmc_cs_insert_mem(cs, base, size);
 775         if (ret < 0)
 776                 return ret;
 777
 778         ret = gpmc_cs_set_memconf(cs, base, size);
 779
 780         return ret;
 781 }
 782
 783 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 784 {
 785         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 786         struct resource *res = &gpmc->mem;
 787         int r = -1;
 788
 789         if (cs > gpmc_cs_num) {
 790                 pr_err("%s: requested chip-select is disabled\n", __func__);
 791                 return -ENODEV;
 792         }
 793         size = gpmc_mem_align(size);
 794         if (size > (1 << GPMC_SECTION_SHIFT))
 795                 return -ENOMEM;
 796
 797         spin_lock(&gpmc_mem_lock);
 798         if (gpmc_cs_reserved(cs)) {
 799                 r = -EBUSY;
 800                 goto out;
 801         }
 802         if (gpmc_cs_mem_enabled(cs))
 803                 r = adjust_resource(res, res->start & ~(size - 1), size);
 804         if (r < 0)
 805                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 806                                       size, NULL, NULL);
 807         if (r < 0)
 808                 goto out;
 809
 810         /* Disable CS while changing base address and size mask */
 811         gpmc_cs_disable_mem(cs);
 812
 813         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
 814         if (r < 0) {
 815                 release_resource(res);
 816                 goto out;
 817         }
 818
 819         /* Enable CS */
 820         gpmc_cs_enable_mem(cs);
 821         *base = res->start;
 822         gpmc_cs_set_reserved(cs, 1);
 823 out:
 824         spin_unlock(&gpmc_mem_lock);
 825         return r;
 826 }
 827 EXPORT_SYMBOL(gpmc_cs_request);
 828
 829 void gpmc_cs_free(int cs)
 830 {
 831         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 832         struct resource *res = &gpmc->mem;
 833
 834         spin_lock(&gpmc_mem_lock);
 835         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
 836                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 837                 BUG();
 838                 spin_unlock(&gpmc_mem_lock);
 839                 return;
 840         }
 841         gpmc_cs_disable_mem(cs);
 842         if (res->flags)
 843                 release_resource(res);
 844         gpmc_cs_set_reserved(cs, 0);
 845         spin_unlock(&gpmc_mem_lock);
 846 }
 847 EXPORT_SYMBOL(gpmc_cs_free);
 848
 849 /**
 850  * gpmc_configure - write request to configure gpmc
 851  * @cmd: command type
 852  * @wval: value to write
 853  * @return status of the operation
 854  */
 855 int gpmc_configure(int cmd, int wval)
 856 {
 857         u32 regval;
 858
 859         switch (cmd) {
 860         case GPMC_ENABLE_IRQ:
 861                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 862                 break;
 863
 864         case GPMC_SET_IRQ_STATUS:
 865                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 866                 break;
 867
 868         case GPMC_CONFIG_WP:
 869                 regval = gpmc_read_reg(GPMC_CONFIG);
 870                 if (wval)
 871                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 872                 else
 873                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 874                 gpmc_write_reg(GPMC_CONFIG, regval);
 875                 break;
 876
 877         default:
 878                 pr_err("%s: command not supported\n", __func__);
 879                 return -EINVAL;
 880         }
 881
 882         return 0;
 883 }
 884 EXPORT_SYMBOL(gpmc_configure);
 885
 886 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 887 {
 888         int i;
 889
 890         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 891         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 892                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 893         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 894                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 895         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 896                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 897         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 898         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 899         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 900         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 901         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 902         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 903         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 904         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 905
 906         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
 907                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
 908                                            GPMC_BCH_SIZE * i;
 909                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
 910                                            GPMC_BCH_SIZE * i;
 911                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
 912                                            GPMC_BCH_SIZE * i;
 913                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
 914                                            GPMC_BCH_SIZE * i;
 915                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
 916                                            i * GPMC_BCH_SIZE;
 917                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
 918                                            i * GPMC_BCH_SIZE;
 919                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
 920                                            i * GPMC_BCH_SIZE;
 921         }
 922 }
 923
 924 int gpmc_get_client_irq(unsigned irq_config)
 925 {
 926         int i;
 927
 928         if (hweight32(irq_config) > 1)
 929                 return 0;
 930
 931         for (i = 0; i < GPMC_NR_IRQ; i++)
 932                 if (gpmc_client_irq[i].bitmask & irq_config)
 933                         return gpmc_client_irq[i].irq;
 934
 935         return 0;
 936 }
 937
 938 static int gpmc_irq_endis(unsigned irq, bool endis)
 939 {
 940         int i;
 941         u32 regval;
 942
 943         for (i = 0; i < GPMC_NR_IRQ; i++)
 944                 if (irq == gpmc_client_irq[i].irq) {
 945                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 946                         if (endis)
 947                                 regval |= gpmc_client_irq[i].bitmask;
 948                         else
 949                                 regval &= ~gpmc_client_irq[i].bitmask;
 950                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 951                         break;
 952                 }
 953
 954         return 0;
 955 }
 956
 957 static void gpmc_irq_disable(struct irq_data *p)
 958 {
 959         gpmc_irq_endis(p->irq, false);
 960 }
 961
 962 static void gpmc_irq_enable(struct irq_data *p)
 963 {
 964         gpmc_irq_endis(p->irq, true);
 965 }
 966
 967 static void gpmc_irq_noop(struct irq_data *data) { }
 968
 969 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 970
 971 static int gpmc_setup_irq(void)
 972 {
 973         int i;
 974         u32 regval;
 975
 976         if (!gpmc_irq)
 977                 return -EINVAL;
 978
 979         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 980         if (gpmc_irq_start < 0) {
 981                 pr_err("irq_alloc_descs failed\n");
 982                 return gpmc_irq_start;
 983         }
 984
 985         gpmc_irq_chip.name = "gpmc";
 986         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 987         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 988         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 989         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 990         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 991         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 992         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 993
 994         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 995         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 996
 997         for (i = 0; i < GPMC_NR_IRQ; i++) {
 998                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 999                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1000                                         &gpmc_irq_chip, handle_simple_irq);
1001                 set_irq_flags(gpmc_client_irq[i].irq,
1002                                 IRQF_VALID | IRQF_NOAUTOEN);
1003         }
1004
1005         /* Disable interrupts */
1006         gpmc_write_reg(GPMC_IRQENABLE, 0);
1007
1008         /* clear interrupts */
1009         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1010         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1011
1012         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1013 }
1014
1015 static int gpmc_free_irq(void)
1016 {
1017         int i;
1018
1019         if (gpmc_irq)
1020                 free_irq(gpmc_irq, NULL);
1021
1022         for (i = 0; i < GPMC_NR_IRQ; i++) {
1023                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1024                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1025                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
1026         }
1027
1028         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1029
1030         return 0;
1031 }
1032
1033 static void gpmc_mem_exit(void)
1034 {
1035         int cs;
1036
1037         for (cs = 0; cs < gpmc_cs_num; cs++) {
1038                 if (!gpmc_cs_mem_enabled(cs))
1039                         continue;
1040                 gpmc_cs_delete_mem(cs);
1041         }
1042
1043 }
1044
1045 static void gpmc_mem_init(void)
1046 {
1047         int cs;
1048
1049         /*
1050          * The first 1MB of GPMC address space is typically mapped to
1051          * the internal ROM. Never allocate the first page, to
1052          * facilitate bug detection; even if we didn't boot from ROM.
1053          */
1054         gpmc_mem_root.start = SZ_1M;
1055         gpmc_mem_root.end = GPMC_MEM_END;
1056
1057         /* Reserve all regions that has been set up by bootloader */
1058         for (cs = 0; cs < gpmc_cs_num; cs++) {
1059                 u32 base, size;
1060
1061                 if (!gpmc_cs_mem_enabled(cs))
1062                         continue;
1063                 gpmc_cs_get_memconf(cs, &base, &size);
1064                 if (gpmc_cs_insert_mem(cs, base, size)) {
1065                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1066                                 __func__, cs, base, base + size);
1067                         gpmc_cs_disable_mem(cs);
1068                 }
1069         }
1070 }
1071
1072 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1073 {
1074         u32 temp;
1075         int div;
1076
1077         div = gpmc_calc_divider(sync_clk);
1078         temp = gpmc_ps_to_ticks(time_ps);
1079         temp = (temp + div - 1) / div;
1080         return gpmc_ticks_to_ps(temp * div);
1081 }
1082
1083 /* XXX: can the cycles be avoided ? */
1084 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1085                                        struct gpmc_device_timings *dev_t,
1086                                        bool mux)
1087 {
1088         u32 temp;
1089
1090         /* adv_rd_off */
1091         temp = dev_t->t_avdp_r;
1092         /* XXX: mux check required ? */
1093         if (mux) {
1094                 /* XXX: t_avdp not to be required for sync, only added for tusb
1095                  * this indirectly necessitates requirement of t_avdp_r and
1096                  * t_avdp_w instead of having a single t_avdp
1097                  */
1098                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1099                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1100         }
1101         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1102
1103         /* oe_on */
1104         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1105         if (mux) {
1106                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1107                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1108                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1109         }
1110         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1111
1112         /* access */
1113         /* XXX: any scope for improvement ?, by combining oe_on
1114          * and clk_activation, need to check whether
1115          * access = clk_activation + round to sync clk ?
1116          */
1117         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1118         temp += gpmc_t->clk_activation;
1119         if (dev_t->cyc_oe)
1120                 temp = max_t(u32, temp, gpmc_t->oe_on +
1121                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1122         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1123
1124         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1125         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1126
1127         /* rd_cycle */
1128         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1129         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1130                                                         gpmc_t->access;
1131         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1132         if (dev_t->t_ce_rdyz)
1133                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1134         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1135
1136         return 0;
1137 }
1138
1139 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1140                                         struct gpmc_device_timings *dev_t,
1141                                         bool mux)
1142 {
1143         u32 temp;
1144
1145         /* adv_wr_off */
1146         temp = dev_t->t_avdp_w;
1147         if (mux) {
1148                 temp = max_t(u32, temp,
1149                         gpmc_t->clk_activation + dev_t->t_avdh);
1150                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1151         }
1152         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1153
1154         /* wr_data_mux_bus */
1155         temp = max_t(u32, dev_t->t_weasu,
1156                         gpmc_t->clk_activation + dev_t->t_rdyo);
1157         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1158          * and in that case remember to handle we_on properly
1159          */
1160         if (mux) {
1161                 temp = max_t(u32, temp,
1162                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1163                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1164                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1165         }
1166         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1167
1168         /* we_on */
1169         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1170                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1171         else
1172                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1173
1174         /* wr_access */
1175         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1176         gpmc_t->wr_access = gpmc_t->access;
1177
1178         /* we_off */
1179         temp = gpmc_t->we_on + dev_t->t_wpl;
1180         temp = max_t(u32, temp,
1181                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1182         temp = max_t(u32, temp,
1183                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1184         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1185
1186         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1187                                                         dev_t->t_wph);
1188
1189         /* wr_cycle */
1190         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1191         temp += gpmc_t->wr_access;
1192         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1193         if (dev_t->t_ce_rdyz)
1194                 temp = max_t(u32, temp,
1195                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1196         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1197
1198         return 0;
1199 }
1200
1201 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1202                                         struct gpmc_device_timings *dev_t,
1203                                         bool mux)
1204 {
1205         u32 temp;
1206
1207         /* adv_rd_off */
1208         temp = dev_t->t_avdp_r;
1209         if (mux)
1210                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1211         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1212
1213         /* oe_on */
1214         temp = dev_t->t_oeasu;
1215         if (mux)
1216                 temp = max_t(u32, temp,
1217                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1218         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1219
1220         /* access */
1221         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1222                                 gpmc_t->oe_on + dev_t->t_oe);
1223         temp = max_t(u32, temp,
1224                                 gpmc_t->cs_on + dev_t->t_ce);
1225         temp = max_t(u32, temp,
1226                                 gpmc_t->adv_on + dev_t->t_aa);
1227         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1228
1229         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1230         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1231
1232         /* rd_cycle */
1233         temp = max_t(u32, dev_t->t_rd_cycle,
1234                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1235         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1236         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1237
1238         return 0;
1239 }
1240
1241 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1242                                          struct gpmc_device_timings *dev_t,
1243                                          bool mux)
1244 {
1245         u32 temp;
1246
1247         /* adv_wr_off */
1248         temp = dev_t->t_avdp_w;
1249         if (mux)
1250                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1251         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1252
1253         /* wr_data_mux_bus */
1254         temp = dev_t->t_weasu;
1255         if (mux) {
1256                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1257                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1258                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1259         }
1260         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1261
1262         /* we_on */
1263         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1264                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1265         else
1266                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1267
1268         /* we_off */
1269         temp = gpmc_t->we_on + dev_t->t_wpl;
1270         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1271
1272         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1273                                                         dev_t->t_wph);
1274
1275         /* wr_cycle */
1276         temp = max_t(u32, dev_t->t_wr_cycle,
1277                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1278         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1279
1280         return 0;
1281 }
1282
1283 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1284                         struct gpmc_device_timings *dev_t)
1285 {
1286         u32 temp;
1287
1288         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1289                                                 gpmc_get_fclk_period();
1290
1291         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1292                                         dev_t->t_bacc,
1293                                         gpmc_t->sync_clk);
1294
1295         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1296         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1297
1298         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1299                 return 0;
1300
1301         if (dev_t->ce_xdelay)
1302                 gpmc_t->bool_timings.cs_extra_delay = true;
1303         if (dev_t->avd_xdelay)
1304                 gpmc_t->bool_timings.adv_extra_delay = true;
1305         if (dev_t->oe_xdelay)
1306                 gpmc_t->bool_timings.oe_extra_delay = true;
1307         if (dev_t->we_xdelay)
1308                 gpmc_t->bool_timings.we_extra_delay = true;
1309
1310         return 0;
1311 }
1312
1313 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1314                                     struct gpmc_device_timings *dev_t,
1315                                     bool sync)
1316 {
1317         u32 temp;
1318
1319         /* cs_on */
1320         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1321
1322         /* adv_on */
1323         temp = dev_t->t_avdasu;
1324         if (dev_t->t_ce_avd)
1325                 temp = max_t(u32, temp,
1326                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1327         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1328
1329         if (sync)
1330                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1331
1332         return 0;
1333 }
1334
1335 /* TODO: remove this function once all peripherals are confirmed to
1336  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1337  * has to be modified to handle timings in ps instead of ns
1338 */
1339 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1340 {
1341         t->cs_on /= 1000;
1342         t->cs_rd_off /= 1000;
1343         t->cs_wr_off /= 1000;
1344         t->adv_on /= 1000;
1345         t->adv_rd_off /= 1000;
1346         t->adv_wr_off /= 1000;
1347         t->we_on /= 1000;
1348         t->we_off /= 1000;
1349         t->oe_on /= 1000;
1350         t->oe_off /= 1000;
1351         t->page_burst_access /= 1000;
1352         t->access /= 1000;
1353         t->rd_cycle /= 1000;
1354         t->wr_cycle /= 1000;
1355         t->bus_turnaround /= 1000;
1356         t->cycle2cycle_delay /= 1000;
1357         t->wait_monitoring /= 1000;
1358         t->clk_activation /= 1000;
1359         t->wr_access /= 1000;
1360         t->wr_data_mux_bus /= 1000;
1361 }
1362
1363 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1364                       struct gpmc_settings *gpmc_s,
1365                       struct gpmc_device_timings *dev_t)
1366 {
1367         bool mux = false, sync = false;
1368
1369         if (gpmc_s) {
1370                 mux = gpmc_s->mux_add_data ? true : false;
1371                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1372         }
1373
1374         memset(gpmc_t, 0, sizeof(*gpmc_t));
1375
1376         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1377
1378         if (gpmc_s && gpmc_s->sync_read)
1379                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1380         else
1381                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1382
1383         if (gpmc_s && gpmc_s->sync_write)
1384                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1385         else
1386                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1387
1388         /* TODO: remove, see function definition */
1389         gpmc_convert_ps_to_ns(gpmc_t);
1390
1391         return 0;
1392 }
1393
1394 /**
1395  * gpmc_cs_program_settings - programs non-timing related settings
1396  * @cs:         GPMC chip-select to program
1397  * @p:          pointer to GPMC settings structure
1398  *
1399  * Programs non-timing related settings for a GPMC chip-select, such as
1400  * bus-width, burst configuration, etc. Function should be called once
1401  * for each chip-select that is being used and must be called before
1402  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1403  * register will be initialised to zero by this function. Returns 0 on
1404  * success and appropriate negative error code on failure.
1405  */
1406 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1407 {
1408         u32 config1;
1409
1410         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1411                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1412                 return -EINVAL;
1413         }
1414
1415         /* Address-data multiplexing not supported for NAND devices */
1416         if (p->device_nand && p->mux_add_data) {
1417                 pr_err("%s: invalid configuration!\n", __func__);
1418                 return -EINVAL;
1419         }
1420
1421         if ((p->mux_add_data > GPMC_MUX_AD) ||
1422             ((p->mux_add_data == GPMC_MUX_AAD) &&
1423              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1424                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1425                 return -EINVAL;
1426         }
1427
1428         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1429         if (p->burst_read || p->burst_write) {
1430                 switch (p->burst_len) {
1431                 case GPMC_BURST_4:
1432                 case GPMC_BURST_8:
1433                 case GPMC_BURST_16:
1434                         break;
1435                 default:
1436                         pr_err("%s: invalid page/burst-length (%d)\n",
1437                                __func__, p->burst_len);
1438                         return -EINVAL;
1439                 }
1440         }
1441
1442         if (p->wait_pin > gpmc_nr_waitpins) {
1443                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1444                 return -EINVAL;
1445         }
1446
1447         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1448
1449         if (p->sync_read)
1450                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1451         if (p->sync_write)
1452                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1453         if (p->wait_on_read)
1454                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1455         if (p->wait_on_write)
1456                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1457         if (p->wait_on_read || p->wait_on_write)
1458                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1459         if (p->device_nand)
1460                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1461         if (p->mux_add_data)
1462                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1463         if (p->burst_read)
1464                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1465         if (p->burst_write)
1466                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1467         if (p->burst_read || p->burst_write) {
1468                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1469                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1470         }
1471
1472         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1473
1474         return 0;
1475 }
1476
1477 #ifdef CONFIG_OF
1478 static const struct of_device_id gpmc_dt_ids[] = {
1479         { .compatible = "ti,omap2420-gpmc" },
1480         { .compatible = "ti,omap2430-gpmc" },
1481         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1482         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1483         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1484         { }
1485 };
1486 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1487
1488 /**
1489  * gpmc_read_settings_dt - read gpmc settings from device-tree
1490  * @np:         pointer to device-tree node for a gpmc child device
1491  * @p:          pointer to gpmc settings structure
1492  *
1493  * Reads the GPMC settings for a GPMC child device from device-tree and
1494  * stores them in the GPMC settings structure passed. The GPMC settings
1495  * structure is initialised to zero by this function and so any
1496  * previously stored settings will be cleared.
1497  */
1498 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1499 {
1500         memset(p, 0, sizeof(struct gpmc_settings));
1501
1502         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1503         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1504         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1505         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1506
1507         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1508                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1509                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1510                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1511                 if (!p->burst_read && !p->burst_write)
1512                         pr_warn("%s: page/burst-length set but not used!\n",
1513                                 __func__);
1514         }
1515
1516         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1517                 p->wait_on_read = of_property_read_bool(np,
1518                                                         "gpmc,wait-on-read");
1519                 p->wait_on_write = of_property_read_bool(np,
1520                                                          "gpmc,wait-on-write");
1521                 if (!p->wait_on_read && !p->wait_on_write)
1522                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1523                                  __func__);
1524         }
1525 }
1526
1527 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1528                                                 struct gpmc_timings *gpmc_t)
1529 {
1530         struct gpmc_bool_timings *p;
1531
1532         if (!np || !gpmc_t)
1533                 return;
1534
1535         memset(gpmc_t, 0, sizeof(*gpmc_t));
1536
1537         /* minimum clock period for syncronous mode */
1538         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1539
1540         /* chip select timtings */
1541         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1542         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1543         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1544
1545         /* ADV signal timings */
1546         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1547         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1548         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1549
1550         /* WE signal timings */
1551         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1552         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1553
1554         /* OE signal timings */
1555         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1556         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1557
1558         /* access and cycle timings */
1559         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1560                              &gpmc_t->page_burst_access);
1561         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1562         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1563         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1564         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1565                              &gpmc_t->bus_turnaround);
1566         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1567                              &gpmc_t->cycle2cycle_delay);
1568         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1569                              &gpmc_t->wait_monitoring);
1570         of_property_read_u32(np, "gpmc,clk-activation-ns",
1571                              &gpmc_t->clk_activation);
1572
1573         /* only applicable to OMAP3+ */
1574         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1575         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1576                              &gpmc_t->wr_data_mux_bus);
1577
1578         /* bool timing parameters */
1579         p = &gpmc_t->bool_timings;
1580
1581         p->cycle2cyclediffcsen =
1582                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1583         p->cycle2cyclesamecsen =
1584                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1585         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1586         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1587         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1588         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1589         p->time_para_granularity =
1590                 of_property_read_bool(np, "gpmc,time-para-granularity");
1591 }
1592
1593 #if IS_ENABLED(CONFIG_MTD_NAND)
1594
1595 static const char * const nand_xfer_types[] = {
1596         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1597         [NAND_OMAP_POLLED]                      = "polled",
1598         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1599         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1600 };
1601
1602 static int gpmc_probe_nand_child(struct platform_device *pdev,
1603                                  struct device_node *child)
1604 {
1605         u32 val;
1606         const char *s;
1607         struct gpmc_timings gpmc_t;
1608         struct omap_nand_platform_data *gpmc_nand_data;
1609
1610         if (of_property_read_u32(child, "reg", &val) < 0) {
1611                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1612                         child->full_name);
1613                 return -ENODEV;
1614         }
1615
1616         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1617                                       GFP_KERNEL);
1618         if (!gpmc_nand_data)
1619                 return -ENOMEM;
1620
1621         gpmc_nand_data->cs = val;
1622         gpmc_nand_data->of_node = child;
1623
1624         /* Detect availability of ELM module */
1625         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1626         if (gpmc_nand_data->elm_of_node == NULL)
1627                 gpmc_nand_data->elm_of_node =
1628                                         of_parse_phandle(child, "elm_id", 0);
1629
1630         /* select ecc-scheme for NAND */
1631         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1632                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1633                 return -ENODEV;
1634         }
1635
1636         if (!strcmp(s, "sw"))
1637                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1638         else if (!strcmp(s, "ham1") ||
1639                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1640                 gpmc_nand_data->ecc_opt =
1641                                 OMAP_ECC_HAM1_CODE_HW;
1642         else if (!strcmp(s, "bch4"))
1643                 if (gpmc_nand_data->elm_of_node)
1644                         gpmc_nand_data->ecc_opt =
1645                                 OMAP_ECC_BCH4_CODE_HW;
1646                 else
1647                         gpmc_nand_data->ecc_opt =
1648                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1649         else if (!strcmp(s, "bch8"))
1650                 if (gpmc_nand_data->elm_of_node)
1651                         gpmc_nand_data->ecc_opt =
1652                                 OMAP_ECC_BCH8_CODE_HW;
1653                 else
1654                         gpmc_nand_data->ecc_opt =
1655                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1656         else if (!strcmp(s, "bch16"))
1657                 if (gpmc_nand_data->elm_of_node)
1658                         gpmc_nand_data->ecc_opt =
1659                                 OMAP_ECC_BCH16_CODE_HW;
1660                 else
1661                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1662         else
1663                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1664
1665         /* select data transfer mode for NAND controller */
1666         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1667                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1668                         if (!strcasecmp(s, nand_xfer_types[val])) {
1669                                 gpmc_nand_data->xfer_type = val;
1670                                 break;
1671                         }
1672
1673         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1674
1675         val = of_get_nand_bus_width(child);
1676         if (val == 16)
1677                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1678
1679         gpmc_read_timings_dt(child, &gpmc_t);
1680         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1681
1682         return 0;
1683 }
1684 #else
1685 static int gpmc_probe_nand_child(struct platform_device *pdev,
1686                                  struct device_node *child)
1687 {
1688         return 0;
1689 }
1690 #endif
1691
1692 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1693 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1694                                  struct device_node *child)
1695 {
1696         u32 val;
1697         struct omap_onenand_platform_data *gpmc_onenand_data;
1698
1699         if (of_property_read_u32(child, "reg", &val) < 0) {
1700                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1701                         child->full_name);
1702                 return -ENODEV;
1703         }
1704
1705         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1706                                          GFP_KERNEL);
1707         if (!gpmc_onenand_data)
1708                 return -ENOMEM;
1709
1710         gpmc_onenand_data->cs = val;
1711         gpmc_onenand_data->of_node = child;
1712         gpmc_onenand_data->dma_channel = -1;
1713
1714         if (!of_property_read_u32(child, "dma-channel", &val))
1715                 gpmc_onenand_data->dma_channel = val;
1716
1717         gpmc_onenand_init(gpmc_onenand_data);
1718
1719         return 0;
1720 }
1721 #else
1722 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1723                                     struct device_node *child)
1724 {
1725         return 0;
1726 }
1727 #endif
1728
1729 /**
1730  * gpmc_probe_generic_child - configures the gpmc for a child device
1731  * @pdev:       pointer to gpmc platform device
1732  * @child:      pointer to device-tree node for child device
1733  *
1734  * Allocates and configures a GPMC chip-select for a child device.
1735  * Returns 0 on success and appropriate negative error code on failure.
1736  */
1737 static int gpmc_probe_generic_child(struct platform_device *pdev,
1738                                 struct device_node *child)
1739 {
1740         struct gpmc_settings gpmc_s;
1741         struct gpmc_timings gpmc_t;
1742         struct resource res;
1743         unsigned long base;
1744         const char *name;
1745         int ret, cs;
1746         u32 val;
1747
1748         if (of_property_read_u32(child, "reg", &cs) < 0) {
1749                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1750                         child->full_name);
1751                 return -ENODEV;
1752         }
1753
1754         if (of_address_to_resource(child, 0, &res) < 0) {
1755                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1756                         child->full_name);
1757                 return -ENODEV;
1758         }
1759
1760         /*
1761          * Check if we have multiple instances of the same device
1762          * on a single chip select. If so, use the already initialized
1763          * timings.
1764          */
1765         name = gpmc_cs_get_name(cs);
1766         if (name && child->name && of_node_cmp(child->name, name) == 0)
1767                         goto no_timings;
1768
1769         ret = gpmc_cs_request(cs, resource_size(&res), &base);
1770         if (ret < 0) {
1771                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1772                 return ret;
1773         }
1774         gpmc_cs_set_name(cs, child->name);
1775
1776         gpmc_read_settings_dt(child, &gpmc_s);
1777         gpmc_read_timings_dt(child, &gpmc_t);
1778
1779         /*
1780          * For some GPMC devices we still need to rely on the bootloader
1781          * timings because the devices can be connected via FPGA.
1782          * REVISIT: Add timing support from slls644g.pdf.
1783          */
1784         if (!gpmc_t.cs_rd_off) {
1785                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1786                         cs);
1787                 gpmc_cs_show_timings(cs,
1788                                      "please add GPMC bootloader timings to .dts");
1789                 goto no_timings;
1790         }
1791
1792         /* CS must be disabled while making changes to gpmc configuration */
1793         gpmc_cs_disable_mem(cs);
1794
1795         /*
1796          * FIXME: gpmc_cs_request() will map the CS to an arbitary
1797          * location in the gpmc address space. When booting with
1798          * device-tree we want the NOR flash to be mapped to the
1799          * location specified in the device-tree blob. So remap the
1800          * CS to this location. Once DT migration is complete should
1801          * just make gpmc_cs_request() map a specific address.
1802          */
1803         ret = gpmc_cs_remap(cs, res.start);
1804         if (ret < 0) {
1805                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1806                         cs, &res.start);
1807                 goto err;
1808         }
1809
1810         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1811         if (ret < 0)
1812                 goto err;
1813
1814         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1815         if (ret < 0)
1816                 goto err;
1817
1818         ret = gpmc_cs_set_timings(cs, &gpmc_t);
1819         if (ret) {
1820                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1821                         child->name);
1822                 goto err;
1823         }
1824
1825         /* Clear limited address i.e. enable A26-A11 */
1826         val = gpmc_read_reg(GPMC_CONFIG);
1827         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1828         gpmc_write_reg(GPMC_CONFIG, val);
1829
1830         /* Enable CS region */
1831         gpmc_cs_enable_mem(cs);
1832
1833 no_timings:
1834
1835         /* create platform device, NULL on error or when disabled */
1836         if (!of_platform_device_create(child, NULL, &pdev->dev))
1837                 goto err_child_fail;
1838
1839         /* is child a common bus? */
1840         if (of_match_node(of_default_bus_match_table, child))
1841                 /* create children and other common bus children */
1842                 if (of_platform_populate(child, of_default_bus_match_table,
1843                                          NULL, &pdev->dev))
1844                         goto err_child_fail;
1845
1846         return 0;
1847
1848 err_child_fail:
1849
1850         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1851         ret = -ENODEV;
1852
1853 err:
1854         gpmc_cs_free(cs);
1855
1856         return ret;
1857 }
1858
1859 static int gpmc_probe_dt(struct platform_device *pdev)
1860 {
1861         int ret;
1862         struct device_node *child;
1863         const struct of_device_id *of_id =
1864                 of_match_device(gpmc_dt_ids, &pdev->dev);
1865
1866         if (!of_id)
1867                 return 0;
1868
1869         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1870                                    &gpmc_cs_num);
1871         if (ret < 0) {
1872                 pr_err("%s: number of chip-selects not defined\n", __func__);
1873                 return ret;
1874         } else if (gpmc_cs_num < 1) {
1875                 pr_err("%s: all chip-selects are disabled\n", __func__);
1876                 return -EINVAL;
1877         } else if (gpmc_cs_num > GPMC_CS_NUM) {
1878                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1879                                          __func__, GPMC_CS_NUM);
1880                 return -EINVAL;
1881         }
1882
1883         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1884                                    &gpmc_nr_waitpins);
1885         if (ret < 0) {
1886                 pr_err("%s: number of wait pins not found!\n", __func__);
1887                 return ret;
1888         }
1889
1890         for_each_available_child_of_node(pdev->dev.of_node, child) {
1891
1892                 if (!child->name)
1893                         continue;
1894
1895                 if (of_node_cmp(child->name, "nand") == 0)
1896                         ret = gpmc_probe_nand_child(pdev, child);
1897                 else if (of_node_cmp(child->name, "onenand") == 0)
1898                         ret = gpmc_probe_onenand_child(pdev, child);
1899                 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1900                          of_node_cmp(child->name, "nor") == 0 ||
1901                          of_node_cmp(child->name, "uart") == 0)
1902                         ret = gpmc_probe_generic_child(pdev, child);
1903
1904                 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1905                          __func__, child->full_name))
1906                         of_node_put(child);
1907         }
1908
1909         return 0;
1910 }
1911 #else
1912 static int gpmc_probe_dt(struct platform_device *pdev)
1913 {
1914         return 0;
1915 }
1916 #endif
1917
1918 static int gpmc_probe(struct platform_device *pdev)
1919 {
1920         int rc;
1921         u32 l;
1922         struct resource *res;
1923
1924         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1925         if (res == NULL)
1926                 return -ENOENT;
1927
1928         phys_base = res->start;
1929         mem_size = resource_size(res);
1930
1931         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1932         if (IS_ERR(gpmc_base))
1933                 return PTR_ERR(gpmc_base);
1934
1935         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1936         if (res == NULL)
1937                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1938         else
1939                 gpmc_irq = res->start;
1940
1941         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
1942         if (IS_ERR(gpmc_l3_clk)) {
1943                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
1944                 gpmc_irq = 0;
1945                 return PTR_ERR(gpmc_l3_clk);
1946         }
1947
1948         if (!clk_get_rate(gpmc_l3_clk)) {
1949                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
1950                 return -EINVAL;
1951         }
1952
1953         pm_runtime_enable(&pdev->dev);
1954         pm_runtime_get_sync(&pdev->dev);
1955
1956         gpmc_dev = &pdev->dev;
1957
1958         l = gpmc_read_reg(GPMC_REVISION);
1959
1960         /*
1961          * FIXME: Once device-tree migration is complete the below flags
1962          * should be populated based upon the device-tree compatible
1963          * string. For now just use the IP revision. OMAP3+ devices have
1964          * the wr_access and wr_data_mux_bus register fields. OMAP4+
1965          * devices support the addr-addr-data multiplex protocol.
1966          *
1967          * GPMC IP revisions:
1968          * - OMAP24xx                   = 2.0
1969          * - OMAP3xxx                   = 5.0
1970          * - OMAP44xx/54xx/AM335x       = 6.0
1971          */
1972         if (GPMC_REVISION_MAJOR(l) > 0x4)
1973                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1974         if (GPMC_REVISION_MAJOR(l) > 0x5)
1975                 gpmc_capability |= GPMC_HAS_MUX_AAD;
1976         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1977                  GPMC_REVISION_MINOR(l));
1978
1979         gpmc_mem_init();
1980
1981         if (gpmc_setup_irq() < 0)
1982                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1983
1984         if (!pdev->dev.of_node) {
1985                 gpmc_cs_num      = GPMC_CS_NUM;
1986                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1987         }
1988
1989         rc = gpmc_probe_dt(pdev);
1990         if (rc < 0) {
1991                 pm_runtime_put_sync(&pdev->dev);
1992                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1993                 return rc;
1994         }
1995
1996         return 0;
1997 }
1998
1999 static int gpmc_remove(struct platform_device *pdev)
2000 {
2001         gpmc_free_irq();
2002         gpmc_mem_exit();
2003         pm_runtime_put_sync(&pdev->dev);
2004         pm_runtime_disable(&pdev->dev);
2005         gpmc_dev = NULL;
2006         return 0;
2007 }
2008
2009 #ifdef CONFIG_PM_SLEEP
2010 static int gpmc_suspend(struct device *dev)
2011 {
2012         omap3_gpmc_save_context();
2013         pm_runtime_put_sync(dev);
2014         return 0;
2015 }
2016
2017 static int gpmc_resume(struct device *dev)
2018 {
2019         pm_runtime_get_sync(dev);
2020         omap3_gpmc_restore_context();
2021         return 0;
2022 }
2023 #endif
2024
2025 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2026
2027 static struct platform_driver gpmc_driver = {
2028         .probe          = gpmc_probe,
2029         .remove         = gpmc_remove,
2030         .driver         = {
2031                 .name   = DEVICE_NAME,
2032                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2033                 .pm     = &gpmc_pm_ops,
2034         },
2035 };
2036
2037 static __init int gpmc_init(void)
2038 {
2039         return platform_driver_register(&gpmc_driver);
2040 }
2041
2042 static __exit void gpmc_exit(void)
2043 {
2044         platform_driver_unregister(&gpmc_driver);
2045
2046 }
2047
2048 postcore_initcall(gpmc_init);
2049 module_exit(gpmc_exit);
2050
2051 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2052 {
2053         int i;
2054         u32 regval;
2055
2056         regval = gpmc_read_reg(GPMC_IRQSTATUS);
2057
2058         if (!regval)
2059                 return IRQ_NONE;
2060
2061         for (i = 0; i < GPMC_NR_IRQ; i++)
2062                 if (regval & gpmc_client_irq[i].bitmask)
2063                         generic_handle_irq(gpmc_client_irq[i].irq);
2064
2065         gpmc_write_reg(GPMC_IRQSTATUS, regval);
2066
2067         return IRQ_HANDLED;
2068 }
2069
2070 static struct omap3_gpmc_regs gpmc_context;
2071
2072 void omap3_gpmc_save_context(void)
2073 {
2074         int i;
2075
2076         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2077         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2078         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2079         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2080         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2081         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2082         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2083         for (i = 0; i < gpmc_cs_num; i++) {
2084                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2085                 if (gpmc_context.cs_context[i].is_valid) {
2086                         gpmc_context.cs_context[i].config1 =
2087                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2088                         gpmc_context.cs_context[i].config2 =
2089                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2090                         gpmc_context.cs_context[i].config3 =
2091                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2092                         gpmc_context.cs_context[i].config4 =
2093                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2094                         gpmc_context.cs_context[i].config5 =
2095                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2096                         gpmc_context.cs_context[i].config6 =
2097                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2098                         gpmc_context.cs_context[i].config7 =
2099                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2100                 }
2101         }
2102 }
2103
2104 void omap3_gpmc_restore_context(void)
2105 {
2106         int i;
2107
2108         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2109         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2110         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2111         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2112         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2113         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2114         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2115         for (i = 0; i < gpmc_cs_num; i++) {
2116                 if (gpmc_context.cs_context[i].is_valid) {
2117                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2118                                 gpmc_context.cs_context[i].config1);
2119                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2120                                 gpmc_context.cs_context[i].config2);
2121                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2122                                 gpmc_context.cs_context[i].config3);
2123                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2124                                 gpmc_context.cs_context[i].config4);
2125                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2126                                 gpmc_context.cs_context[i].config5);
2127                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2128                                 gpmc_context.cs_context[i].config6);
2129                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2130                                 gpmc_context.cs_context[i].config7);
2131                 }
2132         }
2133 }