2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_mtd.h>
29 #include <linux/of_device.h>
30 #include <linux/of_platform.h>
31 #include <linux/omap-gpmc.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <linux/platform_data/mtd-onenand-omap2.h>
38 #include <asm/mach-types.h>
40 #define DEVICE_NAME "omap-gpmc"
42 /* GPMC register offsets */
43 #define GPMC_REVISION 0x00
44 #define GPMC_SYSCONFIG 0x10
45 #define GPMC_SYSSTATUS 0x14
46 #define GPMC_IRQSTATUS 0x18
47 #define GPMC_IRQENABLE 0x1c
48 #define GPMC_TIMEOUT_CONTROL 0x40
49 #define GPMC_ERR_ADDRESS 0x44
50 #define GPMC_ERR_TYPE 0x48
51 #define GPMC_CONFIG 0x50
52 #define GPMC_STATUS 0x54
53 #define GPMC_PREFETCH_CONFIG1 0x1e0
54 #define GPMC_PREFETCH_CONFIG2 0x1e4
55 #define GPMC_PREFETCH_CONTROL 0x1ec
56 #define GPMC_PREFETCH_STATUS 0x1f0
57 #define GPMC_ECC_CONFIG 0x1f4
58 #define GPMC_ECC_CONTROL 0x1f8
59 #define GPMC_ECC_SIZE_CONFIG 0x1fc
60 #define GPMC_ECC1_RESULT 0x200
61 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
69 /* GPMC ECC control settings */
70 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
71 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
72 #define GPMC_ECC_CTRL_ECCREG1 0x001
73 #define GPMC_ECC_CTRL_ECCREG2 0x002
74 #define GPMC_ECC_CTRL_ECCREG3 0x003
75 #define GPMC_ECC_CTRL_ECCREG4 0x004
76 #define GPMC_ECC_CTRL_ECCREG5 0x005
77 #define GPMC_ECC_CTRL_ECCREG6 0x006
78 #define GPMC_ECC_CTRL_ECCREG7 0x007
79 #define GPMC_ECC_CTRL_ECCREG8 0x008
80 #define GPMC_ECC_CTRL_ECCREG9 0x009
82 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
95 #define GPMC_MEM_END 0x3FFFFFFF
97 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100 #define CS_NUM_SHIFT 24
101 #define ENABLE_PREFETCH (0x1 << 7)
102 #define DMA_MPU_MODE 2
104 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107 #define GPMC_HAS_WR_ACCESS 0x1
108 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
109 #define GPMC_HAS_MUX_AAD 0x4
111 #define GPMC_NR_WAITPINS 4
113 #define GPMC_CS_CONFIG1 0x00
114 #define GPMC_CS_CONFIG2 0x04
115 #define GPMC_CS_CONFIG3 0x08
116 #define GPMC_CS_CONFIG4 0x0c
117 #define GPMC_CS_CONFIG5 0x10
118 #define GPMC_CS_CONFIG6 0x14
119 #define GPMC_CS_CONFIG7 0x18
120 #define GPMC_CS_NAND_COMMAND 0x1c
121 #define GPMC_CS_NAND_ADDRESS 0x20
122 #define GPMC_CS_NAND_DATA 0x24
124 /* Control Commands */
125 #define GPMC_CONFIG_RDY_BSY 0x00000001
126 #define GPMC_CONFIG_DEV_SIZE 0x00000002
127 #define GPMC_CONFIG_DEV_TYPE 0x00000003
128 #define GPMC_SET_IRQ_STATUS 0x00000004
130 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
131 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
132 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
133 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
135 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
136 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
138 /** CLKACTIVATIONTIME Max Ticks */
139 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
140 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
141 /** ATTACHEDDEVICEPAGELENGTH Max Value */
142 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
143 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
144 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
145 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
146 /** WAITMONITORINGTIME Max Ticks */
147 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
148 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
149 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
150 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
151 /** DEVICESIZE Max Value */
152 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
153 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
154 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
155 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
156 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
157 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
158 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
159 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
160 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
161 #define GPMC_CONFIG7_CSVALID (1 << 6)
163 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
164 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
165 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
166 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
167 /* All CONFIG7 bits except reserved bits */
168 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
169 GPMC_CONFIG7_CSVALID_MASK | \
170 GPMC_CONFIG7_MASKADDRESS_MASK)
172 #define GPMC_DEVICETYPE_NOR 0
173 #define GPMC_DEVICETYPE_NAND 2
174 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
175 #define WR_RD_PIN_MONITORING 0x00600000
177 #define GPMC_ENABLE_IRQ 0x0000000d
180 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
181 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
182 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
184 /* XXX: Only NAND irq has been considered,currently these are the only ones used
186 #define GPMC_NR_IRQ 2
188 enum gpmc_clk_domain {
193 struct gpmc_cs_data {
196 #define GPMC_CS_RESERVED (1 << 0)
202 struct gpmc_client_irq {
207 /* Structure to save gpmc cs context */
208 struct gpmc_cs_config {
220 * Structure to save/restore gpmc context
221 * to support core off on OMAP3
223 struct omap3_gpmc_regs {
228 u32 prefetch_config1;
229 u32 prefetch_config2;
230 u32 prefetch_control;
231 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
234 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
235 static struct irq_chip gpmc_irq_chip;
236 static int gpmc_irq_start;
238 static struct resource gpmc_mem_root;
239 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
240 static DEFINE_SPINLOCK(gpmc_mem_lock);
241 /* Define chip-selects as reserved by default until probe completes */
242 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
243 static unsigned int gpmc_nr_waitpins;
244 static struct device *gpmc_dev;
246 static resource_size_t phys_base, mem_size;
247 static unsigned gpmc_capability;
248 static void __iomem *gpmc_base;
250 static struct clk *gpmc_l3_clk;
252 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
254 static void gpmc_write_reg(int idx, u32 val)
256 writel_relaxed(val, gpmc_base + idx);
259 static u32 gpmc_read_reg(int idx)
261 return readl_relaxed(gpmc_base + idx);
264 void gpmc_cs_write_reg(int cs, int idx, u32 val)
266 void __iomem *reg_addr;
268 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
269 writel_relaxed(val, reg_addr);
272 static u32 gpmc_cs_read_reg(int cs, int idx)
274 void __iomem *reg_addr;
276 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
277 return readl_relaxed(reg_addr);
280 /* TODO: Add support for gpmc_fck to clock framework and use it */
281 static unsigned long gpmc_get_fclk_period(void)
283 unsigned long rate = clk_get_rate(gpmc_l3_clk);
286 rate = 1000000000 / rate; /* In picoseconds */
292 * gpmc_get_clk_period - get period of selected clock domain in ps
293 * @cs Chip Select Region.
296 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
297 * prior to calling this function with GPMC_CD_CLK.
299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
302 unsigned long tick_ps = gpmc_get_fclk_period();
308 /* get current clk divider */
309 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
310 div = (l & 0x03) + 1;
311 /* get GPMC_CLK period */
324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
325 enum gpmc_clk_domain cd)
327 unsigned long tick_ps;
329 /* Calculate in picosecs to yield more exact results */
330 tick_ps = gpmc_get_clk_period(cs, cd);
332 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
342 unsigned long tick_ps;
344 /* Calculate in picosecs to yield more exact results */
345 tick_ps = gpmc_get_fclk_period();
347 return (time_ps + tick_ps - 1) / tick_ps;
350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
351 enum gpmc_clk_domain cd)
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
356 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
363 return ticks * gpmc_get_fclk_period();
366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
368 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
370 return ticks * gpmc_get_fclk_period();
373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
377 l = gpmc_cs_read_reg(cs, reg);
382 gpmc_cs_write_reg(cs, reg, l);
385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
388 GPMC_CONFIG1_TIME_PARA_GRAN,
389 p->time_para_granularity);
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
397 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
400 p->cycle2cyclesamecsen);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
403 p->cycle2cyclediffcsen);
406 #ifdef CONFIG_OMAP_GPMC_DEBUG
408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
409 * @cs: Chip Select Region
410 * @reg: GPMC_CS_CONFIGn register offset.
412 * @end_bit: End Bit. Must be >= @st_bit.
413 * @ma:x Maximum parameter value (before optional @shift).
414 * If 0, maximum is as high as @st_bit and @end_bit allow.
415 * @name: DTS node name, w/o "gpmc,"
416 * @cd: Clock Domain of timing parameter.
417 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
418 * @raw: Raw Format Option.
419 * raw format: gpmc,name = <value>
420 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
421 * Where x ns -- y ns result in the same tick value.
422 * When @max is exceeded, "invalid" is printed inside comment.
423 * @noval: Parameter values equal to 0 are not printed.
424 * @return: Specified timing parameter (after optional @shift).
427 static int get_gpmc_timing_reg(
428 /* timing specifiers */
429 int cs, int reg, int st_bit, int end_bit, int max,
430 const char *name, const enum gpmc_clk_domain cd,
431 /* value transform */
433 /* format specifiers */
434 bool raw, bool noval)
441 l = gpmc_cs_read_reg(cs, reg);
442 nr_bits = end_bit - st_bit + 1;
443 mask = (1 << nr_bits) - 1;
444 l = (l >> st_bit) & mask;
450 if (noval && (l == 0))
453 /* DTS tick format for timings in ns */
454 unsigned int time_ns;
455 unsigned int time_ns_min = 0;
458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
460 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
461 name, time_ns, time_ns_min, time_ns, l,
462 invalid ? "; invalid " : " ");
465 pr_info("gpmc,%s = <%u>%s\n", name, l,
466 invalid ? " /* invalid */" : "");
472 #define GPMC_PRINT_CONFIG(cs, config) \
473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
474 gpmc_cs_read_reg(cs, config))
475 #define GPMC_GET_RAW(reg, st, end, field) \
476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
483 #define GPMC_GET_TICKS(reg, st, end, field) \
484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
490 static void gpmc_show_regs(int cs, const char *desc)
492 pr_info("gpmc cs%i %s:\n", cs, desc);
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
503 * see commit c9fb809.
505 static void gpmc_cs_show_timings(int cs, const char *desc)
507 gpmc_show_regs(cs, desc);
509 pr_info("gpmc cs%i access configuration:\n", cs);
510 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
512 GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
513 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
517 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
518 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
536 pr_info("gpmc cs%i timings configuration:\n", cs);
537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
547 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
550 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
551 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
552 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
554 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
557 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
559 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
560 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
561 "wait-monitoring-ns", GPMC_CD_CLK);
562 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
563 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
564 "clk-activation-ns", GPMC_CD_FCLK);
566 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
567 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
570 static inline void gpmc_cs_show_timings(int cs, const char *desc)
576 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
577 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
578 * prior to calling this function with @cd equal to GPMC_CD_CLK.
580 * @cs: Chip Select Region.
581 * @reg: GPMC_CS_CONFIGn register offset.
583 * @end_bit: End Bit. Must be >= @st_bit.
584 * @max: Maximum parameter value.
585 * If 0, maximum is as high as @st_bit and @end_bit allow.
586 * @time: Timing parameter in ns.
587 * @cd: Timing parameter clock domain.
588 * @name: Timing parameter name.
589 * @return: 0 on success, -1 on error.
591 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
592 int time, enum gpmc_clk_domain cd, const char *name)
595 int ticks, mask, nr_bits;
600 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
601 nr_bits = end_bit - st_bit + 1;
602 mask = (1 << nr_bits) - 1;
608 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
609 __func__, cs, name, time, ticks, max);
614 l = gpmc_cs_read_reg(cs, reg);
615 #ifdef CONFIG_OMAP_GPMC_DEBUG
617 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
618 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
619 (l >> st_bit) & mask, time);
621 l &= ~(mask << st_bit);
622 l |= ticks << st_bit;
623 gpmc_cs_write_reg(cs, reg, l);
628 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
629 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
630 t->field, (cd), #field) < 0) \
633 #define GPMC_SET_ONE(reg, st, end, field) \
634 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
637 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
638 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
639 * read --> don't sample bus too early
640 * write --> data is longer on bus
643 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
644 * / waitmonitoring_ticks)
645 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
648 * @wait_monitoring: WAITMONITORINGTIME in ns.
649 * @return: -1 on failure to scale, else proper divider > 0.
651 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
654 int div = gpmc_ns_to_ticks(wait_monitoring);
656 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
657 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
669 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
670 * @sync_clk: GPMC_CLK period in ps.
671 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
674 int gpmc_calc_divider(unsigned int sync_clk)
676 int div = gpmc_ps_to_ticks(sync_clk);
687 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
688 * @cs: Chip Select Region.
689 * @t: GPMC timing parameters.
690 * @s: GPMC timing settings.
691 * @return: 0 on success, -1 on error.
693 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
694 const struct gpmc_settings *s)
699 gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
700 div = gpmc_calc_divider(t->sync_clk);
705 * See if we need to change the divider for waitmonitoringtime.
707 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
708 * pure asynchronous accesses, i.e. both read and write asynchronous.
709 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
710 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
712 * This statement must not change div to scale async WAITMONITORINGTIME
713 * to protect mixed synchronous and asynchronous accesses.
715 * We raise an error later if WAITMONITORINGTIME does not fit.
717 if (!s->sync_read && !s->sync_write &&
718 (s->wait_on_read || s->wait_on_write)
721 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
723 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
731 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
732 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
733 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
735 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
736 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
737 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
739 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
740 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
741 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
742 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
744 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
745 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
746 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
748 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
750 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
751 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
753 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
754 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
755 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
756 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
758 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
761 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
763 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
764 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
765 wait_monitoring, GPMC_CD_CLK);
766 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
767 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
768 clk_activation, GPMC_CD_FCLK);
770 #ifdef CONFIG_OMAP_GPMC_DEBUG
771 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
772 cs, (div * gpmc_get_fclk_period()) / 1000, div);
775 gpmc_cs_bool_timings(cs, &t->bool_timings);
776 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
781 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
787 * Ensure that base address is aligned on a
788 * boundary equal to or greater than size.
790 if (base & (size - 1))
793 base >>= GPMC_CHUNK_SHIFT;
794 mask = (1 << GPMC_SECTION_SHIFT) - size;
795 mask >>= GPMC_CHUNK_SHIFT;
796 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
798 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
799 l &= ~GPMC_CONFIG7_MASK;
800 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
801 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
802 l |= GPMC_CONFIG7_CSVALID;
803 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
808 static void gpmc_cs_enable_mem(int cs)
812 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
813 l |= GPMC_CONFIG7_CSVALID;
814 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
817 static void gpmc_cs_disable_mem(int cs)
821 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
822 l &= ~GPMC_CONFIG7_CSVALID;
823 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
826 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
831 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
832 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
833 mask = (l >> 8) & 0x0f;
834 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
837 static int gpmc_cs_mem_enabled(int cs)
841 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
842 return l & GPMC_CONFIG7_CSVALID;
845 static void gpmc_cs_set_reserved(int cs, int reserved)
847 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
849 gpmc->flags |= GPMC_CS_RESERVED;
852 static bool gpmc_cs_reserved(int cs)
854 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
856 return gpmc->flags & GPMC_CS_RESERVED;
859 static void gpmc_cs_set_name(int cs, const char *name)
861 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
866 static const char *gpmc_cs_get_name(int cs)
868 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
873 static unsigned long gpmc_mem_align(unsigned long size)
877 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
878 order = GPMC_CHUNK_SHIFT - 1;
887 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
889 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
890 struct resource *res = &gpmc->mem;
893 size = gpmc_mem_align(size);
894 spin_lock(&gpmc_mem_lock);
896 res->end = base + size - 1;
897 r = request_resource(&gpmc_mem_root, res);
898 spin_unlock(&gpmc_mem_lock);
903 static int gpmc_cs_delete_mem(int cs)
905 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
906 struct resource *res = &gpmc->mem;
909 spin_lock(&gpmc_mem_lock);
910 r = release_resource(res);
913 spin_unlock(&gpmc_mem_lock);
919 * gpmc_cs_remap - remaps a chip-select physical base address
920 * @cs: chip-select to remap
921 * @base: physical base address to re-map chip-select to
923 * Re-maps a chip-select to a new physical base address specified by
924 * "base". Returns 0 on success and appropriate negative error code
927 static int gpmc_cs_remap(int cs, u32 base)
932 if (cs > gpmc_cs_num) {
933 pr_err("%s: requested chip-select is disabled\n", __func__);
938 * Make sure we ignore any device offsets from the GPMC partition
939 * allocated for the chip select and that the new base confirms
940 * to the GPMC 16MB minimum granularity.
942 base &= ~(SZ_16M - 1);
944 gpmc_cs_get_memconf(cs, &old_base, &size);
945 if (base == old_base)
948 ret = gpmc_cs_delete_mem(cs);
952 ret = gpmc_cs_insert_mem(cs, base, size);
956 ret = gpmc_cs_set_memconf(cs, base, size);
961 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
963 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
964 struct resource *res = &gpmc->mem;
967 if (cs > gpmc_cs_num) {
968 pr_err("%s: requested chip-select is disabled\n", __func__);
971 size = gpmc_mem_align(size);
972 if (size > (1 << GPMC_SECTION_SHIFT))
975 spin_lock(&gpmc_mem_lock);
976 if (gpmc_cs_reserved(cs)) {
980 if (gpmc_cs_mem_enabled(cs))
981 r = adjust_resource(res, res->start & ~(size - 1), size);
983 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
988 /* Disable CS while changing base address and size mask */
989 gpmc_cs_disable_mem(cs);
991 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
993 release_resource(res);
998 gpmc_cs_enable_mem(cs);
1000 gpmc_cs_set_reserved(cs, 1);
1002 spin_unlock(&gpmc_mem_lock);
1005 EXPORT_SYMBOL(gpmc_cs_request);
1007 void gpmc_cs_free(int cs)
1009 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1010 struct resource *res = &gpmc->mem;
1012 spin_lock(&gpmc_mem_lock);
1013 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1014 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1016 spin_unlock(&gpmc_mem_lock);
1019 gpmc_cs_disable_mem(cs);
1021 release_resource(res);
1022 gpmc_cs_set_reserved(cs, 0);
1023 spin_unlock(&gpmc_mem_lock);
1025 EXPORT_SYMBOL(gpmc_cs_free);
1028 * gpmc_configure - write request to configure gpmc
1029 * @cmd: command type
1030 * @wval: value to write
1031 * @return status of the operation
1033 int gpmc_configure(int cmd, int wval)
1038 case GPMC_ENABLE_IRQ:
1039 gpmc_write_reg(GPMC_IRQENABLE, wval);
1042 case GPMC_SET_IRQ_STATUS:
1043 gpmc_write_reg(GPMC_IRQSTATUS, wval);
1046 case GPMC_CONFIG_WP:
1047 regval = gpmc_read_reg(GPMC_CONFIG);
1049 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1051 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1052 gpmc_write_reg(GPMC_CONFIG, regval);
1056 pr_err("%s: command not supported\n", __func__);
1062 EXPORT_SYMBOL(gpmc_configure);
1064 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1068 reg->gpmc_status = gpmc_base + GPMC_STATUS;
1069 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1070 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1071 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1072 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1073 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1074 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1075 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1076 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1077 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1078 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1079 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1080 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1081 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1082 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1084 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1085 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1087 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1089 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1091 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1093 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1095 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1097 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1102 int gpmc_get_client_irq(unsigned irq_config)
1106 if (hweight32(irq_config) > 1)
1109 for (i = 0; i < GPMC_NR_IRQ; i++)
1110 if (gpmc_client_irq[i].bitmask & irq_config)
1111 return gpmc_client_irq[i].irq;
1116 static int gpmc_irq_endis(unsigned irq, bool endis)
1121 for (i = 0; i < GPMC_NR_IRQ; i++)
1122 if (irq == gpmc_client_irq[i].irq) {
1123 regval = gpmc_read_reg(GPMC_IRQENABLE);
1125 regval |= gpmc_client_irq[i].bitmask;
1127 regval &= ~gpmc_client_irq[i].bitmask;
1128 gpmc_write_reg(GPMC_IRQENABLE, regval);
1135 static void gpmc_irq_disable(struct irq_data *p)
1137 gpmc_irq_endis(p->irq, false);
1140 static void gpmc_irq_enable(struct irq_data *p)
1142 gpmc_irq_endis(p->irq, true);
1145 static void gpmc_irq_noop(struct irq_data *data) { }
1147 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1149 static int gpmc_setup_irq(void)
1157 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
1158 if (gpmc_irq_start < 0) {
1159 pr_err("irq_alloc_descs failed\n");
1160 return gpmc_irq_start;
1163 gpmc_irq_chip.name = "gpmc";
1164 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
1165 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
1166 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
1167 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
1168 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
1169 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
1170 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
1172 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
1173 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
1175 for (i = 0; i < GPMC_NR_IRQ; i++) {
1176 gpmc_client_irq[i].irq = gpmc_irq_start + i;
1177 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
1178 &gpmc_irq_chip, handle_simple_irq);
1179 irq_modify_status(gpmc_client_irq[i].irq, IRQ_NOREQUEST,
1183 /* Disable interrupts */
1184 gpmc_write_reg(GPMC_IRQENABLE, 0);
1186 /* clear interrupts */
1187 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1188 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1190 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
1193 static int gpmc_free_irq(void)
1198 free_irq(gpmc_irq, NULL);
1200 for (i = 0; i < GPMC_NR_IRQ; i++) {
1201 irq_set_handler(gpmc_client_irq[i].irq, NULL);
1202 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
1205 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
1210 static void gpmc_mem_exit(void)
1214 for (cs = 0; cs < gpmc_cs_num; cs++) {
1215 if (!gpmc_cs_mem_enabled(cs))
1217 gpmc_cs_delete_mem(cs);
1222 static void gpmc_mem_init(void)
1227 * The first 1MB of GPMC address space is typically mapped to
1228 * the internal ROM. Never allocate the first page, to
1229 * facilitate bug detection; even if we didn't boot from ROM.
1231 gpmc_mem_root.start = SZ_1M;
1232 gpmc_mem_root.end = GPMC_MEM_END;
1234 /* Reserve all regions that has been set up by bootloader */
1235 for (cs = 0; cs < gpmc_cs_num; cs++) {
1238 if (!gpmc_cs_mem_enabled(cs))
1240 gpmc_cs_get_memconf(cs, &base, &size);
1241 if (gpmc_cs_insert_mem(cs, base, size)) {
1242 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1243 __func__, cs, base, base + size);
1244 gpmc_cs_disable_mem(cs);
1249 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1254 div = gpmc_calc_divider(sync_clk);
1255 temp = gpmc_ps_to_ticks(time_ps);
1256 temp = (temp + div - 1) / div;
1257 return gpmc_ticks_to_ps(temp * div);
1260 /* XXX: can the cycles be avoided ? */
1261 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1262 struct gpmc_device_timings *dev_t,
1268 temp = dev_t->t_avdp_r;
1269 /* XXX: mux check required ? */
1271 /* XXX: t_avdp not to be required for sync, only added for tusb
1272 * this indirectly necessitates requirement of t_avdp_r and
1273 * t_avdp_w instead of having a single t_avdp
1275 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1276 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1278 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1281 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1283 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1284 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1285 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1287 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1290 /* XXX: any scope for improvement ?, by combining oe_on
1291 * and clk_activation, need to check whether
1292 * access = clk_activation + round to sync clk ?
1294 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1295 temp += gpmc_t->clk_activation;
1297 temp = max_t(u32, temp, gpmc_t->oe_on +
1298 gpmc_ticks_to_ps(dev_t->cyc_oe));
1299 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1301 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1302 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1305 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1306 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1308 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1309 if (dev_t->t_ce_rdyz)
1310 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1311 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1316 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1317 struct gpmc_device_timings *dev_t,
1323 temp = dev_t->t_avdp_w;
1325 temp = max_t(u32, temp,
1326 gpmc_t->clk_activation + dev_t->t_avdh);
1327 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1329 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1331 /* wr_data_mux_bus */
1332 temp = max_t(u32, dev_t->t_weasu,
1333 gpmc_t->clk_activation + dev_t->t_rdyo);
1334 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1335 * and in that case remember to handle we_on properly
1338 temp = max_t(u32, temp,
1339 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1340 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1341 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1343 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1346 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1347 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1349 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1352 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1353 gpmc_t->wr_access = gpmc_t->access;
1356 temp = gpmc_t->we_on + dev_t->t_wpl;
1357 temp = max_t(u32, temp,
1358 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1359 temp = max_t(u32, temp,
1360 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1361 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1363 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1367 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1368 temp += gpmc_t->wr_access;
1369 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1370 if (dev_t->t_ce_rdyz)
1371 temp = max_t(u32, temp,
1372 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1373 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1378 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1379 struct gpmc_device_timings *dev_t,
1385 temp = dev_t->t_avdp_r;
1387 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1388 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1391 temp = dev_t->t_oeasu;
1393 temp = max_t(u32, temp,
1394 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1395 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1398 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1399 gpmc_t->oe_on + dev_t->t_oe);
1400 temp = max_t(u32, temp,
1401 gpmc_t->cs_on + dev_t->t_ce);
1402 temp = max_t(u32, temp,
1403 gpmc_t->adv_on + dev_t->t_aa);
1404 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1406 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1407 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1410 temp = max_t(u32, dev_t->t_rd_cycle,
1411 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1412 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1413 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1418 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1419 struct gpmc_device_timings *dev_t,
1425 temp = dev_t->t_avdp_w;
1427 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1428 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1430 /* wr_data_mux_bus */
1431 temp = dev_t->t_weasu;
1433 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1434 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1435 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1437 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1440 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1441 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1443 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1446 temp = gpmc_t->we_on + dev_t->t_wpl;
1447 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1449 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1453 temp = max_t(u32, dev_t->t_wr_cycle,
1454 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1455 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1460 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1461 struct gpmc_device_timings *dev_t)
1465 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1466 gpmc_get_fclk_period();
1468 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1472 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1473 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1475 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1478 if (dev_t->ce_xdelay)
1479 gpmc_t->bool_timings.cs_extra_delay = true;
1480 if (dev_t->avd_xdelay)
1481 gpmc_t->bool_timings.adv_extra_delay = true;
1482 if (dev_t->oe_xdelay)
1483 gpmc_t->bool_timings.oe_extra_delay = true;
1484 if (dev_t->we_xdelay)
1485 gpmc_t->bool_timings.we_extra_delay = true;
1490 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1491 struct gpmc_device_timings *dev_t,
1497 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1500 temp = dev_t->t_avdasu;
1501 if (dev_t->t_ce_avd)
1502 temp = max_t(u32, temp,
1503 gpmc_t->cs_on + dev_t->t_ce_avd);
1504 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1507 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1512 /* TODO: remove this function once all peripherals are confirmed to
1513 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1514 * has to be modified to handle timings in ps instead of ns
1516 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1519 t->cs_rd_off /= 1000;
1520 t->cs_wr_off /= 1000;
1522 t->adv_rd_off /= 1000;
1523 t->adv_wr_off /= 1000;
1528 t->page_burst_access /= 1000;
1530 t->rd_cycle /= 1000;
1531 t->wr_cycle /= 1000;
1532 t->bus_turnaround /= 1000;
1533 t->cycle2cycle_delay /= 1000;
1534 t->wait_monitoring /= 1000;
1535 t->clk_activation /= 1000;
1536 t->wr_access /= 1000;
1537 t->wr_data_mux_bus /= 1000;
1540 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1541 struct gpmc_settings *gpmc_s,
1542 struct gpmc_device_timings *dev_t)
1544 bool mux = false, sync = false;
1547 mux = gpmc_s->mux_add_data ? true : false;
1548 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1551 memset(gpmc_t, 0, sizeof(*gpmc_t));
1553 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1555 if (gpmc_s && gpmc_s->sync_read)
1556 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1558 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1560 if (gpmc_s && gpmc_s->sync_write)
1561 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1563 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1565 /* TODO: remove, see function definition */
1566 gpmc_convert_ps_to_ns(gpmc_t);
1572 * gpmc_cs_program_settings - programs non-timing related settings
1573 * @cs: GPMC chip-select to program
1574 * @p: pointer to GPMC settings structure
1576 * Programs non-timing related settings for a GPMC chip-select, such as
1577 * bus-width, burst configuration, etc. Function should be called once
1578 * for each chip-select that is being used and must be called before
1579 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1580 * register will be initialised to zero by this function. Returns 0 on
1581 * success and appropriate negative error code on failure.
1583 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1587 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1588 pr_err("%s: invalid width %d!", __func__, p->device_width);
1592 /* Address-data multiplexing not supported for NAND devices */
1593 if (p->device_nand && p->mux_add_data) {
1594 pr_err("%s: invalid configuration!\n", __func__);
1598 if ((p->mux_add_data > GPMC_MUX_AD) ||
1599 ((p->mux_add_data == GPMC_MUX_AAD) &&
1600 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1601 pr_err("%s: invalid multiplex configuration!\n", __func__);
1605 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1606 if (p->burst_read || p->burst_write) {
1607 switch (p->burst_len) {
1613 pr_err("%s: invalid page/burst-length (%d)\n",
1614 __func__, p->burst_len);
1619 if (p->wait_pin > gpmc_nr_waitpins) {
1620 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1624 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1627 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1629 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1630 if (p->wait_on_read)
1631 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1632 if (p->wait_on_write)
1633 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1634 if (p->wait_on_read || p->wait_on_write)
1635 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1637 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1638 if (p->mux_add_data)
1639 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1641 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1643 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1644 if (p->burst_read || p->burst_write) {
1645 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1646 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1649 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1655 static const struct of_device_id gpmc_dt_ids[] = {
1656 { .compatible = "ti,omap2420-gpmc" },
1657 { .compatible = "ti,omap2430-gpmc" },
1658 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1659 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1660 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1663 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1666 * gpmc_read_settings_dt - read gpmc settings from device-tree
1667 * @np: pointer to device-tree node for a gpmc child device
1668 * @p: pointer to gpmc settings structure
1670 * Reads the GPMC settings for a GPMC child device from device-tree and
1671 * stores them in the GPMC settings structure passed. The GPMC settings
1672 * structure is initialised to zero by this function and so any
1673 * previously stored settings will be cleared.
1675 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1677 memset(p, 0, sizeof(struct gpmc_settings));
1679 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1680 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1681 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1682 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1684 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1685 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1686 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1687 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1688 if (!p->burst_read && !p->burst_write)
1689 pr_warn("%s: page/burst-length set but not used!\n",
1693 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1694 p->wait_on_read = of_property_read_bool(np,
1695 "gpmc,wait-on-read");
1696 p->wait_on_write = of_property_read_bool(np,
1697 "gpmc,wait-on-write");
1698 if (!p->wait_on_read && !p->wait_on_write)
1699 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1704 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1705 struct gpmc_timings *gpmc_t)
1707 struct gpmc_bool_timings *p;
1712 memset(gpmc_t, 0, sizeof(*gpmc_t));
1714 /* minimum clock period for syncronous mode */
1715 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1717 /* chip select timtings */
1718 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1719 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1720 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1722 /* ADV signal timings */
1723 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1724 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1725 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1727 /* WE signal timings */
1728 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1729 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1731 /* OE signal timings */
1732 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1733 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1735 /* access and cycle timings */
1736 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1737 &gpmc_t->page_burst_access);
1738 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1739 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1740 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1741 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1742 &gpmc_t->bus_turnaround);
1743 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1744 &gpmc_t->cycle2cycle_delay);
1745 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1746 &gpmc_t->wait_monitoring);
1747 of_property_read_u32(np, "gpmc,clk-activation-ns",
1748 &gpmc_t->clk_activation);
1750 /* only applicable to OMAP3+ */
1751 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1752 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1753 &gpmc_t->wr_data_mux_bus);
1755 /* bool timing parameters */
1756 p = &gpmc_t->bool_timings;
1758 p->cycle2cyclediffcsen =
1759 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1760 p->cycle2cyclesamecsen =
1761 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1762 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1763 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1764 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1765 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1766 p->time_para_granularity =
1767 of_property_read_bool(np, "gpmc,time-para-granularity");
1770 #if IS_ENABLED(CONFIG_MTD_NAND)
1772 static const char * const nand_xfer_types[] = {
1773 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1774 [NAND_OMAP_POLLED] = "polled",
1775 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1776 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1779 static int gpmc_probe_nand_child(struct platform_device *pdev,
1780 struct device_node *child)
1784 struct gpmc_timings gpmc_t;
1785 struct omap_nand_platform_data *gpmc_nand_data;
1787 if (of_property_read_u32(child, "reg", &val) < 0) {
1788 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1793 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1795 if (!gpmc_nand_data)
1798 gpmc_nand_data->cs = val;
1799 gpmc_nand_data->of_node = child;
1801 /* Detect availability of ELM module */
1802 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1803 if (gpmc_nand_data->elm_of_node == NULL)
1804 gpmc_nand_data->elm_of_node =
1805 of_parse_phandle(child, "elm_id", 0);
1807 /* select ecc-scheme for NAND */
1808 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1809 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1813 if (!strcmp(s, "sw"))
1814 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1815 else if (!strcmp(s, "ham1") ||
1816 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1817 gpmc_nand_data->ecc_opt =
1818 OMAP_ECC_HAM1_CODE_HW;
1819 else if (!strcmp(s, "bch4"))
1820 if (gpmc_nand_data->elm_of_node)
1821 gpmc_nand_data->ecc_opt =
1822 OMAP_ECC_BCH4_CODE_HW;
1824 gpmc_nand_data->ecc_opt =
1825 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1826 else if (!strcmp(s, "bch8"))
1827 if (gpmc_nand_data->elm_of_node)
1828 gpmc_nand_data->ecc_opt =
1829 OMAP_ECC_BCH8_CODE_HW;
1831 gpmc_nand_data->ecc_opt =
1832 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1833 else if (!strcmp(s, "bch16"))
1834 if (gpmc_nand_data->elm_of_node)
1835 gpmc_nand_data->ecc_opt =
1836 OMAP_ECC_BCH16_CODE_HW;
1838 pr_err("%s: BCH16 requires ELM support\n", __func__);
1840 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1842 /* select data transfer mode for NAND controller */
1843 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1844 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1845 if (!strcasecmp(s, nand_xfer_types[val])) {
1846 gpmc_nand_data->xfer_type = val;
1850 gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1852 val = of_get_nand_bus_width(child);
1854 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1856 gpmc_read_timings_dt(child, &gpmc_t);
1857 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1862 static int gpmc_probe_nand_child(struct platform_device *pdev,
1863 struct device_node *child)
1869 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1870 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1871 struct device_node *child)
1874 struct omap_onenand_platform_data *gpmc_onenand_data;
1876 if (of_property_read_u32(child, "reg", &val) < 0) {
1877 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1882 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1884 if (!gpmc_onenand_data)
1887 gpmc_onenand_data->cs = val;
1888 gpmc_onenand_data->of_node = child;
1889 gpmc_onenand_data->dma_channel = -1;
1891 if (!of_property_read_u32(child, "dma-channel", &val))
1892 gpmc_onenand_data->dma_channel = val;
1894 gpmc_onenand_init(gpmc_onenand_data);
1899 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1900 struct device_node *child)
1907 * gpmc_probe_generic_child - configures the gpmc for a child device
1908 * @pdev: pointer to gpmc platform device
1909 * @child: pointer to device-tree node for child device
1911 * Allocates and configures a GPMC chip-select for a child device.
1912 * Returns 0 on success and appropriate negative error code on failure.
1914 static int gpmc_probe_generic_child(struct platform_device *pdev,
1915 struct device_node *child)
1917 struct gpmc_settings gpmc_s;
1918 struct gpmc_timings gpmc_t;
1919 struct resource res;
1925 if (of_property_read_u32(child, "reg", &cs) < 0) {
1926 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1931 if (of_address_to_resource(child, 0, &res) < 0) {
1932 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1938 * Check if we have multiple instances of the same device
1939 * on a single chip select. If so, use the already initialized
1942 name = gpmc_cs_get_name(cs);
1943 if (name && child->name && of_node_cmp(child->name, name) == 0)
1946 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1948 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1951 gpmc_cs_set_name(cs, child->name);
1953 gpmc_read_settings_dt(child, &gpmc_s);
1954 gpmc_read_timings_dt(child, &gpmc_t);
1957 * For some GPMC devices we still need to rely on the bootloader
1958 * timings because the devices can be connected via FPGA.
1959 * REVISIT: Add timing support from slls644g.pdf.
1961 if (!gpmc_t.cs_rd_off) {
1962 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1964 gpmc_cs_show_timings(cs,
1965 "please add GPMC bootloader timings to .dts");
1969 /* CS must be disabled while making changes to gpmc configuration */
1970 gpmc_cs_disable_mem(cs);
1973 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1974 * location in the gpmc address space. When booting with
1975 * device-tree we want the NOR flash to be mapped to the
1976 * location specified in the device-tree blob. So remap the
1977 * CS to this location. Once DT migration is complete should
1978 * just make gpmc_cs_request() map a specific address.
1980 ret = gpmc_cs_remap(cs, res.start);
1982 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1987 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1991 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1995 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1997 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2002 /* Clear limited address i.e. enable A26-A11 */
2003 val = gpmc_read_reg(GPMC_CONFIG);
2004 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2005 gpmc_write_reg(GPMC_CONFIG, val);
2007 /* Enable CS region */
2008 gpmc_cs_enable_mem(cs);
2012 /* create platform device, NULL on error or when disabled */
2013 if (!of_platform_device_create(child, NULL, &pdev->dev))
2014 goto err_child_fail;
2016 /* is child a common bus? */
2017 if (of_match_node(of_default_bus_match_table, child))
2018 /* create children and other common bus children */
2019 if (of_platform_populate(child, of_default_bus_match_table,
2021 goto err_child_fail;
2027 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2036 static int gpmc_probe_dt(struct platform_device *pdev)
2039 struct device_node *child;
2040 const struct of_device_id *of_id =
2041 of_match_device(gpmc_dt_ids, &pdev->dev);
2046 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2049 pr_err("%s: number of chip-selects not defined\n", __func__);
2051 } else if (gpmc_cs_num < 1) {
2052 pr_err("%s: all chip-selects are disabled\n", __func__);
2054 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2055 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2056 __func__, GPMC_CS_NUM);
2060 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2063 pr_err("%s: number of wait pins not found!\n", __func__);
2067 for_each_available_child_of_node(pdev->dev.of_node, child) {
2072 if (of_node_cmp(child->name, "nand") == 0)
2073 ret = gpmc_probe_nand_child(pdev, child);
2074 else if (of_node_cmp(child->name, "onenand") == 0)
2075 ret = gpmc_probe_onenand_child(pdev, child);
2077 ret = gpmc_probe_generic_child(pdev, child);
2083 static int gpmc_probe_dt(struct platform_device *pdev)
2089 static int gpmc_probe(struct platform_device *pdev)
2093 struct resource *res;
2095 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2099 phys_base = res->start;
2100 mem_size = resource_size(res);
2102 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2103 if (IS_ERR(gpmc_base))
2104 return PTR_ERR(gpmc_base);
2106 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2108 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
2110 gpmc_irq = res->start;
2112 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2113 if (IS_ERR(gpmc_l3_clk)) {
2114 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2116 return PTR_ERR(gpmc_l3_clk);
2119 if (!clk_get_rate(gpmc_l3_clk)) {
2120 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2124 pm_runtime_enable(&pdev->dev);
2125 pm_runtime_get_sync(&pdev->dev);
2127 gpmc_dev = &pdev->dev;
2129 l = gpmc_read_reg(GPMC_REVISION);
2132 * FIXME: Once device-tree migration is complete the below flags
2133 * should be populated based upon the device-tree compatible
2134 * string. For now just use the IP revision. OMAP3+ devices have
2135 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2136 * devices support the addr-addr-data multiplex protocol.
2138 * GPMC IP revisions:
2141 * - OMAP44xx/54xx/AM335x = 6.0
2143 if (GPMC_REVISION_MAJOR(l) > 0x4)
2144 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2145 if (GPMC_REVISION_MAJOR(l) > 0x5)
2146 gpmc_capability |= GPMC_HAS_MUX_AAD;
2147 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2148 GPMC_REVISION_MINOR(l));
2152 if (gpmc_setup_irq() < 0)
2153 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
2155 if (!pdev->dev.of_node) {
2156 gpmc_cs_num = GPMC_CS_NUM;
2157 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2160 rc = gpmc_probe_dt(pdev);
2162 pm_runtime_put_sync(&pdev->dev);
2163 dev_err(gpmc_dev, "failed to probe DT parameters\n");
2170 static int gpmc_remove(struct platform_device *pdev)
2174 pm_runtime_put_sync(&pdev->dev);
2175 pm_runtime_disable(&pdev->dev);
2180 #ifdef CONFIG_PM_SLEEP
2181 static int gpmc_suspend(struct device *dev)
2183 omap3_gpmc_save_context();
2184 pm_runtime_put_sync(dev);
2188 static int gpmc_resume(struct device *dev)
2190 pm_runtime_get_sync(dev);
2191 omap3_gpmc_restore_context();
2196 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2198 static struct platform_driver gpmc_driver = {
2199 .probe = gpmc_probe,
2200 .remove = gpmc_remove,
2202 .name = DEVICE_NAME,
2203 .of_match_table = of_match_ptr(gpmc_dt_ids),
2208 static __init int gpmc_init(void)
2210 return platform_driver_register(&gpmc_driver);
2213 static __exit void gpmc_exit(void)
2215 platform_driver_unregister(&gpmc_driver);
2219 postcore_initcall(gpmc_init);
2220 module_exit(gpmc_exit);
2222 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
2227 regval = gpmc_read_reg(GPMC_IRQSTATUS);
2232 for (i = 0; i < GPMC_NR_IRQ; i++)
2233 if (regval & gpmc_client_irq[i].bitmask)
2234 generic_handle_irq(gpmc_client_irq[i].irq);
2236 gpmc_write_reg(GPMC_IRQSTATUS, regval);
2241 static struct omap3_gpmc_regs gpmc_context;
2243 void omap3_gpmc_save_context(void)
2250 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2251 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2252 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2253 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2254 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2255 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2256 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2257 for (i = 0; i < gpmc_cs_num; i++) {
2258 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2259 if (gpmc_context.cs_context[i].is_valid) {
2260 gpmc_context.cs_context[i].config1 =
2261 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2262 gpmc_context.cs_context[i].config2 =
2263 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2264 gpmc_context.cs_context[i].config3 =
2265 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2266 gpmc_context.cs_context[i].config4 =
2267 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2268 gpmc_context.cs_context[i].config5 =
2269 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2270 gpmc_context.cs_context[i].config6 =
2271 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2272 gpmc_context.cs_context[i].config7 =
2273 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2278 void omap3_gpmc_restore_context(void)
2285 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2286 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2287 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2288 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2289 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2290 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2291 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2292 for (i = 0; i < gpmc_cs_num; i++) {
2293 if (gpmc_context.cs_context[i].is_valid) {
2294 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2295 gpmc_context.cs_context[i].config1);
2296 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2297 gpmc_context.cs_context[i].config2);
2298 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2299 gpmc_context.cs_context[i].config3);
2300 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2301 gpmc_context.cs_context[i].config4);
2302 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2303 gpmc_context.cs_context[i].config5);
2304 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2305 gpmc_context.cs_context[i].config6);
2306 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2307 gpmc_context.cs_context[i].config7);