2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <asm/cacheflush.h>
14 #include <dt-bindings/memory/tegra124-mc.h>
18 static const struct tegra_mc_client tegra124_mc_clients[] = {
22 .swgroup = TEGRA_SWGROUP_PTC,
26 .swgroup = TEGRA_SWGROUP_DC,
40 .swgroup = TEGRA_SWGROUP_DCB,
54 .swgroup = TEGRA_SWGROUP_DC,
68 .swgroup = TEGRA_SWGROUP_DCB,
82 .swgroup = TEGRA_SWGROUP_DC,
96 .swgroup = TEGRA_SWGROUP_DCB,
110 .swgroup = TEGRA_SWGROUP_AFI,
124 .swgroup = TEGRA_SWGROUP_AVPC,
138 .swgroup = TEGRA_SWGROUP_DC,
151 .name = "displayhcb",
152 .swgroup = TEGRA_SWGROUP_DCB,
166 .swgroup = TEGRA_SWGROUP_HDA,
179 .name = "host1xdmar",
180 .swgroup = TEGRA_SWGROUP_HC,
194 .swgroup = TEGRA_SWGROUP_HC,
208 .swgroup = TEGRA_SWGROUP_MSENC,
221 .name = "ppcsahbdmar",
222 .swgroup = TEGRA_SWGROUP_PPCS,
235 .name = "ppcsahbslvr",
236 .swgroup = TEGRA_SWGROUP_PPCS,
250 .swgroup = TEGRA_SWGROUP_SATA,
264 .swgroup = TEGRA_SWGROUP_VDE,
278 .swgroup = TEGRA_SWGROUP_VDE,
292 .swgroup = TEGRA_SWGROUP_VDE,
306 .swgroup = TEGRA_SWGROUP_VDE,
320 .swgroup = TEGRA_SWGROUP_MPCORELP,
330 .swgroup = TEGRA_SWGROUP_MPCORE,
340 .swgroup = TEGRA_SWGROUP_MSENC,
354 .swgroup = TEGRA_SWGROUP_AFI,
368 .swgroup = TEGRA_SWGROUP_AVPC,
382 .swgroup = TEGRA_SWGROUP_HDA,
396 .swgroup = TEGRA_SWGROUP_HC,
410 .swgroup = TEGRA_SWGROUP_MPCORELP,
420 .swgroup = TEGRA_SWGROUP_MPCORE,
429 .name = "ppcsahbdmaw",
430 .swgroup = TEGRA_SWGROUP_PPCS,
443 .name = "ppcsahbslvw",
444 .swgroup = TEGRA_SWGROUP_PPCS,
458 .swgroup = TEGRA_SWGROUP_SATA,
472 .swgroup = TEGRA_SWGROUP_VDE,
486 .swgroup = TEGRA_SWGROUP_VDE,
500 .swgroup = TEGRA_SWGROUP_VDE,
514 .swgroup = TEGRA_SWGROUP_VDE,
528 .swgroup = TEGRA_SWGROUP_ISP2,
542 .swgroup = TEGRA_SWGROUP_ISP2,
556 .swgroup = TEGRA_SWGROUP_ISP2,
569 .name = "xusb_hostr",
570 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
583 .name = "xusb_hostw",
584 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
598 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
612 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
626 .swgroup = TEGRA_SWGROUP_ISP2B,
640 .swgroup = TEGRA_SWGROUP_ISP2B,
654 .swgroup = TEGRA_SWGROUP_ISP2B,
668 .swgroup = TEGRA_SWGROUP_TSEC,
682 .swgroup = TEGRA_SWGROUP_TSEC,
696 .swgroup = TEGRA_SWGROUP_A9AVP,
710 .swgroup = TEGRA_SWGROUP_A9AVP,
724 .swgroup = TEGRA_SWGROUP_GPU,
739 .swgroup = TEGRA_SWGROUP_GPU,
754 .swgroup = TEGRA_SWGROUP_DC,
768 .swgroup = TEGRA_SWGROUP_SDMMC1A,
782 .swgroup = TEGRA_SWGROUP_SDMMC2A,
796 .swgroup = TEGRA_SWGROUP_SDMMC3A,
809 .swgroup = TEGRA_SWGROUP_SDMMC4A,
824 .swgroup = TEGRA_SWGROUP_SDMMC1A,
838 .swgroup = TEGRA_SWGROUP_SDMMC2A,
852 .swgroup = TEGRA_SWGROUP_SDMMC3A,
866 .swgroup = TEGRA_SWGROUP_SDMMC4A,
880 .swgroup = TEGRA_SWGROUP_VIC,
894 .swgroup = TEGRA_SWGROUP_VIC,
908 .swgroup = TEGRA_SWGROUP_VI,
922 .swgroup = TEGRA_SWGROUP_DC,
936 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
937 { .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
938 { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
939 { .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
940 { .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
941 { .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
942 { .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
943 { .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
944 { .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
945 { .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
946 { .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
947 { .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
948 { .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
949 { .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
950 { .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
951 { .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
952 { .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
953 { .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
954 { .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
955 { .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
956 { .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
957 { .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
958 { .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
959 { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
962 #ifdef CONFIG_ARCH_TEGRA_124_SOC
963 static void tegra124_flush_dcache(struct page *page, unsigned long offset,
966 phys_addr_t phys = page_to_phys(page) + offset;
967 void *virt = page_address(page) + offset;
969 __cpuc_flush_dcache_area(virt, size);
970 outer_flush_range(phys, phys + size);
973 static const struct tegra_smmu_ops tegra124_smmu_ops = {
974 .flush_dcache = tegra124_flush_dcache,
977 static const struct tegra_smmu_soc tegra124_smmu_soc = {
978 .clients = tegra124_mc_clients,
979 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
980 .swgroups = tegra124_swgroups,
981 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
982 .supports_round_robin_arbitration = true,
983 .supports_request_limit = true,
985 .ops = &tegra124_smmu_ops,
988 const struct tegra_mc_soc tegra124_mc_soc = {
989 .clients = tegra124_mc_clients,
990 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
991 .num_address_bits = 34,
993 .smmu = &tegra124_smmu_soc,
995 #endif /* CONFIG_ARCH_TEGRA_124_SOC */