2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <asm/cacheflush.h>
14 #include <dt-bindings/memory/tegra30-mc.h>
18 static const struct tegra_mc_client tegra30_mc_clients[] = {
22 .swgroup = TEGRA_SWGROUP_PTC,
26 .swgroup = TEGRA_SWGROUP_DC,
40 .swgroup = TEGRA_SWGROUP_DCB,
54 .swgroup = TEGRA_SWGROUP_DC,
68 .swgroup = TEGRA_SWGROUP_DCB,
82 .swgroup = TEGRA_SWGROUP_DC,
96 .swgroup = TEGRA_SWGROUP_DCB,
110 .swgroup = TEGRA_SWGROUP_DC,
123 .name = "display1bb",
124 .swgroup = TEGRA_SWGROUP_DCB,
138 .swgroup = TEGRA_SWGROUP_EPP,
152 .swgroup = TEGRA_SWGROUP_G2,
166 .swgroup = TEGRA_SWGROUP_G2,
180 .swgroup = TEGRA_SWGROUP_MPE,
194 .swgroup = TEGRA_SWGROUP_VI,
208 .swgroup = TEGRA_SWGROUP_AFI,
222 .swgroup = TEGRA_SWGROUP_AVPC,
236 .swgroup = TEGRA_SWGROUP_DC,
249 .name = "displayhcb",
250 .swgroup = TEGRA_SWGROUP_DCB,
264 .swgroup = TEGRA_SWGROUP_NV,
278 .swgroup = TEGRA_SWGROUP_NV2,
292 .swgroup = TEGRA_SWGROUP_G2,
306 .swgroup = TEGRA_SWGROUP_HDA,
319 .name = "host1xdmar",
320 .swgroup = TEGRA_SWGROUP_HC,
334 .swgroup = TEGRA_SWGROUP_HC,
348 .swgroup = TEGRA_SWGROUP_NV,
362 .swgroup = TEGRA_SWGROUP_NV2,
376 .swgroup = TEGRA_SWGROUP_MPE,
390 .swgroup = TEGRA_SWGROUP_MPE,
404 .swgroup = TEGRA_SWGROUP_MPE,
417 .name = "ppcsahbdmar",
418 .swgroup = TEGRA_SWGROUP_PPCS,
431 .name = "ppcsahbslvr",
432 .swgroup = TEGRA_SWGROUP_PPCS,
446 .swgroup = TEGRA_SWGROUP_SATA,
460 .swgroup = TEGRA_SWGROUP_NV,
474 .swgroup = TEGRA_SWGROUP_NV2,
488 .swgroup = TEGRA_SWGROUP_VDE,
502 .swgroup = TEGRA_SWGROUP_VDE,
516 .swgroup = TEGRA_SWGROUP_VDE,
530 .swgroup = TEGRA_SWGROUP_VDE,
544 .swgroup = TEGRA_SWGROUP_MPCORELP,
554 .swgroup = TEGRA_SWGROUP_MPCORE,
564 .swgroup = TEGRA_SWGROUP_EPP,
578 .swgroup = TEGRA_SWGROUP_EPP,
592 .swgroup = TEGRA_SWGROUP_EPP,
606 .swgroup = TEGRA_SWGROUP_MPE,
620 .swgroup = TEGRA_SWGROUP_VI,
634 .swgroup = TEGRA_SWGROUP_VI,
648 .swgroup = TEGRA_SWGROUP_VI,
662 .swgroup = TEGRA_SWGROUP_VI,
676 .swgroup = TEGRA_SWGROUP_G2,
690 .swgroup = TEGRA_SWGROUP_AFI,
704 .swgroup = TEGRA_SWGROUP_AVPC,
718 .swgroup = TEGRA_SWGROUP_NV,
732 .swgroup = TEGRA_SWGROUP_NV2,
746 .swgroup = TEGRA_SWGROUP_HDA,
760 .swgroup = TEGRA_SWGROUP_HC,
774 .swgroup = TEGRA_SWGROUP_ISP,
788 .swgroup = TEGRA_SWGROUP_MPCORELP,
798 .swgroup = TEGRA_SWGROUP_MPCORE,
808 .swgroup = TEGRA_SWGROUP_MPE,
821 .name = "ppcsahbdmaw",
822 .swgroup = TEGRA_SWGROUP_PPCS,
835 .name = "ppcsahbslvw",
836 .swgroup = TEGRA_SWGROUP_PPCS,
850 .swgroup = TEGRA_SWGROUP_SATA,
864 .swgroup = TEGRA_SWGROUP_VDE,
878 .swgroup = TEGRA_SWGROUP_VDE,
892 .swgroup = TEGRA_SWGROUP_VDE,
906 .swgroup = TEGRA_SWGROUP_VDE,
920 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
921 { .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
922 { .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
923 { .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
924 { .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
925 { .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
926 { .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
927 { .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
928 { .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
929 { .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
930 { .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
931 { .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
932 { .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
933 { .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
934 { .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
935 { .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
936 { .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
939 static void tegra30_flush_dcache(struct page *page, unsigned long offset,
942 phys_addr_t phys = page_to_phys(page) + offset;
943 void *virt = page_address(page) + offset;
945 __cpuc_flush_dcache_area(virt, size);
946 outer_flush_range(phys, phys + size);
949 static const struct tegra_smmu_ops tegra30_smmu_ops = {
950 .flush_dcache = tegra30_flush_dcache,
953 static const struct tegra_smmu_soc tegra30_smmu_soc = {
954 .clients = tegra30_mc_clients,
955 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
956 .swgroups = tegra30_swgroups,
957 .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
958 .supports_round_robin_arbitration = false,
959 .supports_request_limit = false,
961 .ops = &tegra30_smmu_ops,
964 const struct tegra_mc_soc tegra30_mc_soc = {
965 .clients = tegra30_mc_clients,
966 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
967 .num_address_bits = 32,
969 .smmu = &tegra30_smmu_soc,