2 * lpc_ich.c - LPC interface for Intel ICH
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
9 * This driver is derived from lpc_sch.
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * This driver supports the following I/O Controller hubs:
28 * (See the intel documentation on http://developer.intel.com.)
29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
30 * document number 290687-002, 298242-027: 82801BA (ICH2)
31 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
33 * document number 290744-001, 290745-025: 82801DB (ICH4)
34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
35 * document number 273599-001, 273645-002: 82801E (C-ICH)
36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
37 * document number 300641-004, 300884-013: 6300ESB
38 * document number 301473-002, 301474-026: 82801F (ICH6)
39 * document number 313082-001, 313075-006: 631xESB, 632xESB
40 * document number 307013-003, 307014-024: 82801G (ICH7)
41 * document number 322896-001, 322897-001: NM10
42 * document number 313056-003, 313057-017: 82801H (ICH8)
43 * document number 316972-004, 316973-012: 82801I (ICH9)
44 * document number 319973-002, 319974-002: 82801J (ICH10)
45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
46 * document number 320066-003, 320257-008: EP80597 (IICH)
47 * document number 324645-001, 324646-001: Cougar Point (CPT)
48 * document number TBD : Patsburg (PBG)
49 * document number TBD : DH89xxCC
50 * document number TBD : Panther Point
51 * document number TBD : Lynx Point
52 * document number TBD : Lynx Point-LP
53 * document number TBD : Wellsburg
54 * document number TBD : Avoton SoC
55 * document number TBD : Coleto Creek
56 * document number TBD : Wildcat Point-LP
59 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61 #include <linux/kernel.h>
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/acpi.h>
65 #include <linux/pci.h>
66 #include <linux/mfd/core.h>
67 #include <linux/mfd/lpc_ich.h>
70 #define ACPIBASE_GPE_OFF 0x28
71 #define ACPIBASE_GPE_END 0x2f
72 #define ACPIBASE_SMI_OFF 0x30
73 #define ACPIBASE_SMI_END 0x33
74 #define ACPIBASE_TCO_OFF 0x60
75 #define ACPIBASE_TCO_END 0x7f
78 #define ACPIBASE_GCS_OFF 0x3410
79 #define ACPIBASE_GCS_END 0x3414
81 #define GPIOBASE_ICH0 0x58
82 #define GPIOCTRL_ICH0 0x5C
83 #define GPIOBASE_ICH6 0x48
84 #define GPIOCTRL_ICH6 0x4C
88 #define wdt_io_res(i) wdt_res(0, i)
89 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
90 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
100 struct lpc_ich_cfg acpi;
101 struct lpc_ich_cfg gpio;
104 static struct resource wdt_ich_res[] = {
107 .flags = IORESOURCE_IO,
111 .flags = IORESOURCE_IO,
115 .flags = IORESOURCE_MEM,
119 static struct resource gpio_ich_res[] = {
122 .flags = IORESOURCE_IO,
126 .flags = IORESOURCE_IO,
135 static struct mfd_cell lpc_ich_cells[] = {
138 .num_resources = ARRAY_SIZE(wdt_ich_res),
139 .resources = wdt_ich_res,
140 .ignore_resource_conflicts = true,
144 .num_resources = ARRAY_SIZE(gpio_ich_res),
145 .resources = gpio_ich_res,
146 .ignore_resource_conflicts = true,
150 /* chipset related info */
152 LPC_ICH = 0, /* ICH */
155 LPC_ICH2M, /* ICH2-M */
156 LPC_ICH3, /* ICH3-S */
157 LPC_ICH3M, /* ICH3-M */
159 LPC_ICH4M, /* ICH4-M */
160 LPC_CICH, /* C-ICH */
161 LPC_ICH5, /* ICH5 & ICH5R */
162 LPC_6300ESB, /* 6300ESB */
163 LPC_ICH6, /* ICH6 & ICH6R */
164 LPC_ICH6M, /* ICH6-M */
165 LPC_ICH6W, /* ICH6W & ICH6RW */
166 LPC_631XESB, /* 631xESB/632xESB */
167 LPC_ICH7, /* ICH7 & ICH7R */
168 LPC_ICH7DH, /* ICH7DH */
169 LPC_ICH7M, /* ICH7-M & ICH7-U */
170 LPC_ICH7MDH, /* ICH7-M DH */
172 LPC_ICH8, /* ICH8 & ICH8R */
173 LPC_ICH8DH, /* ICH8DH */
174 LPC_ICH8DO, /* ICH8DO */
175 LPC_ICH8M, /* ICH8M */
176 LPC_ICH8ME, /* ICH8M-E */
178 LPC_ICH9R, /* ICH9R */
179 LPC_ICH9DH, /* ICH9DH */
180 LPC_ICH9DO, /* ICH9DO */
181 LPC_ICH9M, /* ICH9M */
182 LPC_ICH9ME, /* ICH9M-E */
183 LPC_ICH10, /* ICH10 */
184 LPC_ICH10R, /* ICH10R */
185 LPC_ICH10D, /* ICH10D */
186 LPC_ICH10DO, /* ICH10DO */
187 LPC_PCH, /* PCH Desktop Full Featured */
188 LPC_PCHM, /* PCH Mobile Full Featured */
197 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
202 LPC_EP80579, /* EP80579 */
203 LPC_CPT, /* Cougar Point */
204 LPC_CPTD, /* Cougar Point Desktop */
205 LPC_CPTM, /* Cougar Point Mobile */
206 LPC_PBG, /* Patsburg */
207 LPC_DH89XXCC, /* DH89xxCC */
208 LPC_PPT, /* Panther Point */
209 LPC_LPT, /* Lynx Point */
210 LPC_LPT_LP, /* Lynx Point-LP */
211 LPC_WBG, /* Wellsburg */
212 LPC_AVN, /* Avoton SoC */
213 LPC_COLETO, /* Coleto Creek */
214 LPC_WPT_LP, /* Wildcat Point-LP */
217 static struct lpc_ich_info lpc_chipset_info[] = {
255 .name = "ICH5 or ICH5R",
263 .name = "ICH6 or ICH6R",
265 .gpio_version = ICH_V6_GPIO,
270 .gpio_version = ICH_V6_GPIO,
273 .name = "ICH6W or ICH6RW",
275 .gpio_version = ICH_V6_GPIO,
278 .name = "631xESB/632xESB",
280 .gpio_version = ICH_V6_GPIO,
283 .name = "ICH7 or ICH7R",
285 .gpio_version = ICH_V7_GPIO,
290 .gpio_version = ICH_V7_GPIO,
293 .name = "ICH7-M or ICH7-U",
295 .gpio_version = ICH_V7_GPIO,
300 .gpio_version = ICH_V7_GPIO,
307 .name = "ICH8 or ICH8R",
309 .gpio_version = ICH_V7_GPIO,
314 .gpio_version = ICH_V7_GPIO,
319 .gpio_version = ICH_V7_GPIO,
324 .gpio_version = ICH_V7_GPIO,
329 .gpio_version = ICH_V7_GPIO,
334 .gpio_version = ICH_V9_GPIO,
339 .gpio_version = ICH_V9_GPIO,
344 .gpio_version = ICH_V9_GPIO,
349 .gpio_version = ICH_V9_GPIO,
354 .gpio_version = ICH_V9_GPIO,
359 .gpio_version = ICH_V9_GPIO,
364 .gpio_version = ICH_V10CONS_GPIO,
369 .gpio_version = ICH_V10CONS_GPIO,
374 .gpio_version = ICH_V10CORP_GPIO,
379 .gpio_version = ICH_V10CORP_GPIO,
382 .name = "PCH Desktop Full Featured",
384 .gpio_version = ICH_V5_GPIO,
387 .name = "PCH Mobile Full Featured",
389 .gpio_version = ICH_V5_GPIO,
394 .gpio_version = ICH_V5_GPIO,
399 .gpio_version = ICH_V5_GPIO,
404 .gpio_version = ICH_V5_GPIO,
409 .gpio_version = ICH_V5_GPIO,
414 .gpio_version = ICH_V5_GPIO,
419 .gpio_version = ICH_V5_GPIO,
424 .gpio_version = ICH_V5_GPIO,
429 .gpio_version = ICH_V5_GPIO,
432 .name = "PCH Mobile SFF Full Featured",
434 .gpio_version = ICH_V5_GPIO,
439 .gpio_version = ICH_V5_GPIO,
444 .gpio_version = ICH_V5_GPIO,
449 .gpio_version = ICH_V5_GPIO,
454 .gpio_version = ICH_V5_GPIO,
461 .name = "Cougar Point",
463 .gpio_version = ICH_V5_GPIO,
466 .name = "Cougar Point Desktop",
468 .gpio_version = ICH_V5_GPIO,
471 .name = "Cougar Point Mobile",
473 .gpio_version = ICH_V5_GPIO,
484 .name = "Panther Point",
488 .name = "Lynx Point",
492 .name = "Lynx Point_LP",
500 .name = "Avoton SoC",
504 .name = "Coleto Creek",
508 .name = "Wildcat Point_LP",
514 * This data only exists for exporting the supported PCI ids
515 * via MODULE_DEVICE_TABLE. We do not actually register a
516 * pci_driver, because the I/O Controller Hub has also other
517 * functions that probably will be registered by other drivers.
519 static const struct pci_device_id lpc_ich_ids[] = {
520 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
521 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
522 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
523 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
524 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
525 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
526 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
527 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
528 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
529 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
530 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
531 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
532 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
533 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
534 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
535 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
536 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
537 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
538 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
539 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
540 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
541 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
542 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
543 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
544 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
545 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
546 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
547 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
548 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
549 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
550 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
551 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
552 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
553 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
554 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
555 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
556 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
557 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
558 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
559 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
560 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
561 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
562 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
563 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
564 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
565 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
566 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
567 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
568 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
569 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
570 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
571 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
572 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
573 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
574 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
575 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
576 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
577 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
578 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
579 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
580 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
581 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
582 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
583 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
584 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
585 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
586 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
588 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
589 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
598 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
599 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
600 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
601 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
602 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
603 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
604 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
605 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
606 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
607 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
608 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
609 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
610 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
611 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
612 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
613 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
614 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
615 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
616 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
617 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
618 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
619 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
620 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
632 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
633 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
634 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
635 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
636 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
637 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
638 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
639 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
640 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
641 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
642 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
643 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
644 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
645 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
646 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
647 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
648 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
649 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
650 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
651 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
652 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
653 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
654 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
655 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
656 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
657 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
658 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
659 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
660 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
661 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
662 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
663 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
664 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
665 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
666 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
667 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
668 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
669 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
670 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
671 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
672 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
673 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
674 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
675 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
676 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
677 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
678 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
679 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
680 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
681 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
682 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
683 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
684 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
685 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
686 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
687 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
688 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
689 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
690 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
691 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
692 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
693 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
694 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
695 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
696 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
697 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
698 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
699 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
700 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
701 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
702 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
703 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
704 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
705 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
706 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
707 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
708 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
709 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
710 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
711 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
712 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
713 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
714 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
715 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
716 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
717 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
718 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
719 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
720 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
721 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
722 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
723 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
724 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
725 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
726 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
727 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
728 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
729 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
730 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
731 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
732 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
733 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
734 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
735 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
736 { 0, }, /* End of list */
738 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
740 static void lpc_ich_restore_config_space(struct pci_dev *dev)
742 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
744 if (priv->acpi.save >= 0) {
745 pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save);
746 priv->acpi.save = -1;
749 if (priv->gpio.save >= 0) {
750 pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save);
751 priv->gpio.save = -1;
755 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
757 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
760 pci_read_config_byte(dev, priv->acpi.ctrl, ®_save);
761 pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10);
762 priv->acpi.save = reg_save;
765 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
767 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
770 pci_read_config_byte(dev, priv->gpio.ctrl, ®_save);
771 pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10);
772 priv->gpio.save = reg_save;
775 static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
777 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
779 cell->platform_data = &lpc_chipset_info[priv->chipset];
780 cell->pdata_size = sizeof(struct lpc_ich_info);
784 * We don't check for resource conflict globally. There are 2 or 3 independent
785 * GPIO groups and it's enough to have access to one of these to instantiate
788 static int lpc_ich_check_conflict_gpio(struct resource *res)
793 if (resource_size(res) >= 0x50 &&
794 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
797 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
800 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
804 return use_gpio ? use_gpio : ret;
807 static int lpc_ich_init_gpio(struct pci_dev *dev)
809 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
813 bool acpi_conflict = false;
814 struct resource *res;
816 /* Setup power management base register */
817 pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
818 base_addr = base_addr_cfg & 0x0000ff80;
820 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
821 lpc_ich_cells[LPC_GPIO].num_resources--;
825 res = &gpio_ich_res[ICH_RES_GPE0];
826 res->start = base_addr + ACPIBASE_GPE_OFF;
827 res->end = base_addr + ACPIBASE_GPE_END;
828 ret = acpi_check_resource_conflict(res);
831 * This isn't fatal for the GPIO, but we have to make sure that
832 * the platform_device subsystem doesn't see this resource
833 * or it will register an invalid region.
835 lpc_ich_cells[LPC_GPIO].num_resources--;
836 acpi_conflict = true;
838 lpc_ich_enable_acpi_space(dev);
842 /* Setup GPIO base register */
843 pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg);
844 base_addr = base_addr_cfg & 0x0000ff80;
846 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
851 /* Older devices provide fewer GPIO and have a smaller resource size. */
852 res = &gpio_ich_res[ICH_RES_GPIO];
853 res->start = base_addr;
854 switch (lpc_chipset_info[priv->chipset].gpio_version) {
856 case ICH_V10CORP_GPIO:
857 res->end = res->start + 128 - 1;
860 res->end = res->start + 64 - 1;
864 ret = lpc_ich_check_conflict_gpio(res);
866 /* this isn't necessarily fatal for the GPIO */
867 acpi_conflict = true;
870 lpc_chipset_info[priv->chipset].use_gpio = ret;
871 lpc_ich_enable_gpio_space(dev);
873 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
874 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
879 pr_warn("Resource conflict(s) found affecting %s\n",
880 lpc_ich_cells[LPC_GPIO].name);
884 static int lpc_ich_init_wdt(struct pci_dev *dev)
886 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
890 struct resource *res;
892 /* Setup power management base register */
893 pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg);
894 base_addr = base_addr_cfg & 0x0000ff80;
896 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
901 res = wdt_io_res(ICH_RES_IO_TCO);
902 res->start = base_addr + ACPIBASE_TCO_OFF;
903 res->end = base_addr + ACPIBASE_TCO_END;
905 res = wdt_io_res(ICH_RES_IO_SMI);
906 res->start = base_addr + ACPIBASE_SMI_OFF;
907 res->end = base_addr + ACPIBASE_SMI_END;
909 lpc_ich_enable_acpi_space(dev);
912 * Get the Memory-Mapped GCS register. To get access to it
913 * we have to read RCBA from PCI Config space 0xf0 and use
914 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
916 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
917 /* Don't register iomem for TCO ver 1 */
918 lpc_ich_cells[LPC_WDT].num_resources--;
920 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
921 base_addr = base_addr_cfg & 0xffffc000;
922 if (!(base_addr_cfg & 1)) {
923 dev_notice(&dev->dev, "RCBA is disabled by "
924 "hardware/BIOS, device disabled\n");
928 res = wdt_mem_res(ICH_RES_MEM_GCS);
929 res->start = base_addr + ACPIBASE_GCS_OFF;
930 res->end = base_addr + ACPIBASE_GCS_END;
933 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
934 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
941 static int lpc_ich_probe(struct pci_dev *dev,
942 const struct pci_device_id *id)
944 struct lpc_ich_priv *priv;
946 bool cell_added = false;
948 priv = devm_kzalloc(&dev->dev,
949 sizeof(struct lpc_ich_priv), GFP_KERNEL);
953 priv->chipset = id->driver_data;
954 priv->acpi.save = -1;
955 priv->acpi.base = ACPIBASE;
956 priv->acpi.ctrl = ACPICTRL;
958 priv->gpio.save = -1;
959 if (priv->chipset <= LPC_ICH5) {
960 priv->gpio.base = GPIOBASE_ICH0;
961 priv->gpio.ctrl = GPIOCTRL_ICH0;
963 priv->gpio.base = GPIOBASE_ICH6;
964 priv->gpio.ctrl = GPIOCTRL_ICH6;
967 pci_set_drvdata(dev, priv);
969 ret = lpc_ich_init_wdt(dev);
973 ret = lpc_ich_init_gpio(dev);
978 * We only care if at least one or none of the cells registered
982 dev_warn(&dev->dev, "No MFD cells added\n");
983 lpc_ich_restore_config_space(dev);
990 static void lpc_ich_remove(struct pci_dev *dev)
992 mfd_remove_devices(&dev->dev);
993 lpc_ich_restore_config_space(dev);
996 static struct pci_driver lpc_ich_driver = {
998 .id_table = lpc_ich_ids,
999 .probe = lpc_ich_probe,
1000 .remove = lpc_ich_remove,
1003 module_pci_driver(lpc_ich_driver);
1005 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1006 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1007 MODULE_LICENSE("GPL");