1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/rtsx_pci.h>
28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
32 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38 u8 driving_3v3[4][3] = {
44 u8 driving_1v8[4][3] = {
50 u8 (*driving)[3], drive_sel;
52 if (voltage == OUTPUT_3V3) {
53 driving = driving_3v3;
54 drive_sel = pcr->sd30_drive_sel_3v3;
56 driving = driving_1v8;
57 drive_sel = pcr->sd30_drive_sel_1v8;
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
61 0xFF, driving[drive_sel][0]);
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
63 0xFF, driving[drive_sel][1]);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
65 0xFF, driving[drive_sel][2]);
68 static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
72 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
73 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75 if (!rtsx_vendor_setting_valid(reg))
78 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
80 pcr->card_drive_sel &= 0x3F;
81 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
84 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
85 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 if (rtsx_reg_check_reverse_socket(reg))
87 pcr->flags |= PCR_REVERSE_SOCKET;
90 static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
92 /* Set relink_time to 0 */
93 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97 if (pm_state == HOST_ENTER_S3)
98 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
100 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
103 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
105 rtsx_pci_init_cmd(pcr);
107 /* Configure GPIO as output */
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
109 /* Reset ASPM state to default value */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
111 /* Switch LDO3318 source from DV33 to card_3v3 */
112 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
114 /* LED shine disabled, set initial shine cycle period */
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
116 /* Configure driving */
117 rts5249_fill_driving(pcr, OUTPUT_3V3);
118 if (pcr->flags & PCR_REVERSE_SOCKET)
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
123 return rtsx_pci_send_cmd(pcr, 100);
126 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
130 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
134 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
135 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
136 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
137 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
138 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
145 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
146 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
147 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
151 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
152 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
153 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
154 PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
158 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
159 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
160 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
161 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
165 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
166 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
167 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
168 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
169 PHY_FLD4_BER_CHK_EN);
172 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
173 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
176 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
177 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
180 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
181 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
186 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
187 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
188 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
189 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
192 static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
194 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
197 static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
199 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
202 static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
204 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
207 static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
209 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
212 static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
216 rtsx_pci_init_cmd(pcr);
217 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
218 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
219 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
220 LDO3318_PWR_MASK, 0x02);
221 err = rtsx_pci_send_cmd(pcr, 100);
227 rtsx_pci_init_cmd(pcr);
228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
229 SD_POWER_MASK, SD_VCC_POWER_ON);
230 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
231 LDO3318_PWR_MASK, 0x06);
232 err = rtsx_pci_send_cmd(pcr, 100);
239 static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
241 rtsx_pci_init_cmd(pcr);
242 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
243 SD_POWER_MASK, SD_POWER_OFF);
244 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
245 LDO3318_PWR_MASK, 0x00);
246 return rtsx_pci_send_cmd(pcr, 100);
249 static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
253 if (voltage == OUTPUT_3V3) {
254 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
257 } else if (voltage == OUTPUT_1V8) {
258 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
261 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
269 rtsx_pci_init_cmd(pcr);
270 rts5249_fill_driving(pcr, voltage);
271 return rtsx_pci_send_cmd(pcr, 100);
274 static const struct pcr_ops rts5249_pcr_ops = {
275 .fetch_vendor_settings = rts5249_fetch_vendor_settings,
276 .extra_init_hw = rts5249_extra_init_hw,
277 .optimize_phy = rts5249_optimize_phy,
278 .turn_on_led = rts5249_turn_on_led,
279 .turn_off_led = rts5249_turn_off_led,
280 .enable_auto_blink = rts5249_enable_auto_blink,
281 .disable_auto_blink = rts5249_disable_auto_blink,
282 .card_power_on = rts5249_card_power_on,
283 .card_power_off = rts5249_card_power_off,
284 .switch_output_voltage = rts5249_switch_output_voltage,
285 .force_power_down = rts5249_force_power_down,
288 /* SD Pull Control Enable:
289 * SD_DAT[3:0] ==> pull up
293 * SD_CLK ==> pull down
295 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
296 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
297 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
298 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
299 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
303 /* SD Pull Control Disable:
304 * SD_DAT[3:0] ==> pull down
306 * SD_WP ==> pull down
307 * SD_CMD ==> pull down
308 * SD_CLK ==> pull down
310 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
311 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
312 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
313 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
314 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
318 /* MS Pull Control Enable:
320 * others ==> pull down
322 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
323 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
324 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
325 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
329 /* MS Pull Control Disable:
331 * others ==> pull down
333 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
334 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
335 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
336 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
340 void rts5249_init_params(struct rtsx_pcr *pcr)
342 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
344 pcr->ops = &rts5249_pcr_ops;
347 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
348 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
349 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
350 pcr->aspm_en = ASPM_L1_EN;
351 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
352 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
354 pcr->ic_version = rts5249_get_ic_version(pcr);
355 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
356 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
357 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
358 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;