drivers/mfd/rts5249.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/delay.h>
  24 #include <linux/mfd/rtsx_pci.h>
  25
  26 #include "rtsx_pcr.h"
  27
  28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  29 {
  30         u8 val;
  31
  32         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  33         return val & 0x0F;
  34 }
  35
  36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  37 {
  38         u8 driving_3v3[4][3] = {
  39                 {0x11, 0x11, 0x11},
  40                 {0x55, 0x55, 0x5C},
  41                 {0x99, 0x99, 0x92},
  42                 {0x99, 0x99, 0x92},
  43         };
  44         u8 driving_1v8[4][3] = {
  45                 {0x3C, 0x3C, 0x3C},
  46                 {0xB3, 0xB3, 0xB3},
  47                 {0xFE, 0xFE, 0xFE},
  48                 {0xC4, 0xC4, 0xC4},
  49         };
  50         u8 (*driving)[3], drive_sel;
  51
  52         if (voltage == OUTPUT_3V3) {
  53                 driving = driving_3v3;
  54                 drive_sel = pcr->sd30_drive_sel_3v3;
  55         } else {
  56                 driving = driving_1v8;
  57                 drive_sel = pcr->sd30_drive_sel_1v8;
  58         }
  59
  60         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  61                         0xFF, driving[drive_sel][0]);
  62         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  63                         0xFF, driving[drive_sel][1]);
  64         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  65                         0xFF, driving[drive_sel][2]);
  66 }
  67
  68 static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
  69 {
  70         u32 reg;
  71
  72         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  73         dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  74
  75         if (!rtsx_vendor_setting_valid(reg))
  76                 return;
  77
  78         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  79         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  80         pcr->card_drive_sel &= 0x3F;
  81         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  82
  83         rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  84         dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  85         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  86         if (rtsx_reg_check_reverse_socket(reg))
  87                 pcr->flags |= PCR_REVERSE_SOCKET;
  88 }
  89
  90 static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  91 {
  92         /* Set relink_time to 0 */
  93         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  94         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  95         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  96
  97         if (pm_state == HOST_ENTER_S3)
  98                 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
  99
 100         rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
 101 }
 102
 103 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 104 {
 105         rtsx_pci_init_cmd(pcr);
 106
 107         /* Configure GPIO as output */
 108         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 109         /* Reset ASPM state to default value */
 110         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 111         /* Switch LDO3318 source from DV33 to card_3v3 */
 112         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 113         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 114         /* LED shine disabled, set initial shine cycle period */
 115         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 116         /* Configure driving */
 117         rts5249_fill_driving(pcr, OUTPUT_3V3);
 118         if (pcr->flags & PCR_REVERSE_SOCKET)
 119                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 120         else
 121                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 122         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
 123
 124         return rtsx_pci_send_cmd(pcr, 100);
 125 }
 126
 127 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 128 {
 129         int err;
 130
 131         err = rtsx_gops_pm_reset(pcr);
 132         if (err < 0)
 133                 return err;
 134
 135         err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV,
 136                         PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED |
 137                         PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN |
 138                         PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 |
 139                         PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR);
 140         if (err < 0)
 141                 return err;
 142
 143         msleep(1);
 144
 145         err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
 146                         PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
 147                         PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 148         if (err < 0)
 149                 return err;
 150         err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
 151                         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
 152                         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
 153                         PHY_PCR_RSSI_EN);
 154         if (err < 0)
 155                 return err;
 156         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 157                         PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
 158                         PHY_RCR2_CDR_CP_10 | PHY_RCR2_CDR_SR_2 |
 159                         PHY_RCR2_FREQSEL_12 | PHY_RCR2_CPADJEN |
 160                         PHY_RCR2_CDR_SC_8 | PHY_RCR2_CALIB_LATE);
 161         if (err < 0)
 162                 return err;
 163         err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
 164                         PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
 165                         PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
 166                         PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
 167                         PHY_FLD4_BER_CHK_EN);
 168         if (err < 0)
 169                 return err;
 170         err = rtsx_pci_write_phy_register(pcr, PHY_RDR, PHY_RDR_RXDSEL_1_9);
 171         if (err < 0)
 172                 return err;
 173         err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
 174                         PHY_RCR1_ADP_TIME | PHY_RCR1_VCO_COARSE);
 175         if (err < 0)
 176                 return err;
 177         err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
 178                         PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
 179                         PHY_FLD3_RXDELINK);
 180         if (err < 0)
 181                 return err;
 182         return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
 183                         PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
 184                         PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
 185                         PHY_TUNE_TUNED12);
 186 }
 187
 188 static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
 189 {
 190         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 191 }
 192
 193 static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
 194 {
 195         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 196 }
 197
 198 static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
 199 {
 200         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 201 }
 202
 203 static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
 204 {
 205         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 206 }
 207
 208 static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
 209 {
 210         int err;
 211
 212         rtsx_pci_init_cmd(pcr);
 213         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 214                         SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
 215         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 216                         LDO3318_PWR_MASK, 0x02);
 217         err = rtsx_pci_send_cmd(pcr, 100);
 218         if (err < 0)
 219                 return err;
 220
 221         msleep(5);
 222
 223         rtsx_pci_init_cmd(pcr);
 224         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 225                         SD_POWER_MASK, SD_VCC_POWER_ON);
 226         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 227                         LDO3318_PWR_MASK, 0x06);
 228         err = rtsx_pci_send_cmd(pcr, 100);
 229         if (err < 0)
 230                 return err;
 231
 232         return 0;
 233 }
 234
 235 static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
 236 {
 237         rtsx_pci_init_cmd(pcr);
 238         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 239                         SD_POWER_MASK, SD_POWER_OFF);
 240         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 241                         LDO3318_PWR_MASK, 0x00);
 242         return rtsx_pci_send_cmd(pcr, 100);
 243 }
 244
 245 static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 246 {
 247         int err;
 248
 249         if (voltage == OUTPUT_3V3) {
 250                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
 251                 if (err < 0)
 252                         return err;
 253         } else if (voltage == OUTPUT_1V8) {
 254                 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
 255                 if (err < 0)
 256                         return err;
 257                 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
 258                 if (err < 0)
 259                         return err;
 260         } else {
 261                 return -EINVAL;
 262         }
 263
 264         /* set pad drive */
 265         rtsx_pci_init_cmd(pcr);
 266         rts5249_fill_driving(pcr, voltage);
 267         return rtsx_pci_send_cmd(pcr, 100);
 268 }
 269
 270 static const struct pcr_ops rts5249_pcr_ops = {
 271         .fetch_vendor_settings = rts5249_fetch_vendor_settings,
 272         .extra_init_hw = rts5249_extra_init_hw,
 273         .optimize_phy = rts5249_optimize_phy,
 274         .turn_on_led = rts5249_turn_on_led,
 275         .turn_off_led = rts5249_turn_off_led,
 276         .enable_auto_blink = rts5249_enable_auto_blink,
 277         .disable_auto_blink = rts5249_disable_auto_blink,
 278         .card_power_on = rts5249_card_power_on,
 279         .card_power_off = rts5249_card_power_off,
 280         .switch_output_voltage = rts5249_switch_output_voltage,
 281         .force_power_down = rts5249_force_power_down,
 282 };
 283
 284 /* SD Pull Control Enable:
 285  *     SD_DAT[3:0] ==> pull up
 286  *     SD_CD       ==> pull up
 287  *     SD_WP       ==> pull up
 288  *     SD_CMD      ==> pull up
 289  *     SD_CLK      ==> pull down
 290  */
 291 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
 292         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 293         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 294         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 295         RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
 296         0,
 297 };
 298
 299 /* SD Pull Control Disable:
 300  *     SD_DAT[3:0] ==> pull down
 301  *     SD_CD       ==> pull up
 302  *     SD_WP       ==> pull down
 303  *     SD_CMD      ==> pull down
 304  *     SD_CLK      ==> pull down
 305  */
 306 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
 307         RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
 308         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 309         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 310         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 311         0,
 312 };
 313
 314 /* MS Pull Control Enable:
 315  *     MS CD       ==> pull up
 316  *     others      ==> pull down
 317  */
 318 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
 319         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 320         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 321         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 322         0,
 323 };
 324
 325 /* MS Pull Control Disable:
 326  *     MS CD       ==> pull up
 327  *     others      ==> pull down
 328  */
 329 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
 330         RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
 331         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 332         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 333         0,
 334 };
 335
 336 void rts5249_init_params(struct rtsx_pcr *pcr)
 337 {
 338         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 339         pcr->num_slots = 2;
 340         pcr->ops = &rts5249_pcr_ops;
 341
 342         pcr->flags = 0;
 343         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 344         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
 345         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 346         pcr->aspm_en = ASPM_L1_EN;
 347         pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
 348         pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
 349
 350         pcr->ic_version = rts5249_get_ic_version(pcr);
 351         pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
 352         pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
 353         pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 354         pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 355 }