1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/mfd/rtsx_pci.h>
28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
32 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38 u8 driving_3v3[4][3] = {
44 u8 driving_1v8[4][3] = {
50 u8 (*driving)[3], drive_sel;
52 if (voltage == OUTPUT_3V3) {
53 driving = driving_3v3;
54 drive_sel = pcr->sd30_drive_sel_3v3;
56 driving = driving_1v8;
57 drive_sel = pcr->sd30_drive_sel_1v8;
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
61 0xFF, driving[drive_sel][0]);
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
63 0xFF, driving[drive_sel][1]);
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
65 0xFF, driving[drive_sel][2]);
68 static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
72 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
73 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75 if (!rtsx_vendor_setting_valid(reg))
78 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
80 pcr->card_drive_sel &= 0x3F;
81 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
84 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
85 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 if (rtsx_reg_check_reverse_socket(reg))
87 pcr->flags |= PCR_REVERSE_SOCKET;
90 static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
92 /* Set relink_time to 0 */
93 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97 if (pm_state == HOST_ENTER_S3)
98 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
100 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
103 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
105 rtsx_pci_init_cmd(pcr);
107 /* Configure GPIO as output */
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
109 /* Reset ASPM state to default value */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
111 /* Switch LDO3318 source from DV33 to card_3v3 */
112 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
114 /* LED shine disabled, set initial shine cycle period */
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
116 /* Configure driving */
117 rts5249_fill_driving(pcr, OUTPUT_3V3);
118 if (pcr->flags & PCR_REVERSE_SOCKET)
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
124 return rtsx_pci_send_cmd(pcr, 100);
127 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
131 err = rtsx_gops_pm_reset(pcr);
135 err = rtsx_pci_write_phy_register(pcr, PHY_REV,
136 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
137 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
138 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
139 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
146 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
147 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
148 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
152 err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
153 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
154 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
155 PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
159 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
160 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
161 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
162 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
166 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
167 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
168 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
169 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
170 PHY_FLD4_BER_CHK_EN);
173 err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
174 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
177 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
178 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
181 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
182 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
187 return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
188 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
189 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
190 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
193 static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
195 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
198 static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
200 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
203 static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
205 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
208 static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
210 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
213 static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
217 rtsx_pci_init_cmd(pcr);
218 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
219 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
221 LDO3318_PWR_MASK, 0x02);
222 err = rtsx_pci_send_cmd(pcr, 100);
228 rtsx_pci_init_cmd(pcr);
229 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
230 SD_POWER_MASK, SD_VCC_POWER_ON);
231 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
232 LDO3318_PWR_MASK, 0x06);
233 err = rtsx_pci_send_cmd(pcr, 100);
240 static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
242 rtsx_pci_init_cmd(pcr);
243 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
244 SD_POWER_MASK, SD_POWER_OFF);
245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
246 LDO3318_PWR_MASK, 0x00);
247 return rtsx_pci_send_cmd(pcr, 100);
250 static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
254 if (voltage == OUTPUT_3V3) {
255 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
258 } else if (voltage == OUTPUT_1V8) {
259 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
262 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
270 rtsx_pci_init_cmd(pcr);
271 rts5249_fill_driving(pcr, voltage);
272 return rtsx_pci_send_cmd(pcr, 100);
275 static const struct pcr_ops rts5249_pcr_ops = {
276 .fetch_vendor_settings = rts5249_fetch_vendor_settings,
277 .extra_init_hw = rts5249_extra_init_hw,
278 .optimize_phy = rts5249_optimize_phy,
279 .turn_on_led = rts5249_turn_on_led,
280 .turn_off_led = rts5249_turn_off_led,
281 .enable_auto_blink = rts5249_enable_auto_blink,
282 .disable_auto_blink = rts5249_disable_auto_blink,
283 .card_power_on = rts5249_card_power_on,
284 .card_power_off = rts5249_card_power_off,
285 .switch_output_voltage = rts5249_switch_output_voltage,
286 .force_power_down = rts5249_force_power_down,
289 /* SD Pull Control Enable:
290 * SD_DAT[3:0] ==> pull up
294 * SD_CLK ==> pull down
296 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
297 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
298 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
299 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
300 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
304 /* SD Pull Control Disable:
305 * SD_DAT[3:0] ==> pull down
307 * SD_WP ==> pull down
308 * SD_CMD ==> pull down
309 * SD_CLK ==> pull down
311 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
312 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
313 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
314 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
315 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
319 /* MS Pull Control Enable:
321 * others ==> pull down
323 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
324 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
325 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
326 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
330 /* MS Pull Control Disable:
332 * others ==> pull down
334 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
335 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
336 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
337 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
341 void rts5249_init_params(struct rtsx_pcr *pcr)
343 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
345 pcr->ops = &rts5249_pcr_ops;
348 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
349 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
350 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
351 pcr->aspm_en = ASPM_L1_EN;
352 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
353 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
355 pcr->ic_version = rts5249_get_ic_version(pcr);
356 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
357 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
358 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
359 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;