1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
37 static bool msi_en = true;
38 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(msi_en, "Enable MSI");
41 static DEFINE_IDR(rtsx_pci_idr);
42 static DEFINE_SPINLOCK(rtsx_pci_lock);
44 static struct mfd_cell rtsx_pcr_cells[] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
49 .name = DRV_NAME_RTSX_PCI_MS,
53 static const struct pci_device_id rtsx_pci_ids[] = {
54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
61 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
62 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
66 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
68 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
70 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
74 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
76 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
80 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
82 /* If pci device removed, don't queue idle work any more */
86 if (pcr->state != PDEV_STAT_RUN) {
87 pcr->state = PDEV_STAT_RUN;
88 if (pcr->ops->enable_auto_blink)
89 pcr->ops->enable_auto_blink(pcr);
92 rtsx_pci_disable_aspm(pcr);
95 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
97 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
99 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
102 u32 val = HAIMR_WRITE_START;
104 val |= (u32)(addr & 0x3FFF) << 16;
105 val |= (u32)mask << 8;
108 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
110 for (i = 0; i < MAX_RW_REG_CNT; i++) {
111 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
112 if ((val & HAIMR_TRANS_END) == 0) {
121 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
123 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
125 u32 val = HAIMR_READ_START;
128 val |= (u32)(addr & 0x3FFF) << 16;
129 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
131 for (i = 0; i < MAX_RW_REG_CNT; i++) {
132 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
133 if ((val & HAIMR_TRANS_END) == 0)
137 if (i >= MAX_RW_REG_CNT)
141 *data = (u8)(val & 0xFF);
145 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
147 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
149 int err, i, finished = 0;
152 rtsx_pci_init_cmd(pcr);
154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
159 err = rtsx_pci_send_cmd(pcr, 100);
163 for (i = 0; i < 100000; i++) {
164 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
180 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
182 if (pcr->ops->write_phy)
183 return pcr->ops->write_phy(pcr, addr, val);
185 return __rtsx_pci_write_phy_register(pcr, addr, val);
187 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
189 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
191 int err, i, finished = 0;
195 rtsx_pci_init_cmd(pcr);
197 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
200 err = rtsx_pci_send_cmd(pcr, 100);
204 for (i = 0; i < 100000; i++) {
205 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
218 rtsx_pci_init_cmd(pcr);
220 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
221 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
223 err = rtsx_pci_send_cmd(pcr, 100);
227 ptr = rtsx_pci_get_cmd_data(pcr);
228 data = ((u16)ptr[1] << 8) | ptr[0];
236 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
238 if (pcr->ops->read_phy)
239 return pcr->ops->read_phy(pcr, addr, val);
241 return __rtsx_pci_read_phy_register(pcr, addr, val);
243 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
245 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
247 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
248 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
250 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
251 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
253 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
255 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
256 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
260 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
262 val |= (u32)(cmd_type & 0x03) << 30;
263 val |= (u32)(reg_addr & 0x3FFF) << 16;
264 val |= (u32)mask << 8;
267 spin_lock_irqsave(&pcr->lock, flags);
269 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
270 put_unaligned_le32(val, ptr);
274 spin_unlock_irqrestore(&pcr->lock, flags);
276 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
278 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
282 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
284 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
285 /* Hardware Auto Response */
287 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
289 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
291 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
293 struct completion trans_done;
299 spin_lock_irqsave(&pcr->lock, flags);
301 /* set up data structures for the wakeup system */
302 pcr->done = &trans_done;
303 pcr->trans_result = TRANS_NOT_READY;
304 init_completion(&trans_done);
306 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
308 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
309 /* Hardware Auto Response */
311 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
313 spin_unlock_irqrestore(&pcr->lock, flags);
315 /* Wait for TRANS_OK_INT */
316 timeleft = wait_for_completion_interruptible_timeout(
317 &trans_done, msecs_to_jiffies(timeout));
319 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
321 goto finish_send_cmd;
324 spin_lock_irqsave(&pcr->lock, flags);
325 if (pcr->trans_result == TRANS_RESULT_FAIL)
327 else if (pcr->trans_result == TRANS_RESULT_OK)
329 else if (pcr->trans_result == TRANS_NO_DEVICE)
331 spin_unlock_irqrestore(&pcr->lock, flags);
334 spin_lock_irqsave(&pcr->lock, flags);
336 spin_unlock_irqrestore(&pcr->lock, flags);
338 if ((err < 0) && (err != -ENODEV))
339 rtsx_pci_stop_cmd(pcr);
342 complete(pcr->finish_me);
346 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
348 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
349 dma_addr_t addr, unsigned int len, int end)
351 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
353 u8 option = SG_VALID | SG_TRANS_DATA;
355 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
359 val = ((u64)addr << 32) | ((u64)len << 12) | option;
361 put_unaligned_le64(val, ptr);
365 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
366 int num_sg, bool read, int timeout)
370 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
371 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
374 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
376 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
378 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
382 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
384 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
385 int num_sg, bool read)
387 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
392 if ((sglist == NULL) || (num_sg <= 0))
395 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
397 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
399 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
400 int num_sg, bool read)
402 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
404 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
406 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
408 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
409 int count, bool read, int timeout)
411 struct completion trans_done;
412 struct scatterlist *sg;
419 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
424 if ((sglist == NULL) || (count < 1))
427 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
429 for_each_sg(sglist, sg, count, i) {
430 addr = sg_dma_address(sg);
431 len = sg_dma_len(sg);
432 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
435 spin_lock_irqsave(&pcr->lock, flags);
437 pcr->done = &trans_done;
438 pcr->trans_result = TRANS_NOT_READY;
439 init_completion(&trans_done);
440 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
441 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
443 spin_unlock_irqrestore(&pcr->lock, flags);
445 timeleft = wait_for_completion_interruptible_timeout(
446 &trans_done, msecs_to_jiffies(timeout));
448 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
453 spin_lock_irqsave(&pcr->lock, flags);
454 if (pcr->trans_result == TRANS_RESULT_FAIL)
456 else if (pcr->trans_result == TRANS_NO_DEVICE)
458 spin_unlock_irqrestore(&pcr->lock, flags);
461 spin_lock_irqsave(&pcr->lock, flags);
463 spin_unlock_irqrestore(&pcr->lock, flags);
465 if ((err < 0) && (err != -ENODEV))
466 rtsx_pci_stop_cmd(pcr);
469 complete(pcr->finish_me);
473 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
475 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
487 for (i = 0; i < buf_len / 256; i++) {
488 rtsx_pci_init_cmd(pcr);
490 for (j = 0; j < 256; j++)
491 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
493 err = rtsx_pci_send_cmd(pcr, 250);
497 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
502 rtsx_pci_init_cmd(pcr);
504 for (j = 0; j < buf_len % 256; j++)
505 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
507 err = rtsx_pci_send_cmd(pcr, 250);
512 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
516 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
518 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
530 for (i = 0; i < buf_len / 256; i++) {
531 rtsx_pci_init_cmd(pcr);
533 for (j = 0; j < 256; j++) {
534 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
539 err = rtsx_pci_send_cmd(pcr, 250);
545 rtsx_pci_init_cmd(pcr);
547 for (j = 0; j < buf_len % 256; j++) {
548 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
553 err = rtsx_pci_send_cmd(pcr, 250);
560 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
562 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
566 rtsx_pci_init_cmd(pcr);
568 while (*tbl & 0xFFFF0000) {
569 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
570 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
574 err = rtsx_pci_send_cmd(pcr, 100);
581 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
585 if (card == RTSX_SD_CARD)
586 tbl = pcr->sd_pull_ctl_enable_tbl;
587 else if (card == RTSX_MS_CARD)
588 tbl = pcr->ms_pull_ctl_enable_tbl;
592 return rtsx_pci_set_pull_ctl(pcr, tbl);
594 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
596 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
600 if (card == RTSX_SD_CARD)
601 tbl = pcr->sd_pull_ctl_disable_tbl;
602 else if (card == RTSX_MS_CARD)
603 tbl = pcr->ms_pull_ctl_disable_tbl;
608 return rtsx_pci_set_pull_ctl(pcr, tbl);
610 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
612 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
614 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
616 if (pcr->num_slots > 1)
617 pcr->bier |= MS_INT_EN;
619 /* Enable Bus Interrupt */
620 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
622 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
625 static inline u8 double_ssc_depth(u8 depth)
627 return ((depth > 1) ? (depth - 1) : depth);
630 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
632 if (div > CLK_DIV_1) {
633 if (ssc_depth > (div - 1))
634 ssc_depth -= (div - 1);
636 ssc_depth = SSC_DEPTH_4M;
642 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
643 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
646 u8 n, clk_divider, mcu_cnt, div;
648 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
649 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
650 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
651 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
652 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
656 /* We use 250k(around) here, in initial stage */
657 clk_divider = SD_CLK_DIVIDE_128;
658 card_clock = 30000000;
660 clk_divider = SD_CLK_DIVIDE_0;
662 err = rtsx_pci_write_register(pcr, SD_CFG1,
663 SD_CLK_DIVIDE_MASK, clk_divider);
667 card_clock /= 1000000;
668 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
671 if (!initial_mode && double_clk)
672 clk = card_clock * 2;
673 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
674 clk, pcr->cur_clock);
676 if (clk == pcr->cur_clock)
679 if (pcr->ops->conv_clk_and_div_n)
680 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
683 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
686 mcu_cnt = (u8)(125/clk + 3);
690 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
692 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
693 if (pcr->ops->conv_clk_and_div_n) {
694 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
696 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
703 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
705 ssc_depth = depth[ssc_depth];
707 ssc_depth = double_ssc_depth(ssc_depth);
709 ssc_depth = revise_ssc_depth(ssc_depth, div);
710 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
712 rtsx_pci_init_cmd(pcr);
713 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
714 CLK_LOW_FREQ, CLK_LOW_FREQ);
715 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
716 0xFF, (div << 4) | mcu_cnt);
717 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
718 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
719 SSC_DEPTH_MASK, ssc_depth);
720 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
723 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
725 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
726 PHASE_NOT_RESET, PHASE_NOT_RESET);
729 err = rtsx_pci_send_cmd(pcr, 2000);
733 /* Wait SSC clock stable */
735 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
739 pcr->cur_clock = clk;
742 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
744 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
746 if (pcr->ops->card_power_on)
747 return pcr->ops->card_power_on(pcr, card);
751 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
753 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
755 if (pcr->ops->card_power_off)
756 return pcr->ops->card_power_off(pcr, card);
760 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
762 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
764 unsigned int cd_mask[] = {
765 [RTSX_SD_CARD] = SD_EXIST,
766 [RTSX_MS_CARD] = MS_EXIST
769 if (!(pcr->flags & PCR_MS_PMOS)) {
770 /* When using single PMOS, accessing card is not permitted
771 * if the existing card is not the designated one.
773 if (pcr->card_exist & (~cd_mask[card]))
779 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
781 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
783 if (pcr->ops->switch_output_voltage)
784 return pcr->ops->switch_output_voltage(pcr, voltage);
788 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
790 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
794 val = rtsx_pci_readl(pcr, RTSX_BIPR);
795 if (pcr->ops->cd_deglitch)
796 val = pcr->ops->cd_deglitch(pcr);
800 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
802 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
804 struct completion finish;
806 pcr->finish_me = &finish;
807 init_completion(&finish);
812 if (!pcr->remove_pci)
813 rtsx_pci_stop_cmd(pcr);
815 wait_for_completion_interruptible_timeout(&finish,
816 msecs_to_jiffies(2));
817 pcr->finish_me = NULL;
819 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
821 static void rtsx_pci_card_detect(struct work_struct *work)
823 struct delayed_work *dwork;
824 struct rtsx_pcr *pcr;
826 unsigned int card_detect = 0, card_inserted, card_removed;
829 dwork = to_delayed_work(work);
830 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
832 pcr_dbg(pcr, "--> %s\n", __func__);
834 mutex_lock(&pcr->pcr_mutex);
835 spin_lock_irqsave(&pcr->lock, flags);
837 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
838 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
840 irq_status &= CARD_EXIST;
841 card_inserted = pcr->card_inserted & irq_status;
842 card_removed = pcr->card_removed;
843 pcr->card_inserted = 0;
844 pcr->card_removed = 0;
846 spin_unlock_irqrestore(&pcr->lock, flags);
848 if (card_inserted || card_removed) {
849 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
850 card_inserted, card_removed);
852 if (pcr->ops->cd_deglitch)
853 card_inserted = pcr->ops->cd_deglitch(pcr);
855 card_detect = card_inserted | card_removed;
857 pcr->card_exist |= card_inserted;
858 pcr->card_exist &= ~card_removed;
861 mutex_unlock(&pcr->pcr_mutex);
863 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
864 pcr->slots[RTSX_SD_CARD].card_event(
865 pcr->slots[RTSX_SD_CARD].p_dev);
866 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
867 pcr->slots[RTSX_MS_CARD].card_event(
868 pcr->slots[RTSX_MS_CARD].p_dev);
871 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
873 struct rtsx_pcr *pcr = dev_id;
879 spin_lock(&pcr->lock);
881 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
882 /* Clear interrupt flag */
883 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
884 if ((int_reg & pcr->bier) == 0) {
885 spin_unlock(&pcr->lock);
888 if (int_reg == 0xFFFFFFFF) {
889 spin_unlock(&pcr->lock);
893 int_reg &= (pcr->bier | 0x7FFFFF);
895 if (int_reg & SD_INT) {
896 if (int_reg & SD_EXIST) {
897 pcr->card_inserted |= SD_EXIST;
899 pcr->card_removed |= SD_EXIST;
900 pcr->card_inserted &= ~SD_EXIST;
904 if (int_reg & MS_INT) {
905 if (int_reg & MS_EXIST) {
906 pcr->card_inserted |= MS_EXIST;
908 pcr->card_removed |= MS_EXIST;
909 pcr->card_inserted &= ~MS_EXIST;
913 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
914 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
915 pcr->trans_result = TRANS_RESULT_FAIL;
918 } else if (int_reg & TRANS_OK_INT) {
919 pcr->trans_result = TRANS_RESULT_OK;
925 if (pcr->card_inserted || pcr->card_removed)
926 schedule_delayed_work(&pcr->carddet_work,
927 msecs_to_jiffies(200));
929 spin_unlock(&pcr->lock);
933 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
935 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
936 __func__, pcr->msi_en, pcr->pci->irq);
938 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
939 pcr->msi_en ? 0 : IRQF_SHARED,
940 DRV_NAME_RTSX_PCI, pcr)) {
941 dev_err(&(pcr->pci->dev),
942 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
947 pcr->irq = pcr->pci->irq;
948 pci_intx(pcr->pci, !pcr->msi_en);
953 static void rtsx_pci_idle_work(struct work_struct *work)
955 struct delayed_work *dwork = to_delayed_work(work);
956 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
958 pcr_dbg(pcr, "--> %s\n", __func__);
960 mutex_lock(&pcr->pcr_mutex);
962 pcr->state = PDEV_STAT_IDLE;
964 if (pcr->ops->disable_auto_blink)
965 pcr->ops->disable_auto_blink(pcr);
966 if (pcr->ops->turn_off_led)
967 pcr->ops->turn_off_led(pcr);
970 rtsx_pci_enable_aspm(pcr);
972 mutex_unlock(&pcr->pcr_mutex);
976 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
978 if (pcr->ops->turn_off_led)
979 pcr->ops->turn_off_led(pcr);
981 rtsx_pci_writel(pcr, RTSX_BIER, 0);
984 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
985 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
987 if (pcr->ops->force_power_down)
988 pcr->ops->force_power_down(pcr, pm_state);
992 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
996 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
997 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
999 rtsx_pci_enable_bus_int(pcr);
1002 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1006 /* Wait SSC power stable */
1009 rtsx_pci_disable_aspm(pcr);
1010 if (pcr->ops->optimize_phy) {
1011 err = pcr->ops->optimize_phy(pcr);
1016 rtsx_pci_init_cmd(pcr);
1018 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1022 /* Disable card clock */
1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1024 /* Reset delink mode */
1025 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1026 /* Card driving select */
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1028 0xFF, pcr->card_drive_sel);
1029 /* Enable SSC Clock */
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1031 0xFF, SSC_8X_EN | SSC_SEL_4M);
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1033 /* Disable cd_pwr_save */
1034 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1035 /* Clear Link Ready Interrupt */
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1037 LINK_RDY_INT, LINK_RDY_INT);
1038 /* Enlarge the estimation window of PERST# glitch
1039 * to reduce the chance of invalid card interrupt
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1042 /* Update RC oscillator to 400k
1043 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1047 /* Set interrupt write clear
1048 * bit 1: U_elbi_if_rd_clr_en
1049 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1050 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1052 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1054 err = rtsx_pci_send_cmd(pcr, 100);
1058 /* Enable clk_request_n to enable clock power management */
1059 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1060 /* Enter L1 when host tx idle */
1061 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1063 if (pcr->ops->extra_init_hw) {
1064 err = pcr->ops->extra_init_hw(pcr);
1069 /* No CD interrupt if probing driver with card inserted.
1070 * So we need to initialize pcr->card_exist here.
1072 if (pcr->ops->cd_deglitch)
1073 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1075 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1080 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1084 spin_lock_init(&pcr->lock);
1085 mutex_init(&pcr->pcr_mutex);
1087 switch (PCI_PID(pcr)) {
1090 rts5209_init_params(pcr);
1094 rts5229_init_params(pcr);
1098 rtl8411_init_params(pcr);
1102 rts5227_init_params(pcr);
1106 rts5249_init_params(pcr);
1110 rts524a_init_params(pcr);
1114 rts525a_init_params(pcr);
1118 rtl8411b_init_params(pcr);
1122 rtl8402_init_params(pcr);
1126 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1127 PCI_PID(pcr), pcr->ic_version);
1129 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1134 if (pcr->ops->fetch_vendor_settings)
1135 pcr->ops->fetch_vendor_settings(pcr);
1137 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1138 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1139 pcr->sd30_drive_sel_1v8);
1140 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1141 pcr->sd30_drive_sel_3v3);
1142 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1143 pcr->card_drive_sel);
1144 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1146 pcr->state = PDEV_STAT_IDLE;
1147 err = rtsx_pci_init_hw(pcr);
1156 static int rtsx_pci_probe(struct pci_dev *pcidev,
1157 const struct pci_device_id *id)
1159 struct rtsx_pcr *pcr;
1160 struct pcr_handle *handle;
1162 int ret, i, bar = 0;
1164 dev_dbg(&(pcidev->dev),
1165 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1166 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1167 (int)pcidev->revision);
1169 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1173 ret = pci_enable_device(pcidev);
1177 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1181 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1187 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1194 idr_preload(GFP_KERNEL);
1195 spin_lock(&rtsx_pci_lock);
1196 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1199 spin_unlock(&rtsx_pci_lock);
1205 dev_set_drvdata(&pcidev->dev, handle);
1207 if (CHK_PCI_PID(pcr, 0x525A))
1209 len = pci_resource_len(pcidev, bar);
1210 base = pci_resource_start(pcidev, bar);
1211 pcr->remap_addr = ioremap_nocache(base, len);
1212 if (!pcr->remap_addr) {
1217 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1218 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1220 if (pcr->rtsx_resv_buf == NULL) {
1224 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1225 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1226 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1227 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1229 pcr->card_inserted = 0;
1230 pcr->card_removed = 0;
1231 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1232 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1234 pcr->msi_en = msi_en;
1236 ret = pci_enable_msi(pcidev);
1238 pcr->msi_en = false;
1241 ret = rtsx_pci_acquire_irq(pcr);
1245 pci_set_master(pcidev);
1246 synchronize_irq(pcr->irq);
1248 ret = rtsx_pci_init_chip(pcr);
1252 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1253 rtsx_pcr_cells[i].platform_data = handle;
1254 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1256 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1257 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1261 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1266 free_irq(pcr->irq, (void *)pcr);
1269 pci_disable_msi(pcr->pci);
1270 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1271 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1273 iounmap(pcr->remap_addr);
1279 pci_release_regions(pcidev);
1281 pci_disable_device(pcidev);
1286 static void rtsx_pci_remove(struct pci_dev *pcidev)
1288 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1289 struct rtsx_pcr *pcr = handle->pcr;
1291 pcr->remove_pci = true;
1293 /* Disable interrupts at the pcr level */
1294 spin_lock_irq(&pcr->lock);
1295 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1297 spin_unlock_irq(&pcr->lock);
1299 cancel_delayed_work_sync(&pcr->carddet_work);
1300 cancel_delayed_work_sync(&pcr->idle_work);
1302 mfd_remove_devices(&pcidev->dev);
1304 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1305 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1306 free_irq(pcr->irq, (void *)pcr);
1308 pci_disable_msi(pcr->pci);
1309 iounmap(pcr->remap_addr);
1311 pci_release_regions(pcidev);
1312 pci_disable_device(pcidev);
1314 spin_lock(&rtsx_pci_lock);
1315 idr_remove(&rtsx_pci_idr, pcr->id);
1316 spin_unlock(&rtsx_pci_lock);
1322 dev_dbg(&(pcidev->dev),
1323 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1324 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1329 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1331 struct pcr_handle *handle;
1332 struct rtsx_pcr *pcr;
1334 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1336 handle = pci_get_drvdata(pcidev);
1339 cancel_delayed_work(&pcr->carddet_work);
1340 cancel_delayed_work(&pcr->idle_work);
1342 mutex_lock(&pcr->pcr_mutex);
1344 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1346 pci_save_state(pcidev);
1347 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1348 pci_disable_device(pcidev);
1349 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1351 mutex_unlock(&pcr->pcr_mutex);
1355 static int rtsx_pci_resume(struct pci_dev *pcidev)
1357 struct pcr_handle *handle;
1358 struct rtsx_pcr *pcr;
1361 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1363 handle = pci_get_drvdata(pcidev);
1366 mutex_lock(&pcr->pcr_mutex);
1368 pci_set_power_state(pcidev, PCI_D0);
1369 pci_restore_state(pcidev);
1370 ret = pci_enable_device(pcidev);
1373 pci_set_master(pcidev);
1375 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1379 ret = rtsx_pci_init_hw(pcr);
1383 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1386 mutex_unlock(&pcr->pcr_mutex);
1390 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1392 struct pcr_handle *handle;
1393 struct rtsx_pcr *pcr;
1395 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1397 handle = pci_get_drvdata(pcidev);
1399 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1401 pci_disable_device(pcidev);
1404 #else /* CONFIG_PM */
1406 #define rtsx_pci_suspend NULL
1407 #define rtsx_pci_resume NULL
1408 #define rtsx_pci_shutdown NULL
1410 #endif /* CONFIG_PM */
1412 static struct pci_driver rtsx_pci_driver = {
1413 .name = DRV_NAME_RTSX_PCI,
1414 .id_table = rtsx_pci_ids,
1415 .probe = rtsx_pci_probe,
1416 .remove = rtsx_pci_remove,
1417 .suspend = rtsx_pci_suspend,
1418 .resume = rtsx_pci_resume,
1419 .shutdown = rtsx_pci_shutdown,
1421 module_pci_driver(rtsx_pci_driver);
1423 MODULE_LICENSE("GPL");
1424 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1425 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");