drivers/mfd/sm501.c

   1 /* linux/drivers/mfd/sm501.c
   2  *
   3  * Copyright (C) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *      Vincent Sanders <vince@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * SM501 MFD driver
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/list.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pci.h>
  22 #include <linux/i2c-gpio.h>
  23
  24 #include <linux/sm501.h>
  25 #include <linux/sm501-regs.h>
  26 #include <linux/serial_8250.h>
  27
  28 #include <asm/io.h>
  29
  30 struct sm501_device {
  31         struct list_head                list;
  32         struct platform_device          pdev;
  33 };
  34
  35 struct sm501_gpio;
  36
  37 #ifdef CONFIG_MFD_SM501_GPIO
  38 #include <linux/gpio.h>
  39
  40 struct sm501_gpio_chip {
  41         struct gpio_chip        gpio;
  42         struct sm501_gpio       *ourgpio;       /* to get back to parent. */
  43         void __iomem            *regbase;
  44         void __iomem            *control;       /* address of control reg. */
  45 };
  46
  47 struct sm501_gpio {
  48         struct sm501_gpio_chip  low;
  49         struct sm501_gpio_chip  high;
  50         spinlock_t              lock;
  51
  52         unsigned int             registered : 1;
  53         void __iomem            *regs;
  54         struct resource         *regs_res;
  55 };
  56 #else
  57 struct sm501_gpio {
  58         /* no gpio support, empty definition for sm501_devdata. */
  59 };
  60 #endif
  61
  62 struct sm501_devdata {
  63         spinlock_t                       reg_lock;
  64         struct mutex                     clock_lock;
  65         struct list_head                 devices;
  66         struct sm501_gpio                gpio;
  67
  68         struct device                   *dev;
  69         struct resource                 *io_res;
  70         struct resource                 *mem_res;
  71         struct resource                 *regs_claim;
  72         struct sm501_platdata           *platdata;
  73
  74
  75         unsigned int                     in_suspend;
  76         unsigned long                    pm_misc;
  77
  78         int                              unit_power[20];
  79         unsigned int                     pdev_id;
  80         unsigned int                     irq;
  81         void __iomem                    *regs;
  82         unsigned int                     rev;
  83 };
  84
  85
  86 #define MHZ (1000 * 1000)
  87
  88 #ifdef DEBUG
  89 static const unsigned int div_tab[] = {
  90         [0]             = 1,
  91         [1]             = 2,
  92         [2]             = 4,
  93         [3]             = 8,
  94         [4]             = 16,
  95         [5]             = 32,
  96         [6]             = 64,
  97         [7]             = 128,
  98         [8]             = 3,
  99         [9]             = 6,
 100         [10]            = 12,
 101         [11]            = 24,
 102         [12]            = 48,
 103         [13]            = 96,
 104         [14]            = 192,
 105         [15]            = 384,
 106         [16]            = 5,
 107         [17]            = 10,
 108         [18]            = 20,
 109         [19]            = 40,
 110         [20]            = 80,
 111         [21]            = 160,
 112         [22]            = 320,
 113         [23]            = 604,
 114 };
 115
 116 static unsigned long decode_div(unsigned long pll2, unsigned long val,
 117                                 unsigned int lshft, unsigned int selbit,
 118                                 unsigned long mask)
 119 {
 120         if (val & selbit)
 121                 pll2 = 288 * MHZ;
 122
 123         return pll2 / div_tab[(val >> lshft) & mask];
 124 }
 125
 126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
 127
 128 /* sm501_dump_clk
 129  *
 130  * Print out the current clock configuration for the device
 131 */
 132
 133 static void sm501_dump_clk(struct sm501_devdata *sm)
 134 {
 135         unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
 136         unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
 137         unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
 138         unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 139         unsigned long sdclk0, sdclk1;
 140         unsigned long pll2 = 0;
 141
 142         switch (misct & 0x30) {
 143         case 0x00:
 144                 pll2 = 336 * MHZ;
 145                 break;
 146         case 0x10:
 147                 pll2 = 288 * MHZ;
 148                 break;
 149         case 0x20:
 150                 pll2 = 240 * MHZ;
 151                 break;
 152         case 0x30:
 153                 pll2 = 192 * MHZ;
 154                 break;
 155         }
 156
 157         sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
 158         sdclk0 /= div_tab[((misct >> 8) & 0xf)];
 159
 160         sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
 161         sdclk1 /= div_tab[((misct >> 16) & 0xf)];
 162
 163         dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
 164                 misct, pm0, pm1);
 165
 166         dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
 167                 fmt_freq(pll2), sdclk0, sdclk1);
 168
 169         dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
 170
 171         dev_dbg(sm->dev, "PM0[%c]: "
 172                  "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 173                  "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 174                  (pmc & 3 ) == 0 ? '*' : '-',
 175                  fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
 176                  fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
 177                  fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
 178                  fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
 179
 180         dev_dbg(sm->dev, "PM1[%c]: "
 181                 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
 182                 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
 183                 (pmc & 3 ) == 1 ? '*' : '-',
 184                 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
 185                 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
 186                 fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
 187                 fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
 188 }
 189
 190 static void sm501_dump_regs(struct sm501_devdata *sm)
 191 {
 192         void __iomem *regs = sm->regs;
 193
 194         dev_info(sm->dev, "System Control   %08x\n",
 195                         readl(regs + SM501_SYSTEM_CONTROL));
 196         dev_info(sm->dev, "Misc Control     %08x\n",
 197                         readl(regs + SM501_MISC_CONTROL));
 198         dev_info(sm->dev, "GPIO Control Low %08x\n",
 199                         readl(regs + SM501_GPIO31_0_CONTROL));
 200         dev_info(sm->dev, "GPIO Control Hi  %08x\n",
 201                         readl(regs + SM501_GPIO63_32_CONTROL));
 202         dev_info(sm->dev, "DRAM Control     %08x\n",
 203                         readl(regs + SM501_DRAM_CONTROL));
 204         dev_info(sm->dev, "Arbitration Ctrl %08x\n",
 205                         readl(regs + SM501_ARBTRTN_CONTROL));
 206         dev_info(sm->dev, "Misc Timing      %08x\n",
 207                         readl(regs + SM501_MISC_TIMING));
 208 }
 209
 210 static void sm501_dump_gate(struct sm501_devdata *sm)
 211 {
 212         dev_info(sm->dev, "CurrentGate      %08x\n",
 213                         readl(sm->regs + SM501_CURRENT_GATE));
 214         dev_info(sm->dev, "CurrentClock     %08x\n",
 215                         readl(sm->regs + SM501_CURRENT_CLOCK));
 216         dev_info(sm->dev, "PowerModeControl %08x\n",
 217                         readl(sm->regs + SM501_POWER_MODE_CONTROL));
 218 }
 219
 220 #else
 221 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
 222 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
 223 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
 224 #endif
 225
 226 /* sm501_sync_regs
 227  *
 228  * ensure the
 229 */
 230
 231 static void sm501_sync_regs(struct sm501_devdata *sm)
 232 {
 233         readl(sm->regs);
 234 }
 235
 236 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
 237 {
 238         /* during suspend/resume, we are currently not allowed to sleep,
 239          * so change to using mdelay() instead of msleep() if we
 240          * are in one of these paths */
 241
 242         if (sm->in_suspend)
 243                 mdelay(delay);
 244         else
 245                 msleep(delay);
 246 }
 247
 248 /* sm501_misc_control
 249  *
 250  * alters the miscellaneous control parameters
 251 */
 252
 253 int sm501_misc_control(struct device *dev,
 254                        unsigned long set, unsigned long clear)
 255 {
 256         struct sm501_devdata *sm = dev_get_drvdata(dev);
 257         unsigned long misc;
 258         unsigned long save;
 259         unsigned long to;
 260
 261         spin_lock_irqsave(&sm->reg_lock, save);
 262
 263         misc = readl(sm->regs + SM501_MISC_CONTROL);
 264         to = (misc & ~clear) | set;
 265
 266         if (to != misc) {
 267                 writel(to, sm->regs + SM501_MISC_CONTROL);
 268                 sm501_sync_regs(sm);
 269
 270                 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
 271         }
 272
 273         spin_unlock_irqrestore(&sm->reg_lock, save);
 274         return to;
 275 }
 276
 277 EXPORT_SYMBOL_GPL(sm501_misc_control);
 278
 279 /* sm501_modify_reg
 280  *
 281  * Modify a register in the SM501 which may be shared with other
 282  * drivers.
 283 */
 284
 285 unsigned long sm501_modify_reg(struct device *dev,
 286                                unsigned long reg,
 287                                unsigned long set,
 288                                unsigned long clear)
 289 {
 290         struct sm501_devdata *sm = dev_get_drvdata(dev);
 291         unsigned long data;
 292         unsigned long save;
 293
 294         spin_lock_irqsave(&sm->reg_lock, save);
 295
 296         data = readl(sm->regs + reg);
 297         data |= set;
 298         data &= ~clear;
 299
 300         writel(data, sm->regs + reg);
 301         sm501_sync_regs(sm);
 302
 303         spin_unlock_irqrestore(&sm->reg_lock, save);
 304
 305         return data;
 306 }
 307
 308 EXPORT_SYMBOL_GPL(sm501_modify_reg);
 309
 310 /* sm501_unit_power
 311  *
 312  * alters the power active gate to set specific units on or off
 313  */
 314
 315 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
 316 {
 317         struct sm501_devdata *sm = dev_get_drvdata(dev);
 318         unsigned long mode;
 319         unsigned long gate;
 320         unsigned long clock;
 321
 322         mutex_lock(&sm->clock_lock);
 323
 324         mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 325         gate = readl(sm->regs + SM501_CURRENT_GATE);
 326         clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 327
 328         mode &= 3;              /* get current power mode */
 329
 330         if (unit >= ARRAY_SIZE(sm->unit_power)) {
 331                 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
 332                 goto already;
 333         }
 334
 335         dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
 336                 sm->unit_power[unit], to);
 337
 338         if (to == 0 && sm->unit_power[unit] == 0) {
 339                 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
 340                 goto already;
 341         }
 342
 343         sm->unit_power[unit] += to ? 1 : -1;
 344         to = sm->unit_power[unit] ? 1 : 0;
 345
 346         if (to) {
 347                 if (gate & (1 << unit))
 348                         goto already;
 349                 gate |= (1 << unit);
 350         } else {
 351                 if (!(gate & (1 << unit)))
 352                         goto already;
 353                 gate &= ~(1 << unit);
 354         }
 355
 356         switch (mode) {
 357         case 1:
 358                 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 359                 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 360                 mode = 0;
 361                 break;
 362         case 2:
 363         case 0:
 364                 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 365                 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 366                 mode = 1;
 367                 break;
 368
 369         default:
 370                 gate = -1;
 371                 goto already;
 372         }
 373
 374         writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 375         sm501_sync_regs(sm);
 376
 377         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 378                 gate, clock, mode);
 379
 380         sm501_mdelay(sm, 16);
 381
 382  already:
 383         mutex_unlock(&sm->clock_lock);
 384         return gate;
 385 }
 386
 387 EXPORT_SYMBOL_GPL(sm501_unit_power);
 388
 389
 390 /* Perform a rounded division. */
 391 static long sm501fb_round_div(long num, long denom)
 392 {
 393         /* n / d + 1 / 2 = (2n + d) / 2d */
 394         return (2 * num + denom) / (2 * denom);
 395 }
 396
 397 /* clock value structure. */
 398 struct sm501_clock {
 399         unsigned long mclk;
 400         int divider;
 401         int shift;
 402         unsigned int m, n, k;
 403 };
 404
 405 /* sm501_calc_clock
 406  *
 407  * Calculates the nearest discrete clock frequency that
 408  * can be achieved with the specified input clock.
 409  *   the maximum divisor is 3 or 5
 410  */
 411
 412 static int sm501_calc_clock(unsigned long freq,
 413                             struct sm501_clock *clock,
 414                             int max_div,
 415                             unsigned long mclk,
 416                             long *best_diff)
 417 {
 418         int ret = 0;
 419         int divider;
 420         int shift;
 421         long diff;
 422
 423         /* try dividers 1 and 3 for CRT and for panel,
 424            try divider 5 for panel only.*/
 425
 426         for (divider = 1; divider <= max_div; divider += 2) {
 427                 /* try all 8 shift values.*/
 428                 for (shift = 0; shift < 8; shift++) {
 429                         /* Calculate difference to requested clock */
 430                         diff = sm501fb_round_div(mclk, divider << shift) - freq;
 431                         if (diff < 0)
 432                                 diff = -diff;
 433
 434                         /* If it is less than the current, use it */
 435                         if (diff < *best_diff) {
 436                                 *best_diff = diff;
 437
 438                                 clock->mclk = mclk;
 439                                 clock->divider = divider;
 440                                 clock->shift = shift;
 441                                 ret = 1;
 442                         }
 443                 }
 444         }
 445
 446         return ret;
 447 }
 448
 449 /* sm501_calc_pll
 450  *
 451  * Calculates the nearest discrete clock frequency that can be
 452  * achieved using the programmable PLL.
 453  *   the maximum divisor is 3 or 5
 454  */
 455
 456 static unsigned long sm501_calc_pll(unsigned long freq,
 457                                         struct sm501_clock *clock,
 458                                         int max_div)
 459 {
 460         unsigned long mclk;
 461         unsigned int m, n, k;
 462         long best_diff = 999999999;
 463
 464         /*
 465          * The SM502 datasheet doesn't specify the min/max values for M and N.
 466          * N = 1 at least doesn't work in practice.
 467          */
 468         for (m = 2; m <= 255; m++) {
 469                 for (n = 2; n <= 127; n++) {
 470                         for (k = 0; k <= 1; k++) {
 471                                 mclk = (24000000UL * m / n) >> k;
 472
 473                                 if (sm501_calc_clock(freq, clock, max_div,
 474                                                      mclk, &best_diff)) {
 475                                         clock->m = m;
 476                                         clock->n = n;
 477                                         clock->k = k;
 478                                 }
 479                         }
 480                 }
 481         }
 482
 483         /* Return best clock. */
 484         return clock->mclk / (clock->divider << clock->shift);
 485 }
 486
 487 /* sm501_select_clock
 488  *
 489  * Calculates the nearest discrete clock frequency that can be
 490  * achieved using the 288MHz and 336MHz PLLs.
 491  *   the maximum divisor is 3 or 5
 492  */
 493
 494 static unsigned long sm501_select_clock(unsigned long freq,
 495                                         struct sm501_clock *clock,
 496                                         int max_div)
 497 {
 498         unsigned long mclk;
 499         long best_diff = 999999999;
 500
 501         /* Try 288MHz and 336MHz clocks. */
 502         for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
 503                 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
 504         }
 505
 506         /* Return best clock. */
 507         return clock->mclk / (clock->divider << clock->shift);
 508 }
 509
 510 /* sm501_set_clock
 511  *
 512  * set one of the four clock sources to the closest available frequency to
 513  *  the one specified
 514 */
 515
 516 unsigned long sm501_set_clock(struct device *dev,
 517                               int clksrc,
 518                               unsigned long req_freq)
 519 {
 520         struct sm501_devdata *sm = dev_get_drvdata(dev);
 521         unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 522         unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
 523         unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 524         unsigned char reg;
 525         unsigned int pll_reg = 0;
 526         unsigned long sm501_freq; /* the actual frequency acheived */
 527
 528         struct sm501_clock to;
 529
 530         /* find achivable discrete frequency and setup register value
 531          * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
 532          * has an extra bit for the divider */
 533
 534         switch (clksrc) {
 535         case SM501_CLOCK_P2XCLK:
 536                 /* This clock is divided in half so to achive the
 537                  * requested frequency the value must be multiplied by
 538                  * 2. This clock also has an additional pre divisor */
 539
 540                 if (sm->rev >= 0xC0) {
 541                         /* SM502 -> use the programmable PLL */
 542                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 543                                                      &to, 5) / 2);
 544                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 545                         if (to.divider == 3)
 546                                 reg |= 0x08; /* /3 divider required */
 547                         else if (to.divider == 5)
 548                                 reg |= 0x10; /* /5 divider required */
 549                         reg |= 0x40; /* select the programmable PLL */
 550                         pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
 551                 } else {
 552                         sm501_freq = (sm501_select_clock(2 * req_freq,
 553                                                          &to, 5) / 2);
 554                         reg = to.shift & 0x07;/* bottom 3 bits are shift */
 555                         if (to.divider == 3)
 556                                 reg |= 0x08; /* /3 divider required */
 557                         else if (to.divider == 5)
 558                                 reg |= 0x10; /* /5 divider required */
 559                         if (to.mclk != 288000000)
 560                                 reg |= 0x20; /* which mclk pll is source */
 561                 }
 562                 break;
 563
 564         case SM501_CLOCK_V2XCLK:
 565                 /* This clock is divided in half so to achive the
 566                  * requested frequency the value must be multiplied by 2. */
 567
 568                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 569                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 570                 if (to.divider == 3)
 571                         reg |= 0x08;    /* /3 divider required */
 572                 if (to.mclk != 288000000)
 573                         reg |= 0x10;    /* which mclk pll is source */
 574                 break;
 575
 576         case SM501_CLOCK_MCLK:
 577         case SM501_CLOCK_M1XCLK:
 578                 /* These clocks are the same and not further divided */
 579
 580                 sm501_freq = sm501_select_clock( req_freq, &to, 3);
 581                 reg=to.shift & 0x07;    /* bottom 3 bits are shift */
 582                 if (to.divider == 3)
 583                         reg |= 0x08;    /* /3 divider required */
 584                 if (to.mclk != 288000000)
 585                         reg |= 0x10;    /* which mclk pll is source */
 586                 break;
 587
 588         default:
 589                 return 0; /* this is bad */
 590         }
 591
 592         mutex_lock(&sm->clock_lock);
 593
 594         mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
 595         gate = readl(sm->regs + SM501_CURRENT_GATE);
 596         clock = readl(sm->regs + SM501_CURRENT_CLOCK);
 597
 598         clock = clock & ~(0xFF << clksrc);
 599         clock |= reg<<clksrc;
 600
 601         mode &= 3;      /* find current mode */
 602
 603         switch (mode) {
 604         case 1:
 605                 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
 606                 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
 607                 mode = 0;
 608                 break;
 609         case 2:
 610         case 0:
 611                 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
 612                 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
 613                 mode = 1;
 614                 break;
 615
 616         default:
 617                 mutex_unlock(&sm->clock_lock);
 618                 return -1;
 619         }
 620
 621         writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
 622
 623         if (pll_reg)
 624                 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
 625
 626         sm501_sync_regs(sm);
 627
 628         dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
 629                 gate, clock, mode);
 630
 631         sm501_mdelay(sm, 16);
 632         mutex_unlock(&sm->clock_lock);
 633
 634         sm501_dump_clk(sm);
 635
 636         return sm501_freq;
 637 }
 638
 639 EXPORT_SYMBOL_GPL(sm501_set_clock);
 640
 641 /* sm501_find_clock
 642  *
 643  * finds the closest available frequency for a given clock
 644 */
 645
 646 unsigned long sm501_find_clock(struct device *dev,
 647                                int clksrc,
 648                                unsigned long req_freq)
 649 {
 650         struct sm501_devdata *sm = dev_get_drvdata(dev);
 651         unsigned long sm501_freq; /* the frequency achiveable by the 501 */
 652         struct sm501_clock to;
 653
 654         switch (clksrc) {
 655         case SM501_CLOCK_P2XCLK:
 656                 if (sm->rev >= 0xC0) {
 657                         /* SM502 -> use the programmable PLL */
 658                         sm501_freq = (sm501_calc_pll(2 * req_freq,
 659                                                      &to, 5) / 2);
 660                 } else {
 661                         sm501_freq = (sm501_select_clock(2 * req_freq,
 662                                                          &to, 5) / 2);
 663                 }
 664                 break;
 665
 666         case SM501_CLOCK_V2XCLK:
 667                 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
 668                 break;
 669
 670         case SM501_CLOCK_MCLK:
 671         case SM501_CLOCK_M1XCLK:
 672                 sm501_freq = sm501_select_clock(req_freq, &to, 3);
 673                 break;
 674
 675         default:
 676                 sm501_freq = 0;         /* error */
 677         }
 678
 679         return sm501_freq;
 680 }
 681
 682 EXPORT_SYMBOL_GPL(sm501_find_clock);
 683
 684 static struct sm501_device *to_sm_device(struct platform_device *pdev)
 685 {
 686         return container_of(pdev, struct sm501_device, pdev);
 687 }
 688
 689 /* sm501_device_release
 690  *
 691  * A release function for the platform devices we create to allow us to
 692  * free any items we allocated
 693 */
 694
 695 static void sm501_device_release(struct device *dev)
 696 {
 697         kfree(to_sm_device(to_platform_device(dev)));
 698 }
 699
 700 /* sm501_create_subdev
 701  *
 702  * Create a skeleton platform device with resources for passing to a
 703  * sub-driver
 704 */
 705
 706 static struct platform_device *
 707 sm501_create_subdev(struct sm501_devdata *sm, char *name,
 708                     unsigned int res_count, unsigned int platform_data_size)
 709 {
 710         struct sm501_device *smdev;
 711
 712         smdev = kzalloc(sizeof(struct sm501_device) +
 713                         (sizeof(struct resource) * res_count) +
 714                         platform_data_size, GFP_KERNEL);
 715         if (!smdev)
 716                 return NULL;
 717
 718         smdev->pdev.dev.release = sm501_device_release;
 719
 720         smdev->pdev.name = name;
 721         smdev->pdev.id = sm->pdev_id;
 722         smdev->pdev.dev.parent = sm->dev;
 723
 724         if (res_count) {
 725                 smdev->pdev.resource = (struct resource *)(smdev+1);
 726                 smdev->pdev.num_resources = res_count;
 727         }
 728         if (platform_data_size)
 729                 smdev->pdev.dev.platform_data = (void *)(smdev+1);
 730
 731         return &smdev->pdev;
 732 }
 733
 734 /* sm501_register_device
 735  *
 736  * Register a platform device created with sm501_create_subdev()
 737 */
 738
 739 static int sm501_register_device(struct sm501_devdata *sm,
 740                                  struct platform_device *pdev)
 741 {
 742         struct sm501_device *smdev = to_sm_device(pdev);
 743         int ptr;
 744         int ret;
 745
 746         for (ptr = 0; ptr < pdev->num_resources; ptr++) {
 747                 printk(KERN_DEBUG "%s[%d] flags %08lx: %08llx..%08llx\n",
 748                        pdev->name, ptr,
 749                        pdev->resource[ptr].flags,
 750                        (unsigned long long)pdev->resource[ptr].start,
 751                        (unsigned long long)pdev->resource[ptr].end);
 752         }
 753
 754         ret = platform_device_register(pdev);
 755
 756         if (ret >= 0) {
 757                 dev_dbg(sm->dev, "registered %s\n", pdev->name);
 758                 list_add_tail(&smdev->list, &sm->devices);
 759         } else
 760                 dev_err(sm->dev, "error registering %s (%d)\n",
 761                         pdev->name, ret);
 762
 763         return ret;
 764 }
 765
 766 /* sm501_create_subio
 767  *
 768  * Fill in an IO resource for a sub device
 769 */
 770
 771 static void sm501_create_subio(struct sm501_devdata *sm,
 772                                struct resource *res,
 773                                resource_size_t offs,
 774                                resource_size_t size)
 775 {
 776         res->flags = IORESOURCE_MEM;
 777         res->parent = sm->io_res;
 778         res->start = sm->io_res->start + offs;
 779         res->end = res->start + size - 1;
 780 }
 781
 782 /* sm501_create_mem
 783  *
 784  * Fill in an MEM resource for a sub device
 785 */
 786
 787 static void sm501_create_mem(struct sm501_devdata *sm,
 788                              struct resource *res,
 789                              resource_size_t *offs,
 790                              resource_size_t size)
 791 {
 792         *offs -= size;          /* adjust memory size */
 793
 794         res->flags = IORESOURCE_MEM;
 795         res->parent = sm->mem_res;
 796         res->start = sm->mem_res->start + *offs;
 797         res->end = res->start + size - 1;
 798 }
 799
 800 /* sm501_create_irq
 801  *
 802  * Fill in an IRQ resource for a sub device
 803 */
 804
 805 static void sm501_create_irq(struct sm501_devdata *sm,
 806                              struct resource *res)
 807 {
 808         res->flags = IORESOURCE_IRQ;
 809         res->parent = NULL;
 810         res->start = res->end = sm->irq;
 811 }
 812
 813 static int sm501_register_usbhost(struct sm501_devdata *sm,
 814                                   resource_size_t *mem_avail)
 815 {
 816         struct platform_device *pdev;
 817
 818         pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
 819         if (!pdev)
 820                 return -ENOMEM;
 821
 822         sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
 823         sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
 824         sm501_create_irq(sm, &pdev->resource[2]);
 825
 826         return sm501_register_device(sm, pdev);
 827 }
 828
 829 static void sm501_setup_uart_data(struct sm501_devdata *sm,
 830                                   struct plat_serial8250_port *uart_data,
 831                                   unsigned int offset)
 832 {
 833         uart_data->membase = sm->regs + offset;
 834         uart_data->mapbase = sm->io_res->start + offset;
 835         uart_data->iotype = UPIO_MEM;
 836         uart_data->irq = sm->irq;
 837         uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
 838         uart_data->regshift = 2;
 839         uart_data->uartclk = (9600 * 16);
 840 }
 841
 842 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
 843 {
 844         struct platform_device *pdev;
 845         struct plat_serial8250_port *uart_data;
 846
 847         pdev = sm501_create_subdev(sm, "serial8250", 0,
 848                                    sizeof(struct plat_serial8250_port) * 3);
 849         if (!pdev)
 850                 return -ENOMEM;
 851
 852         uart_data = pdev->dev.platform_data;
 853
 854         if (devices & SM501_USE_UART0) {
 855                 sm501_setup_uart_data(sm, uart_data++, 0x30000);
 856                 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
 857                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
 858                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
 859         }
 860         if (devices & SM501_USE_UART1) {
 861                 sm501_setup_uart_data(sm, uart_data++, 0x30020);
 862                 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
 863                 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
 864                 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
 865         }
 866
 867         pdev->id = PLAT8250_DEV_SM501;
 868
 869         return sm501_register_device(sm, pdev);
 870 }
 871
 872 static int sm501_register_display(struct sm501_devdata *sm,
 873                                   resource_size_t *mem_avail)
 874 {
 875         struct platform_device *pdev;
 876
 877         pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
 878         if (!pdev)
 879                 return -ENOMEM;
 880
 881         sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
 882         sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
 883         sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
 884         sm501_create_irq(sm, &pdev->resource[3]);
 885
 886         return sm501_register_device(sm, pdev);
 887 }
 888
 889 #ifdef CONFIG_MFD_SM501_GPIO
 890
 891 static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
 892 {
 893         return container_of(gc, struct sm501_gpio_chip, gpio);
 894 }
 895
 896 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
 897 {
 898         return container_of(gpio, struct sm501_devdata, gpio);
 899 }
 900
 901 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
 902
 903 {
 904         struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
 905         unsigned long result;
 906
 907         result = readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
 908         result >>= offset;
 909
 910         return result & 1UL;
 911 }
 912
 913 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
 914                                    unsigned long bit)
 915 {
 916         unsigned long ctrl;
 917
 918         /* check and modify if this pin is not set as gpio. */
 919
 920         if (readl(smchip->control) & bit) {
 921                 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
 922                          "changing mode of gpio, bit %08lx\n", bit);
 923
 924                 ctrl = readl(smchip->control);
 925                 ctrl &= ~bit;
 926                 writel(ctrl, smchip->control);
 927
 928                 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
 929         }
 930 }
 931
 932 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 933
 934 {
 935         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 936         struct sm501_gpio *smgpio = smchip->ourgpio;
 937         unsigned long bit = 1 << offset;
 938         void __iomem *regs = smchip->regbase;
 939         unsigned long save;
 940         unsigned long val;
 941
 942         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 943                 __func__, chip, offset);
 944
 945         spin_lock_irqsave(&smgpio->lock, save);
 946
 947         val = readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
 948         if (value)
 949                 val |= bit;
 950         writel(val, regs);
 951
 952         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 953         sm501_gpio_ensure_gpio(smchip, bit);
 954
 955         spin_unlock_irqrestore(&smgpio->lock, save);
 956 }
 957
 958 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
 959 {
 960         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 961         struct sm501_gpio *smgpio = smchip->ourgpio;
 962         void __iomem *regs = smchip->regbase;
 963         unsigned long bit = 1 << offset;
 964         unsigned long save;
 965         unsigned long ddr;
 966
 967         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
 968                 __func__, chip, offset);
 969
 970         spin_lock_irqsave(&smgpio->lock, save);
 971
 972         ddr = readl(regs + SM501_GPIO_DDR_LOW);
 973         writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
 974
 975         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
 976         sm501_gpio_ensure_gpio(smchip, bit);
 977
 978         spin_unlock_irqrestore(&smgpio->lock, save);
 979
 980         return 0;
 981 }
 982
 983 static int sm501_gpio_output(struct gpio_chip *chip,
 984                              unsigned offset, int value)
 985 {
 986         struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
 987         struct sm501_gpio *smgpio = smchip->ourgpio;
 988         unsigned long bit = 1 << offset;
 989         void __iomem *regs = smchip->regbase;
 990         unsigned long save;
 991         unsigned long val;
 992         unsigned long ddr;
 993
 994         dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
 995                 __func__, chip, offset, value);
 996
 997         spin_lock_irqsave(&smgpio->lock, save);
 998
 999         val = readl(regs + SM501_GPIO_DATA_LOW);
1000         if (value)
1001                 val |= bit;
1002         else
1003                 val &= ~bit;
1004         writel(val, regs);
1005
1006         ddr = readl(regs + SM501_GPIO_DDR_LOW);
1007         writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
1008
1009         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1010         writel(val, regs + SM501_GPIO_DATA_LOW);
1011
1012         sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1013         spin_unlock_irqrestore(&smgpio->lock, save);
1014
1015         return 0;
1016 }
1017
1018 static struct gpio_chip gpio_chip_template = {
1019         .ngpio                  = 32,
1020         .direction_input        = sm501_gpio_input,
1021         .direction_output       = sm501_gpio_output,
1022         .set                    = sm501_gpio_set,
1023         .get                    = sm501_gpio_get,
1024 };
1025
1026 static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
1027                                               struct sm501_gpio *gpio,
1028                                               struct sm501_gpio_chip *chip)
1029 {
1030         struct sm501_platdata *pdata = sm->platdata;
1031         struct gpio_chip *gchip = &chip->gpio;
1032         int base = pdata->gpio_base;
1033
1034         chip->gpio = gpio_chip_template;
1035
1036         if (chip == &gpio->high) {
1037                 if (base > 0)
1038                         base += 32;
1039                 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1040                 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1041                 gchip->label  = "SM501-HIGH";
1042         } else {
1043                 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1044                 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1045                 gchip->label  = "SM501-LOW";
1046         }
1047
1048         gchip->base   = base;
1049         chip->ourgpio = gpio;
1050
1051         return gpiochip_add(gchip);
1052 }
1053
1054 static int __devinit sm501_register_gpio(struct sm501_devdata *sm)
1055 {
1056         struct sm501_gpio *gpio = &sm->gpio;
1057         resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1058         int ret;
1059         int tmp;
1060
1061         dev_dbg(sm->dev, "registering gpio block %08llx\n",
1062                 (unsigned long long)iobase);
1063
1064         spin_lock_init(&gpio->lock);
1065
1066         gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1067         if (gpio->regs_res == NULL) {
1068                 dev_err(sm->dev, "gpio: failed to request region\n");
1069                 return -ENXIO;
1070         }
1071
1072         gpio->regs = ioremap(iobase, 0x20);
1073         if (gpio->regs == NULL) {
1074                 dev_err(sm->dev, "gpio: failed to remap registers\n");
1075                 ret = -ENXIO;
1076                 goto err_claimed;
1077         }
1078
1079         /* Register both our chips. */
1080
1081         ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1082         if (ret) {
1083                 dev_err(sm->dev, "failed to add low chip\n");
1084                 goto err_mapped;
1085         }
1086
1087         ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1088         if (ret) {
1089                 dev_err(sm->dev, "failed to add high chip\n");
1090                 goto err_low_chip;
1091         }
1092
1093         gpio->registered = 1;
1094
1095         return 0;
1096
1097  err_low_chip:
1098         tmp = gpiochip_remove(&gpio->low.gpio);
1099         if (tmp) {
1100                 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1101                 return ret;
1102         }
1103
1104  err_mapped:
1105         iounmap(gpio->regs);
1106
1107  err_claimed:
1108         release_resource(gpio->regs_res);
1109         kfree(gpio->regs_res);
1110
1111         return ret;
1112 }
1113
1114 static void sm501_gpio_remove(struct sm501_devdata *sm)
1115 {
1116         struct sm501_gpio *gpio = &sm->gpio;
1117         int ret;
1118
1119         if (!sm->gpio.registered)
1120                 return;
1121
1122         ret = gpiochip_remove(&gpio->low.gpio);
1123         if (ret)
1124                 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1125
1126         ret = gpiochip_remove(&gpio->high.gpio);
1127         if (ret)
1128                 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1129
1130         iounmap(gpio->regs);
1131         release_resource(gpio->regs_res);
1132         kfree(gpio->regs_res);
1133 }
1134
1135 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1136 {
1137         struct sm501_gpio *gpio = &sm->gpio;
1138         int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1139
1140         return (pin % 32) + base;
1141 }
1142
1143 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1144 {
1145         return sm->gpio.registered;
1146 }
1147 #else
1148 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1149 {
1150         return 0;
1151 }
1152
1153 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1154 {
1155 }
1156
1157 static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1158 {
1159         return -1;
1160 }
1161
1162 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1163 {
1164         return 0;
1165 }
1166 #endif
1167
1168 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1169                                             struct sm501_platdata_gpio_i2c *iic)
1170 {
1171         struct i2c_gpio_platform_data *icd;
1172         struct platform_device *pdev;
1173
1174         pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1175                                    sizeof(struct i2c_gpio_platform_data));
1176         if (!pdev)
1177                 return -ENOMEM;
1178
1179         icd = pdev->dev.platform_data;
1180
1181         /* We keep the pin_sda and pin_scl fields relative in case the
1182          * same platform data is passed to >1 SM501.
1183          */
1184
1185         icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1186         icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1187         icd->timeout = iic->timeout;
1188         icd->udelay = iic->udelay;
1189
1190         /* note, we can't use either of the pin numbers, as the i2c-gpio
1191          * driver uses the platform.id field to generate the bus number
1192          * to register with the i2c core; The i2c core doesn't have enough
1193          * entries to deal with anything we currently use.
1194         */
1195
1196         pdev->id = iic->bus_num;
1197
1198         dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1199                  iic->bus_num,
1200                  icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1201
1202         return sm501_register_device(sm, pdev);
1203 }
1204
1205 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1206                                    struct sm501_platdata *pdata)
1207 {
1208         struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1209         int index;
1210         int ret;
1211
1212         for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1213                 ret = sm501_register_gpio_i2c_instance(sm, iic);
1214                 if (ret < 0)
1215                         return ret;
1216         }
1217
1218         return 0;
1219 }
1220
1221 /* sm501_dbg_regs
1222  *
1223  * Debug attribute to attach to parent device to show core registers
1224 */
1225
1226 static ssize_t sm501_dbg_regs(struct device *dev,
1227                               struct device_attribute *attr, char *buff)
1228 {
1229         struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1230         unsigned int reg;
1231         char *ptr = buff;
1232         int ret;
1233
1234         for (reg = 0x00; reg < 0x70; reg += 4) {
1235                 ret = sprintf(ptr, "%08x = %08x\n",
1236                               reg, readl(sm->regs + reg));
1237                 ptr += ret;
1238         }
1239
1240         return ptr - buff;
1241 }
1242
1243
1244 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1245
1246 /* sm501_init_reg
1247  *
1248  * Helper function for the init code to setup a register
1249  *
1250  * clear the bits which are set in r->mask, and then set
1251  * the bits set in r->set.
1252 */
1253
1254 static inline void sm501_init_reg(struct sm501_devdata *sm,
1255                                   unsigned long reg,
1256                                   struct sm501_reg_init *r)
1257 {
1258         unsigned long tmp;
1259
1260         tmp = readl(sm->regs + reg);
1261         tmp &= ~r->mask;
1262         tmp |= r->set;
1263         writel(tmp, sm->regs + reg);
1264 }
1265
1266 /* sm501_init_regs
1267  *
1268  * Setup core register values
1269 */
1270
1271 static void sm501_init_regs(struct sm501_devdata *sm,
1272                             struct sm501_initdata *init)
1273 {
1274         sm501_misc_control(sm->dev,
1275                            init->misc_control.set,
1276                            init->misc_control.mask);
1277
1278         sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1279         sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1280         sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1281
1282         if (init->m1xclk) {
1283                 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1284                 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1285         }
1286
1287         if (init->mclk) {
1288                 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1289                 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1290         }
1291
1292 }
1293
1294 /* Check the PLL sources for the M1CLK and M1XCLK
1295  *
1296  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1297  * there is a risk (see errata AB-5) that the SM501 will cease proper
1298  * function. If this happens, then it is likely the SM501 will
1299  * hang the system.
1300 */
1301
1302 static int sm501_check_clocks(struct sm501_devdata *sm)
1303 {
1304         unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
1305         unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1306         unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1307
1308         return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1309 }
1310
1311 static unsigned int sm501_mem_local[] = {
1312         [0]     = 4*1024*1024,
1313         [1]     = 8*1024*1024,
1314         [2]     = 16*1024*1024,
1315         [3]     = 32*1024*1024,
1316         [4]     = 64*1024*1024,
1317         [5]     = 2*1024*1024,
1318 };
1319
1320 /* sm501_init_dev
1321  *
1322  * Common init code for an SM501
1323 */
1324
1325 static int __devinit sm501_init_dev(struct sm501_devdata *sm)
1326 {
1327         struct sm501_initdata *idata;
1328         struct sm501_platdata *pdata;
1329         resource_size_t mem_avail;
1330         unsigned long dramctrl;
1331         unsigned long devid;
1332         int ret;
1333
1334         mutex_init(&sm->clock_lock);
1335         spin_lock_init(&sm->reg_lock);
1336
1337         INIT_LIST_HEAD(&sm->devices);
1338
1339         devid = readl(sm->regs + SM501_DEVICEID);
1340
1341         if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1342                 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1343                 return -EINVAL;
1344         }
1345
1346         /* disable irqs */
1347         writel(0, sm->regs + SM501_IRQ_MASK);
1348
1349         dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
1350         mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1351
1352         dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1353                  sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1354
1355         sm->rev = devid & SM501_DEVICEID_REVMASK;
1356
1357         sm501_dump_gate(sm);
1358
1359         ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1360         if (ret)
1361                 dev_err(sm->dev, "failed to create debug regs file\n");
1362
1363         sm501_dump_clk(sm);
1364
1365         /* check to see if we have some device initialisation */
1366
1367         pdata = sm->platdata;
1368         idata = pdata ? pdata->init : NULL;
1369
1370         if (idata) {
1371                 sm501_init_regs(sm, idata);
1372
1373                 if (idata->devices & SM501_USE_USB_HOST)
1374                         sm501_register_usbhost(sm, &mem_avail);
1375                 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1376                         sm501_register_uart(sm, idata->devices);
1377                 if (idata->devices & SM501_USE_GPIO)
1378                         sm501_register_gpio(sm);
1379         }
1380
1381         if (pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1382                 if (!sm501_gpio_isregistered(sm))
1383                         dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1384                 else
1385                         sm501_register_gpio_i2c(sm, pdata);
1386         }
1387
1388         ret = sm501_check_clocks(sm);
1389         if (ret) {
1390                 dev_err(sm->dev, "M1X and M clocks sourced from different "
1391                                         "PLLs\n");
1392                 return -EINVAL;
1393         }
1394
1395         /* always create a framebuffer */
1396         sm501_register_display(sm, &mem_avail);
1397
1398         return 0;
1399 }
1400
1401 static int __devinit sm501_plat_probe(struct platform_device *dev)
1402 {
1403         struct sm501_devdata *sm;
1404         int ret;
1405
1406         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1407         if (sm == NULL) {
1408                 dev_err(&dev->dev, "no memory for device data\n");
1409                 ret = -ENOMEM;
1410                 goto err1;
1411         }
1412
1413         sm->dev = &dev->dev;
1414         sm->pdev_id = dev->id;
1415         sm->platdata = dev->dev.platform_data;
1416
1417         ret = platform_get_irq(dev, 0);
1418         if (ret < 0) {
1419                 dev_err(&dev->dev, "failed to get irq resource\n");
1420                 goto err_res;
1421         }
1422         sm->irq = ret;
1423
1424         sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1425         sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1426         if (sm->io_res == NULL || sm->mem_res == NULL) {
1427                 dev_err(&dev->dev, "failed to get IO resource\n");
1428                 ret = -ENOENT;
1429                 goto err_res;
1430         }
1431
1432         sm->regs_claim = request_mem_region(sm->io_res->start,
1433                                             0x100, "sm501");
1434
1435         if (sm->regs_claim == NULL) {
1436                 dev_err(&dev->dev, "cannot claim registers\n");
1437                 ret = -EBUSY;
1438                 goto err_res;
1439         }
1440
1441         platform_set_drvdata(dev, sm);
1442
1443         sm->regs = ioremap(sm->io_res->start,
1444                            (sm->io_res->end - sm->io_res->start) - 1);
1445
1446         if (sm->regs == NULL) {
1447                 dev_err(&dev->dev, "cannot remap registers\n");
1448                 ret = -EIO;
1449                 goto err_claim;
1450         }
1451
1452         return sm501_init_dev(sm);
1453
1454  err_claim:
1455         release_resource(sm->regs_claim);
1456         kfree(sm->regs_claim);
1457  err_res:
1458         kfree(sm);
1459  err1:
1460         return ret;
1461
1462 }
1463
1464 #ifdef CONFIG_PM
1465
1466 /* power management support */
1467
1468 static void sm501_set_power(struct sm501_devdata *sm, int on)
1469 {
1470         struct sm501_platdata *pd = sm->platdata;
1471
1472         if (pd == NULL)
1473                 return;
1474
1475         if (pd->get_power) {
1476                 if (pd->get_power(sm->dev) == on) {
1477                         dev_dbg(sm->dev, "is already %d\n", on);
1478                         return;
1479                 }
1480         }
1481
1482         if (pd->set_power) {
1483                 dev_dbg(sm->dev, "setting power to %d\n", on);
1484
1485                 pd->set_power(sm->dev, on);
1486                 sm501_mdelay(sm, 10);
1487         }
1488 }
1489
1490 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1491 {
1492         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1493
1494         sm->in_suspend = 1;
1495         sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1496
1497         sm501_dump_regs(sm);
1498
1499         if (sm->platdata) {
1500                 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1501                         sm501_set_power(sm, 0);
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int sm501_plat_resume(struct platform_device *pdev)
1508 {
1509         struct sm501_devdata *sm = platform_get_drvdata(pdev);
1510
1511         sm501_set_power(sm, 1);
1512
1513         sm501_dump_regs(sm);
1514         sm501_dump_gate(sm);
1515         sm501_dump_clk(sm);
1516
1517         /* check to see if we are in the same state as when suspended */
1518
1519         if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1520                 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1521                 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1522
1523                 /* our suspend causes the controller state to change,
1524                  * either by something attempting setup, power loss,
1525                  * or an external reset event on power change */
1526
1527                 if (sm->platdata && sm->platdata->init) {
1528                         sm501_init_regs(sm, sm->platdata->init);
1529                 }
1530         }
1531
1532         /* dump our state from resume */
1533
1534         sm501_dump_regs(sm);
1535         sm501_dump_clk(sm);
1536
1537         sm->in_suspend = 0;
1538
1539         return 0;
1540 }
1541 #else
1542 #define sm501_plat_suspend NULL
1543 #define sm501_plat_resume NULL
1544 #endif
1545
1546 /* Initialisation data for PCI devices */
1547
1548 static struct sm501_initdata sm501_pci_initdata = {
1549         .gpio_high      = {
1550                 .set    = 0x3F000000,           /* 24bit panel */
1551                 .mask   = 0x0,
1552         },
1553         .misc_timing    = {
1554                 .set    = 0x010100,             /* SDRAM timing */
1555                 .mask   = 0x1F1F00,
1556         },
1557         .misc_control   = {
1558                 .set    = SM501_MISC_PNL_24BIT,
1559                 .mask   = 0,
1560         },
1561
1562         .devices        = SM501_USE_ALL,
1563
1564         /* Errata AB-3 says that 72MHz is the fastest available
1565          * for 33MHZ PCI with proper bus-mastering operation */
1566
1567         .mclk           = 72 * MHZ,
1568         .m1xclk         = 144 * MHZ,
1569 };
1570
1571 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1572         .flags          = (SM501FB_FLAG_USE_INIT_MODE |
1573                            SM501FB_FLAG_USE_HWCURSOR |
1574                            SM501FB_FLAG_USE_HWACCEL |
1575                            SM501FB_FLAG_DISABLE_AT_EXIT),
1576 };
1577
1578 static struct sm501_platdata_fb sm501_fb_pdata = {
1579         .fb_route       = SM501_FB_OWN,
1580         .fb_crt         = &sm501_pdata_fbsub,
1581         .fb_pnl         = &sm501_pdata_fbsub,
1582 };
1583
1584 static struct sm501_platdata sm501_pci_platdata = {
1585         .init           = &sm501_pci_initdata,
1586         .fb             = &sm501_fb_pdata,
1587         .gpio_base      = -1,
1588 };
1589
1590 static int __devinit sm501_pci_probe(struct pci_dev *dev,
1591                                      const struct pci_device_id *id)
1592 {
1593         struct sm501_devdata *sm;
1594         int err;
1595
1596         sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1597         if (sm == NULL) {
1598                 dev_err(&dev->dev, "no memory for device data\n");
1599                 err = -ENOMEM;
1600                 goto err1;
1601         }
1602
1603         /* set a default set of platform data */
1604         dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1605
1606         /* set a hopefully unique id for our child platform devices */
1607         sm->pdev_id = 32 + dev->devfn;
1608
1609         pci_set_drvdata(dev, sm);
1610
1611         err = pci_enable_device(dev);
1612         if (err) {
1613                 dev_err(&dev->dev, "cannot enable device\n");
1614                 goto err2;
1615         }
1616
1617         sm->dev = &dev->dev;
1618         sm->irq = dev->irq;
1619
1620 #ifdef __BIG_ENDIAN
1621         /* if the system is big-endian, we most probably have a
1622          * translation in the IO layer making the PCI bus little endian
1623          * so make the framebuffer swapped pixels */
1624
1625         sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1626 #endif
1627
1628         /* check our resources */
1629
1630         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1631                 dev_err(&dev->dev, "region #0 is not memory?\n");
1632                 err = -EINVAL;
1633                 goto err3;
1634         }
1635
1636         if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1637                 dev_err(&dev->dev, "region #1 is not memory?\n");
1638                 err = -EINVAL;
1639                 goto err3;
1640         }
1641
1642         /* make our resources ready for sharing */
1643
1644         sm->io_res = &dev->resource[1];
1645         sm->mem_res = &dev->resource[0];
1646
1647         sm->regs_claim = request_mem_region(sm->io_res->start,
1648                                             0x100, "sm501");
1649         if (sm->regs_claim == NULL) {
1650                 dev_err(&dev->dev, "cannot claim registers\n");
1651                 err= -EBUSY;
1652                 goto err3;
1653         }
1654
1655         sm->regs = pci_ioremap_bar(dev, 1);
1656
1657         if (sm->regs == NULL) {
1658                 dev_err(&dev->dev, "cannot remap registers\n");
1659                 err = -EIO;
1660                 goto err4;
1661         }
1662
1663         sm501_init_dev(sm);
1664         return 0;
1665
1666  err4:
1667         release_resource(sm->regs_claim);
1668         kfree(sm->regs_claim);
1669  err3:
1670         pci_disable_device(dev);
1671  err2:
1672         pci_set_drvdata(dev, NULL);
1673         kfree(sm);
1674  err1:
1675         return err;
1676 }
1677
1678 static void sm501_remove_sub(struct sm501_devdata *sm,
1679                              struct sm501_device *smdev)
1680 {
1681         list_del(&smdev->list);
1682         platform_device_unregister(&smdev->pdev);
1683 }
1684
1685 static void sm501_dev_remove(struct sm501_devdata *sm)
1686 {
1687         struct sm501_device *smdev, *tmp;
1688
1689         list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1690                 sm501_remove_sub(sm, smdev);
1691
1692         device_remove_file(sm->dev, &dev_attr_dbg_regs);
1693
1694         sm501_gpio_remove(sm);
1695 }
1696
1697 static void __devexit sm501_pci_remove(struct pci_dev *dev)
1698 {
1699         struct sm501_devdata *sm = pci_get_drvdata(dev);
1700
1701         sm501_dev_remove(sm);
1702         iounmap(sm->regs);
1703
1704         release_resource(sm->regs_claim);
1705         kfree(sm->regs_claim);
1706
1707         pci_set_drvdata(dev, NULL);
1708         pci_disable_device(dev);
1709 }
1710
1711 static int sm501_plat_remove(struct platform_device *dev)
1712 {
1713         struct sm501_devdata *sm = platform_get_drvdata(dev);
1714
1715         sm501_dev_remove(sm);
1716         iounmap(sm->regs);
1717
1718         release_resource(sm->regs_claim);
1719         kfree(sm->regs_claim);
1720
1721         return 0;
1722 }
1723
1724 static struct pci_device_id sm501_pci_tbl[] = {
1725         { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1726         { 0, },
1727 };
1728
1729 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1730
1731 static struct pci_driver sm501_pci_driver = {
1732         .name           = "sm501",
1733         .id_table       = sm501_pci_tbl,
1734         .probe          = sm501_pci_probe,
1735         .remove         = __devexit_p(sm501_pci_remove),
1736 };
1737
1738 MODULE_ALIAS("platform:sm501");
1739
1740 static struct platform_driver sm501_plat_driver = {
1741         .driver         = {
1742                 .name   = "sm501",
1743                 .owner  = THIS_MODULE,
1744         },
1745         .probe          = sm501_plat_probe,
1746         .remove         = sm501_plat_remove,
1747         .suspend        = sm501_plat_suspend,
1748         .resume         = sm501_plat_resume,
1749 };
1750
1751 static int __init sm501_base_init(void)
1752 {
1753         platform_driver_register(&sm501_plat_driver);
1754         return pci_register_driver(&sm501_pci_driver);
1755 }
1756
1757 static void __exit sm501_base_exit(void)
1758 {
1759         platform_driver_unregister(&sm501_plat_driver);
1760         pci_unregister_driver(&sm501_pci_driver);
1761 }
1762
1763 module_init(sm501_base_init);
1764 module_exit(sm501_base_exit);
1765
1766 MODULE_DESCRIPTION("SM501 Core Driver");
1767 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1768 MODULE_LICENSE("GPL v2");