2 * Toshiba TC6393XB SoC support
4 * Copyright(c) 2005-2006 Chris Humbert
5 * Copyright(c) 2005 Dirk Opfer
6 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
7 * Copyright(c) 2007 Dmitry Baryshkov
9 * Based on code written by Sharp/Lineo for 2.4 kernels
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mfd/tc6393xb.h>
27 #include <linux/gpio.h>
29 #define SCR_REVID 0x08 /* b Revision ID */
30 #define SCR_ISR 0x50 /* b Interrupt Status */
31 #define SCR_IMR 0x52 /* b Interrupt Mask */
32 #define SCR_IRR 0x54 /* b Interrupt Routing */
33 #define SCR_GPER 0x60 /* w GP Enable */
34 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
35 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
36 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
37 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
38 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
39 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
40 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
41 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
42 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
43 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
44 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
45 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
46 #define SCR_CCR 0x98 /* w Clock Control */
47 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
48 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
49 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
50 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
51 #define SCR_FER 0xe0 /* b Function Enable */
52 #define SCR_MCR 0xe4 /* w Mode Control */
53 #define SCR_CONFIG 0xfc /* b Configuration Control */
54 #define SCR_DEBUG 0xff /* b Debug */
56 #define SCR_CCR_CK32K BIT(0)
57 #define SCR_CCR_USBCK BIT(1)
58 #define SCR_CCR_UNK1 BIT(4)
59 #define SCR_CCR_MCLK_MASK (7 << 8)
60 #define SCR_CCR_MCLK_OFF (0 << 8)
61 #define SCR_CCR_MCLK_12 (1 << 8)
62 #define SCR_CCR_MCLK_24 (2 << 8)
63 #define SCR_CCR_MCLK_48 (3 << 8)
64 #define SCR_CCR_HCLK_MASK (3 << 12)
65 #define SCR_CCR_HCLK_24 (0 << 12)
66 #define SCR_CCR_HCLK_48 (1 << 12)
68 #define SCR_FER_USBEN BIT(0) /* USB host enable */
69 #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
70 #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
72 #define SCR_MCR_RDY_MASK (3 << 0)
73 #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
74 #define SCR_MCR_RDY_TRISTATE (1 << 0)
75 #define SCR_MCR_RDY_PUSHPULL (2 << 0)
76 #define SCR_MCR_RDY_UNK BIT(2)
77 #define SCR_MCR_RDY_EN BIT(3)
78 #define SCR_MCR_INT_MASK (3 << 4)
79 #define SCR_MCR_INT_OPENDRAIN (0 << 4)
80 #define SCR_MCR_INT_TRISTATE (1 << 4)
81 #define SCR_MCR_INT_PUSHPULL (2 << 4)
82 #define SCR_MCR_INT_UNK BIT(6)
83 #define SCR_MCR_INT_EN BIT(7)
84 /* bits 8 - 16 are unknown */
86 #define TC_GPIO_BIT(i) (1 << (i & 0x7))
88 /*--------------------------------------------------------------------------*/
93 struct gpio_chip gpio;
95 struct clk *clk; /* 3,6 Mhz */
97 spinlock_t lock; /* protects RMW cycles */
107 struct resource rscr;
108 struct resource *iomem;
120 /*--------------------------------------------------------------------------*/
122 static int tc6393xb_nand_enable(struct platform_device *nand)
124 struct platform_device *dev = to_platform_device(nand->dev.parent);
125 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
128 spin_lock_irqsave(&tc6393xb->lock, flags);
131 dev_dbg(&dev->dev, "SMD buffer on\n");
132 tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
134 spin_unlock_irqrestore(&tc6393xb->lock, flags);
139 static struct resource __devinitdata tc6393xb_nand_resources[] = {
143 .flags = IORESOURCE_MEM,
148 .flags = IORESOURCE_MEM,
151 .start = IRQ_TC6393_NAND,
152 .end = IRQ_TC6393_NAND,
153 .flags = IORESOURCE_IRQ,
157 static struct resource __devinitdata tc6393xb_mmc_resources[] = {
161 .flags = IORESOURCE_MEM,
164 .start = IRQ_TC6393_MMC,
165 .end = IRQ_TC6393_MMC,
166 .flags = IORESOURCE_IRQ,
170 static const struct resource tc6393xb_ohci_resources[] = {
174 .flags = IORESOURCE_MEM,
179 .flags = IORESOURCE_MEM,
184 .flags = IORESOURCE_MEM,
189 .flags = IORESOURCE_MEM,
192 .start = IRQ_TC6393_OHCI,
193 .end = IRQ_TC6393_OHCI,
194 .flags = IORESOURCE_IRQ,
198 static struct resource __devinitdata tc6393xb_fb_resources[] = {
202 .flags = IORESOURCE_MEM,
207 .flags = IORESOURCE_MEM,
212 .flags = IORESOURCE_MEM,
215 .start = IRQ_TC6393_FB,
216 .end = IRQ_TC6393_FB,
217 .flags = IORESOURCE_IRQ,
221 static int tc6393xb_ohci_enable(struct platform_device *dev)
223 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
228 spin_lock_irqsave(&tc6393xb->lock, flags);
230 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
231 ccr |= SCR_CCR_USBCK;
232 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
234 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
235 fer |= SCR_FER_USBEN;
236 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
238 spin_unlock_irqrestore(&tc6393xb->lock, flags);
243 static int tc6393xb_ohci_disable(struct platform_device *dev)
245 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
250 spin_lock_irqsave(&tc6393xb->lock, flags);
252 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
253 fer &= ~SCR_FER_USBEN;
254 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
256 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
257 ccr &= ~SCR_CCR_USBCK;
258 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
260 spin_unlock_irqrestore(&tc6393xb->lock, flags);
265 static int tc6393xb_fb_enable(struct platform_device *dev)
267 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
271 spin_lock_irqsave(&tc6393xb->lock, flags);
273 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
274 ccr &= ~SCR_CCR_MCLK_MASK;
275 ccr |= SCR_CCR_MCLK_48;
276 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
278 spin_unlock_irqrestore(&tc6393xb->lock, flags);
283 static int tc6393xb_fb_disable(struct platform_device *dev)
285 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
289 spin_lock_irqsave(&tc6393xb->lock, flags);
291 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
292 ccr &= ~SCR_CCR_MCLK_MASK;
293 ccr |= SCR_CCR_MCLK_OFF;
294 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
296 spin_unlock_irqrestore(&tc6393xb->lock, flags);
301 int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
303 struct platform_device *dev = to_platform_device(fb->dev.parent);
304 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
308 spin_lock_irqsave(&tc6393xb->lock, flags);
310 fer = ioread8(tc6393xb->scr + SCR_FER);
312 fer |= SCR_FER_SLCDEN;
314 fer &= ~SCR_FER_SLCDEN;
315 iowrite8(fer, tc6393xb->scr + SCR_FER);
317 spin_unlock_irqrestore(&tc6393xb->lock, flags);
321 EXPORT_SYMBOL(tc6393xb_lcd_set_power);
323 int tc6393xb_lcd_mode(struct platform_device *fb,
324 const struct fb_videomode *mode) {
325 struct platform_device *dev = to_platform_device(fb->dev.parent);
326 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
329 spin_lock_irqsave(&tc6393xb->lock, flags);
331 iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
332 iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
334 spin_unlock_irqrestore(&tc6393xb->lock, flags);
338 EXPORT_SYMBOL(tc6393xb_lcd_mode);
340 static int tc6393xb_mmc_enable(struct platform_device *mmc)
342 struct platform_device *dev = to_platform_device(mmc->dev.parent);
343 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
345 tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
346 tc6393xb_mmc_resources[0].start & 0xfffe);
351 static int tc6393xb_mmc_resume(struct platform_device *mmc)
353 struct platform_device *dev = to_platform_device(mmc->dev.parent);
354 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
356 tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
357 tc6393xb_mmc_resources[0].start & 0xfffe);
362 static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
364 struct platform_device *dev = to_platform_device(mmc->dev.parent);
365 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
367 tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
370 static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
372 struct platform_device *dev = to_platform_device(mmc->dev.parent);
373 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
375 tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
378 static struct tmio_mmc_data tc6393xb_mmc_data = {
380 .set_pwr = tc6393xb_mmc_pwr,
381 .set_clk_div = tc6393xb_mmc_clk_div,
384 static struct mfd_cell __devinitdata tc6393xb_cells[] = {
385 [TC6393XB_CELL_NAND] = {
387 .enable = tc6393xb_nand_enable,
388 .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
389 .resources = tc6393xb_nand_resources,
391 [TC6393XB_CELL_MMC] = {
393 .enable = tc6393xb_mmc_enable,
394 .resume = tc6393xb_mmc_resume,
395 .driver_data = &tc6393xb_mmc_data,
396 .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
397 .resources = tc6393xb_mmc_resources,
399 [TC6393XB_CELL_OHCI] = {
401 .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
402 .resources = tc6393xb_ohci_resources,
403 .enable = tc6393xb_ohci_enable,
404 .suspend = tc6393xb_ohci_disable,
405 .resume = tc6393xb_ohci_enable,
406 .disable = tc6393xb_ohci_disable,
408 [TC6393XB_CELL_FB] = {
410 .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
411 .resources = tc6393xb_fb_resources,
412 .enable = tc6393xb_fb_enable,
413 .suspend = tc6393xb_fb_disable,
414 .resume = tc6393xb_fb_enable,
415 .disable = tc6393xb_fb_disable,
419 /*--------------------------------------------------------------------------*/
421 static int tc6393xb_gpio_get(struct gpio_chip *chip,
424 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
426 /* XXX: does dsr also represent inputs? */
427 return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
428 & TC_GPIO_BIT(offset);
431 static void __tc6393xb_gpio_set(struct gpio_chip *chip,
432 unsigned offset, int value)
434 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
437 dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
439 dsr |= TC_GPIO_BIT(offset);
441 dsr &= ~TC_GPIO_BIT(offset);
443 tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
446 static void tc6393xb_gpio_set(struct gpio_chip *chip,
447 unsigned offset, int value)
449 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
452 spin_lock_irqsave(&tc6393xb->lock, flags);
454 __tc6393xb_gpio_set(chip, offset, value);
456 spin_unlock_irqrestore(&tc6393xb->lock, flags);
459 static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
462 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
466 spin_lock_irqsave(&tc6393xb->lock, flags);
468 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
469 doecr &= ~TC_GPIO_BIT(offset);
470 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
472 spin_unlock_irqrestore(&tc6393xb->lock, flags);
477 static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
478 unsigned offset, int value)
480 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
484 spin_lock_irqsave(&tc6393xb->lock, flags);
486 __tc6393xb_gpio_set(chip, offset, value);
488 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
489 doecr |= TC_GPIO_BIT(offset);
490 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
492 spin_unlock_irqrestore(&tc6393xb->lock, flags);
497 static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
499 tc6393xb->gpio.label = "tc6393xb";
500 tc6393xb->gpio.base = gpio_base;
501 tc6393xb->gpio.ngpio = 16;
502 tc6393xb->gpio.set = tc6393xb_gpio_set;
503 tc6393xb->gpio.get = tc6393xb_gpio_get;
504 tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
505 tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
507 return gpiochip_add(&tc6393xb->gpio);
510 /*--------------------------------------------------------------------------*/
513 tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
515 struct tc6393xb *tc6393xb = get_irq_data(irq);
517 unsigned int i, irq_base;
519 irq_base = tc6393xb->irq_base;
521 while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
522 ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
523 for (i = 0; i < TC6393XB_NR_IRQS; i++) {
525 generic_handle_irq(irq_base + i);
529 static void tc6393xb_irq_ack(unsigned int irq)
533 static void tc6393xb_irq_mask(unsigned int irq)
535 struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
539 spin_lock_irqsave(&tc6393xb->lock, flags);
540 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
541 imr |= 1 << (irq - tc6393xb->irq_base);
542 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
543 spin_unlock_irqrestore(&tc6393xb->lock, flags);
546 static void tc6393xb_irq_unmask(unsigned int irq)
548 struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
552 spin_lock_irqsave(&tc6393xb->lock, flags);
553 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
554 imr &= ~(1 << (irq - tc6393xb->irq_base));
555 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
556 spin_unlock_irqrestore(&tc6393xb->lock, flags);
559 static struct irq_chip tc6393xb_chip = {
561 .ack = tc6393xb_irq_ack,
562 .mask = tc6393xb_irq_mask,
563 .unmask = tc6393xb_irq_unmask,
566 static void tc6393xb_attach_irq(struct platform_device *dev)
568 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
569 unsigned int irq, irq_base;
571 irq_base = tc6393xb->irq_base;
573 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
574 set_irq_chip(irq, &tc6393xb_chip);
575 set_irq_chip_data(irq, tc6393xb);
576 set_irq_handler(irq, handle_edge_irq);
577 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
580 set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
581 set_irq_data(tc6393xb->irq, tc6393xb);
582 set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
585 static void tc6393xb_detach_irq(struct platform_device *dev)
587 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
588 unsigned int irq, irq_base;
590 set_irq_chained_handler(tc6393xb->irq, NULL);
591 set_irq_data(tc6393xb->irq, NULL);
593 irq_base = tc6393xb->irq_base;
595 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
596 set_irq_flags(irq, 0);
597 set_irq_chip(irq, NULL);
598 set_irq_chip_data(irq, NULL);
602 /*--------------------------------------------------------------------------*/
604 static int __devinit tc6393xb_probe(struct platform_device *dev)
606 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
607 struct tc6393xb *tc6393xb;
608 struct resource *iomem, *rscr;
611 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
615 tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
621 spin_lock_init(&tc6393xb->lock);
623 platform_set_drvdata(dev, tc6393xb);
625 ret = platform_get_irq(dev, 0);
631 tc6393xb->iomem = iomem;
632 tc6393xb->irq_base = tcpd->irq_base;
634 tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
635 if (IS_ERR(tc6393xb->clk)) {
636 ret = PTR_ERR(tc6393xb->clk);
640 rscr = &tc6393xb->rscr;
641 rscr->name = "tc6393xb-core";
642 rscr->start = iomem->start;
643 rscr->end = iomem->start + 0xff;
644 rscr->flags = IORESOURCE_MEM;
646 ret = request_resource(iomem, rscr);
648 goto err_request_scr;
650 tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
651 if (!tc6393xb->scr) {
656 ret = clk_enable(tc6393xb->clk);
660 ret = tcpd->enable(dev);
664 iowrite8(0, tc6393xb->scr + SCR_FER);
665 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
666 iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
667 tc6393xb->scr + SCR_CCR);
668 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
669 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
670 BIT(15), tc6393xb->scr + SCR_MCR);
671 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
672 iowrite8(0, tc6393xb->scr + SCR_IRR);
673 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
675 printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
676 tmio_ioread8(tc6393xb->scr + SCR_REVID),
677 (unsigned long) iomem->start, tc6393xb->irq);
679 tc6393xb->gpio.base = -1;
681 if (tcpd->gpio_base >= 0) {
682 ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
687 tc6393xb_attach_irq(dev);
690 ret = tcpd->setup(dev);
695 tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data;
696 tc6393xb_cells[TC6393XB_CELL_NAND].platform_data =
697 &tc6393xb_cells[TC6393XB_CELL_NAND];
698 tc6393xb_cells[TC6393XB_CELL_NAND].data_size =
699 sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]);
701 tc6393xb_cells[TC6393XB_CELL_MMC].platform_data =
702 &tc6393xb_cells[TC6393XB_CELL_MMC];
703 tc6393xb_cells[TC6393XB_CELL_MMC].data_size =
704 sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]);
706 tc6393xb_cells[TC6393XB_CELL_OHCI].platform_data =
707 &tc6393xb_cells[TC6393XB_CELL_OHCI];
708 tc6393xb_cells[TC6393XB_CELL_OHCI].data_size =
709 sizeof(tc6393xb_cells[TC6393XB_CELL_OHCI]);
711 tc6393xb_cells[TC6393XB_CELL_FB].driver_data = tcpd->fb_data;
712 tc6393xb_cells[TC6393XB_CELL_FB].platform_data =
713 &tc6393xb_cells[TC6393XB_CELL_FB];
714 tc6393xb_cells[TC6393XB_CELL_FB].data_size =
715 sizeof(tc6393xb_cells[TC6393XB_CELL_FB]);
717 ret = mfd_add_devices(&dev->dev, dev->id,
718 tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
719 iomem, tcpd->irq_base);
728 tc6393xb_detach_irq(dev);
731 if (tc6393xb->gpio.base != -1)
732 temp = gpiochip_remove(&tc6393xb->gpio);
735 clk_disable(tc6393xb->clk);
737 iounmap(tc6393xb->scr);
739 release_resource(&tc6393xb->rscr);
741 clk_put(tc6393xb->clk);
749 static int __devexit tc6393xb_remove(struct platform_device *dev)
751 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
752 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
755 mfd_remove_devices(&dev->dev);
760 tc6393xb_detach_irq(dev);
762 if (tc6393xb->gpio.base != -1) {
763 ret = gpiochip_remove(&tc6393xb->gpio);
765 dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
770 ret = tcpd->disable(dev);
771 clk_disable(tc6393xb->clk);
772 iounmap(tc6393xb->scr);
773 release_resource(&tc6393xb->rscr);
774 platform_set_drvdata(dev, NULL);
775 clk_put(tc6393xb->clk);
782 static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
784 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
785 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
788 tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
789 tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
791 for (i = 0; i < 3; i++) {
792 tc6393xb->suspend_state.gpo_dsr[i] =
793 ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
794 tc6393xb->suspend_state.gpo_doecr[i] =
795 ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
796 tc6393xb->suspend_state.gpi_bcr[i] =
797 ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
799 ret = tcpd->suspend(dev);
800 clk_disable(tc6393xb->clk);
805 static int tc6393xb_resume(struct platform_device *dev)
807 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
808 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
812 clk_enable(tc6393xb->clk);
814 ret = tcpd->resume(dev);
818 if (!tcpd->resume_restore)
821 iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
822 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
823 iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
824 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
825 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
826 BIT(15), tc6393xb->scr + SCR_MCR);
827 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
828 iowrite8(0, tc6393xb->scr + SCR_IRR);
829 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
831 for (i = 0; i < 3; i++) {
832 iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
833 tc6393xb->scr + SCR_GPO_DSR(i));
834 iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
835 tc6393xb->scr + SCR_GPO_DOECR(i));
836 iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
837 tc6393xb->scr + SCR_GPI_BCR(i));
843 #define tc6393xb_suspend NULL
844 #define tc6393xb_resume NULL
847 static struct platform_driver tc6393xb_driver = {
848 .probe = tc6393xb_probe,
849 .remove = __devexit_p(tc6393xb_remove),
850 .suspend = tc6393xb_suspend,
851 .resume = tc6393xb_resume,
855 .owner = THIS_MODULE,
859 static int __init tc6393xb_init(void)
861 return platform_driver_register(&tc6393xb_driver);
864 static void __exit tc6393xb_exit(void)
866 platform_driver_unregister(&tc6393xb_driver);
869 subsys_initcall(tc6393xb_init);
870 module_exit(tc6393xb_exit);
872 MODULE_LICENSE("GPL v2");
873 MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
874 MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
875 MODULE_ALIAS("platform:tc6393xb");