2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/export.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/slab.h>
37 #include <linux/irqdomain.h>
38 #include <linux/i2c/twl.h>
43 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
44 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
45 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
46 * SIH modules are more traditional IRQ components, which support per-IRQ
47 * enable/disable and trigger controls; they do most of the work.
49 * These chips are designed to support IRQ handling from two different
50 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
51 * and mask registers in the PIH and SIH modules.
53 * We set up IRQs starting at a platform-specified base, always starting
54 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
55 * base + 0 .. base + 7 PIH
56 * base + 8 .. base + 15 SIH for PWR_INT
57 * base + 16 .. base + 33 SIH for GPIO
59 #define TWL4030_CORE_NR_IRQS 8
60 #define TWL4030_PWR_NR_IRQS 8
62 /* PIH register offsets */
63 #define REG_PIH_ISR_P1 0x01
64 #define REG_PIH_ISR_P2 0x02
65 #define REG_PIH_SIR 0x03 /* for testing */
67 /* Linux could (eventually) use either IRQ line */
72 u8 module; /* module id */
73 u8 control_offset; /* for SIH_CTRL */
76 u8 bits; /* valid in isr/imr */
77 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
80 u8 bytes_edr; /* bytelen of EDR */
82 u8 irq_lines; /* number of supported irq lines */
84 /* SIR ignored -- set interrupt, for testing only */
89 /* + 2 bytes padding */
92 static const struct sih *sih_modules;
93 static int nr_sih_modules;
95 #define SIH_INITIALIZER(modname, nbits) \
96 .module = TWL4030_MODULE_ ## modname, \
97 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
99 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
100 .edr_offset = TWL4030_ ## modname ## _EDR, \
101 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
104 .isr_offset = TWL4030_ ## modname ## _ISR1, \
105 .imr_offset = TWL4030_ ## modname ## _IMR1, \
108 .isr_offset = TWL4030_ ## modname ## _ISR2, \
109 .imr_offset = TWL4030_ ## modname ## _IMR2, \
112 /* register naming policies are inconsistent ... */
113 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
114 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
115 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
119 * Order in this table matches order in PIH_ISR. That is,
120 * BIT(n) in PIH_ISR is sih_modules[n].
122 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
123 static const struct sih sih_modules_twl4030[6] = {
126 .module = TWL4030_MODULE_GPIO,
127 .control_offset = REG_GPIO_SIH_CTRL,
129 .bits = TWL4030_GPIO_MAX,
131 /* Note: *all* of these IRQs default to no-trigger */
132 .edr_offset = REG_GPIO_EDR1,
136 .isr_offset = REG_GPIO_ISR1A,
137 .imr_offset = REG_GPIO_IMR1A,
139 .isr_offset = REG_GPIO_ISR1B,
140 .imr_offset = REG_GPIO_IMR1B,
146 SIH_INITIALIZER(KEYPAD_KEYP, 4)
150 .module = TWL4030_MODULE_INTERRUPTS,
151 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
155 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
156 /* Note: most of these IRQs default to no-trigger */
160 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
161 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
163 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
164 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
169 SIH_INITIALIZER(MADC, 4)
172 /* USB doesn't use the same SIH organization */
178 SIH_INITIALIZER(INT_PWR, 8)
180 /* there are no SIH modules #6 or #7 ... */
183 static const struct sih sih_modules_twl5031[8] = {
186 .module = TWL4030_MODULE_GPIO,
187 .control_offset = REG_GPIO_SIH_CTRL,
189 .bits = TWL4030_GPIO_MAX,
191 /* Note: *all* of these IRQs default to no-trigger */
192 .edr_offset = REG_GPIO_EDR1,
196 .isr_offset = REG_GPIO_ISR1A,
197 .imr_offset = REG_GPIO_IMR1A,
199 .isr_offset = REG_GPIO_ISR1B,
200 .imr_offset = REG_GPIO_IMR1B,
206 SIH_INITIALIZER(KEYPAD_KEYP, 4)
210 .module = TWL5031_MODULE_INTERRUPTS,
211 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
214 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
215 /* Note: most of these IRQs default to no-trigger */
219 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
220 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
222 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
223 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
228 SIH_INITIALIZER(MADC, 4)
231 /* USB doesn't use the same SIH organization */
237 SIH_INITIALIZER(INT_PWR, 8)
241 * ECI/DBI doesn't use the same SIH organization.
242 * For example, it supports only one interrupt output line.
243 * That is, the interrupts are seen on both INT1 and INT2 lines.
246 .module = TWL5031_MODULE_ACCESSORY,
251 .isr_offset = TWL5031_ACIIDR_LSB,
252 .imr_offset = TWL5031_ACIIMR_LSB,
257 /* Audio accessory */
259 .module = TWL5031_MODULE_ACCESSORY,
260 .control_offset = TWL5031_ACCSIHCTRL,
263 .edr_offset = TWL5031_ACCEDR1,
264 /* Note: most of these IRQs default to no-trigger */
268 .isr_offset = TWL5031_ACCISR1,
269 .imr_offset = TWL5031_ACCIMR1,
271 .isr_offset = TWL5031_ACCISR2,
272 .imr_offset = TWL5031_ACCIMR2,
277 #undef TWL4030_MODULE_KEYPAD_KEYP
278 #undef TWL4030_MODULE_INT_PWR
279 #undef TWL4030_INT_PWR_EDR
281 /*----------------------------------------------------------------------*/
283 static unsigned twl4030_irq_base;
286 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
287 * This is a chained interrupt, so there is no desc->action method for it.
288 * Now we need to query the interrupt controller in the twl4030 to determine
289 * which module is generating the interrupt request. However, we can't do i2c
290 * transactions in interrupt context, so we must defer that work to a kernel
291 * thread. All we do here is acknowledge and mask the interrupt and wakeup
294 static irqreturn_t handle_twl4030_pih(int irq, void *devid)
300 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
303 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret);
307 /* these handlers deal with the relevant SIH irq status */
308 for (module_irq = twl4030_irq_base;
310 pih_isr >>= 1, module_irq++) {
312 handle_nested_irq(module_irq);
318 /*----------------------------------------------------------------------*/
321 * twl4030_init_sih_modules() ... start from a known state where no
322 * IRQs will be coming in, and where we can quickly enable them then
323 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
325 * NOTE: we don't touch EDR registers here; they stay with hardware
326 * defaults or whatever the last value was. Note that when both EDR
327 * bits for an IRQ are clear, that's as if its IMR bit is set...
329 static int twl4030_init_sih_modules(unsigned line)
331 const struct sih *sih;
336 /* line 0 == int1_n signal; line 1 == int2_n signal */
342 /* disable all interrupts on our line */
343 memset(buf, 0xff, sizeof buf);
345 for (i = 0; i < nr_sih_modules; i++, sih++) {
346 /* skip USB -- it's funky */
350 /* Not all the SIH modules support multiple interrupt lines */
351 if (sih->irq_lines <= line)
354 status = twl_i2c_write(sih->module, buf,
355 sih->mask[line].imr_offset, sih->bytes_ixr);
357 pr_err("twl4030: err %d initializing %s %s\n",
358 status, sih->name, "IMR");
361 * Maybe disable "exclusive" mode; buffer second pending irq;
362 * set Clear-On-Read (COR) bit.
364 * NOTE that sometimes COR polarity is documented as being
365 * inverted: for MADC, COR=1 means "clear on write".
366 * And for PWR_INT it's not documented...
369 status = twl_i2c_write_u8(sih->module,
370 TWL4030_SIH_CTRL_COR_MASK,
371 sih->control_offset);
373 pr_err("twl4030: err %d initializing %s %s\n",
374 status, sih->name, "SIH_CTRL");
379 for (i = 0; i < nr_sih_modules; i++, sih++) {
387 /* Not all the SIH modules support multiple interrupt lines */
388 if (sih->irq_lines <= line)
392 * Clear pending interrupt status. Either the read was
393 * enough, or we need to write those bits. Repeat, in
394 * case an IRQ is pending (PENDDIS=0) ... that's not
395 * uncommon with PWR_INT.PWRON.
397 for (j = 0; j < 2; j++) {
398 status = twl_i2c_read(sih->module, rxbuf,
399 sih->mask[line].isr_offset, sih->bytes_ixr);
401 pr_err("twl4030: err %d initializing %s %s\n",
402 status, sih->name, "ISR");
405 status = twl_i2c_write(sih->module, buf,
406 sih->mask[line].isr_offset,
409 * else COR=1 means read sufficed.
410 * (for most SIH modules...)
418 static inline void activate_irq(int irq)
422 * ARM requires an extra step to clear IRQ_NOREQUEST, which it
423 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
425 set_irq_flags(irq, IRQF_VALID);
427 /* same effect on other architectures */
428 irq_set_noprobe(irq);
432 /*----------------------------------------------------------------------*/
436 const struct sih *sih;
439 bool imr_change_pending;
443 struct mutex irq_lock;
447 /*----------------------------------------------------------------------*/
450 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
451 * which can't perform the underlying I2C operations (because they sleep).
452 * So we must hand them off to a thread (workqueue) and cope with asynch
453 * completion, potentially including some re-ordering, of these requests.
456 static void twl4030_sih_mask(struct irq_data *data)
458 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
460 agent->imr |= BIT(data->irq - agent->irq_base);
461 agent->imr_change_pending = true;
464 static void twl4030_sih_unmask(struct irq_data *data)
466 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
468 agent->imr &= ~BIT(data->irq - agent->irq_base);
469 agent->imr_change_pending = true;
472 static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
474 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
476 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
479 if (irqd_get_trigger_type(data) != trigger)
480 agent->edge_change |= BIT(data->irq - agent->irq_base);
485 static void twl4030_sih_bus_lock(struct irq_data *data)
487 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
489 mutex_lock(&agent->irq_lock);
492 static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
494 struct sih_agent *agent = irq_data_get_irq_chip_data(data);
495 const struct sih *sih = agent->sih;
498 if (agent->imr_change_pending) {
504 /* byte[0] gets overwritten as we write ... */
505 imr.word = cpu_to_le32(agent->imr << 8);
506 agent->imr_change_pending = false;
508 /* write the whole mask ... simpler than subsetting it */
509 status = twl_i2c_write(sih->module, imr.bytes,
510 sih->mask[irq_line].imr_offset,
513 pr_err("twl4030: %s, %s --> %d\n", __func__,
517 if (agent->edge_change) {
521 edge_change = agent->edge_change;
522 agent->edge_change = 0;
525 * Read, reserving first byte for write scratch. Yes, this
526 * could be cached for some speedup ... but be careful about
527 * any processor on the other IRQ line, EDR registers are
530 status = twl_i2c_read(sih->module, bytes + 1,
531 sih->edr_offset, sih->bytes_edr);
533 pr_err("twl4030: %s, %s --> %d\n", __func__,
538 /* Modify only the bits we know must change */
539 while (edge_change) {
540 int i = fls(edge_change) - 1;
541 struct irq_data *idata;
542 int byte = 1 + (i >> 2);
543 int off = (i & 0x3) * 2;
546 idata = irq_get_irq_data(i + agent->irq_base);
548 bytes[byte] &= ~(0x03 << off);
550 type = irqd_get_trigger_type(idata);
551 if (type & IRQ_TYPE_EDGE_RISING)
552 bytes[byte] |= BIT(off + 1);
553 if (type & IRQ_TYPE_EDGE_FALLING)
554 bytes[byte] |= BIT(off + 0);
556 edge_change &= ~BIT(i);
560 status = twl_i2c_write(sih->module, bytes,
561 sih->edr_offset, sih->bytes_edr);
563 pr_err("twl4030: %s, %s --> %d\n", __func__,
567 mutex_unlock(&agent->irq_lock);
570 static struct irq_chip twl4030_sih_irq_chip = {
572 .irq_mask = twl4030_sih_mask,
573 .irq_unmask = twl4030_sih_unmask,
574 .irq_set_type = twl4030_sih_set_type,
575 .irq_bus_lock = twl4030_sih_bus_lock,
576 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
579 /*----------------------------------------------------------------------*/
581 static inline int sih_read_isr(const struct sih *sih)
589 /* FIXME need retry-on-error ... */
592 status = twl_i2c_read(sih->module, isr.bytes,
593 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
595 return (status < 0) ? status : le32_to_cpu(isr.word);
599 * Generic handler for SIH interrupts ... we "know" this is called
600 * in task context, with IRQs enabled.
602 static irqreturn_t handle_twl4030_sih(int irq, void *data)
604 struct sih_agent *agent = irq_get_handler_data(irq);
605 const struct sih *sih = agent->sih;
608 /* reading ISR acks the IRQs, using clear-on-read mode */
609 isr = sih_read_isr(sih);
612 pr_err("twl4030: %s SIH, read ISR error %d\n",
614 /* REVISIT: recover; eventually mask it all, etc */
624 handle_nested_irq(agent->irq_base + irq);
626 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
632 /* returns the first IRQ used by this SIH bank, or negative errno */
633 int twl4030_sih_setup(struct device *dev, int module, int irq_base)
636 const struct sih *sih = NULL;
637 struct sih_agent *agent;
639 int status = -EINVAL;
641 /* only support modules with standard clear-on-read for now */
642 for (sih_mod = 0, sih = sih_modules;
643 sih_mod < nr_sih_modules;
645 if (sih->module == module && sih->set_cor) {
653 agent = kzalloc(sizeof *agent, GFP_KERNEL);
657 agent->irq_base = irq_base;
660 mutex_init(&agent->irq_lock);
662 for (i = 0; i < sih->bits; i++) {
665 irq_set_chip_data(irq, agent);
666 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
668 irq_set_nested_thread(irq, 1);
672 /* replace generic PIH handler (handle_simple_irq) */
673 irq = sih_mod + twl4030_irq_base;
674 irq_set_handler_data(irq, agent);
675 agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
676 status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
677 agent->irq_name ?: sih->name, NULL);
679 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
680 irq, irq_base, irq_base + i - 1);
682 return status < 0 ? status : irq_base;
685 /* FIXME need a call to reverse twl4030_sih_setup() ... */
687 /*----------------------------------------------------------------------*/
689 /* FIXME pass in which interrupt line we'll use ... */
690 #define twl_irq_line 0
692 int twl4030_init_irq(struct device *dev, int irq_num)
694 static struct irq_chip twl4030_irq_chip;
695 int irq_base, irq_end, nr_irqs;
696 struct device_node *node = dev->of_node;
702 * TWL core and pwr interrupts must be contiguous because
703 * the hwirqs numbers are defined contiguously from 1 to 15.
704 * Create only one domain for both.
706 nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
708 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
709 if (IS_ERR_VALUE(irq_base)) {
710 dev_err(dev, "Fail to allocate IRQ descs\n");
714 irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
715 &irq_domain_simple_ops, NULL);
717 irq_end = irq_base + TWL4030_CORE_NR_IRQS;
720 * Mask and clear all TWL4030 interrupts since initially we do
721 * not have any TWL4030 module interrupt handlers present
723 status = twl4030_init_sih_modules(twl_irq_line);
727 twl4030_irq_base = irq_base;
730 * install an irq handler for each of the SIH modules;
731 * clone dummy irq_chip since PIH can't *do* anything
733 twl4030_irq_chip = dummy_irq_chip;
734 twl4030_irq_chip.name = "twl4030";
736 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
738 for (i = irq_base; i < irq_end; i++) {
739 irq_set_chip_and_handler(i, &twl4030_irq_chip,
741 irq_set_nested_thread(i, 1);
745 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
746 irq_num, irq_base, irq_end);
748 /* ... and the PWR_INT module ... */
749 status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
751 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
755 /* install an irq handler to demultiplex the TWL4030 interrupt */
756 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
758 "TWL4030-PIH", NULL);
760 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
766 /* clean up twl4030_sih_setup */
768 for (i = irq_base; i < irq_end; i++) {
769 irq_set_nested_thread(i, 0);
770 irq_set_chip_and_handler(i, NULL, NULL);
776 int twl4030_exit_irq(void)
778 /* FIXME undo twl_init_irq() */
779 if (twl4030_irq_base) {
780 pr_err("twl4030: can't yet clean up IRQs?\n");
786 int twl4030_init_chip_irq(const char *chip)
788 if (!strcmp(chip, "twl5031")) {
789 sih_modules = sih_modules_twl5031;
790 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
792 sih_modules = sih_modules_twl4030;
793 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);