2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
4 * Copyright 2009 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/irq.h>
19 #include <linux/mfd/core.h>
20 #include <linux/interrupt.h>
22 #include <linux/mfd/wm831x/core.h>
23 #include <linux/mfd/wm831x/pdata.h>
24 #include <linux/mfd/wm831x/gpio.h>
25 #include <linux/mfd/wm831x/irq.h>
27 #include <linux/delay.h>
30 * Since generic IRQs don't currently support interrupt controllers on
31 * interrupt driven buses we don't use genirq but instead provide an
32 * interface that looks very much like the standard ones. This leads
33 * to some bodges, including storing interrupt handler information in
34 * the static irq_data table we use to look up the data for individual
35 * interrupts, but hopefully won't last too long.
38 struct wm831x_irq_data {
42 irq_handler_t handler;
46 static struct wm831x_irq_data wm831x_irqs[] = {
47 [WM831X_IRQ_TEMP_THW] = {
48 .primary = WM831X_TEMP_INT,
50 .mask = WM831X_TEMP_THW_EINT,
52 [WM831X_IRQ_GPIO_1] = {
53 .primary = WM831X_GP_INT,
55 .mask = WM831X_GP1_EINT,
57 [WM831X_IRQ_GPIO_2] = {
58 .primary = WM831X_GP_INT,
60 .mask = WM831X_GP2_EINT,
62 [WM831X_IRQ_GPIO_3] = {
63 .primary = WM831X_GP_INT,
65 .mask = WM831X_GP3_EINT,
67 [WM831X_IRQ_GPIO_4] = {
68 .primary = WM831X_GP_INT,
70 .mask = WM831X_GP4_EINT,
72 [WM831X_IRQ_GPIO_5] = {
73 .primary = WM831X_GP_INT,
75 .mask = WM831X_GP5_EINT,
77 [WM831X_IRQ_GPIO_6] = {
78 .primary = WM831X_GP_INT,
80 .mask = WM831X_GP6_EINT,
82 [WM831X_IRQ_GPIO_7] = {
83 .primary = WM831X_GP_INT,
85 .mask = WM831X_GP7_EINT,
87 [WM831X_IRQ_GPIO_8] = {
88 .primary = WM831X_GP_INT,
90 .mask = WM831X_GP8_EINT,
92 [WM831X_IRQ_GPIO_9] = {
93 .primary = WM831X_GP_INT,
95 .mask = WM831X_GP9_EINT,
97 [WM831X_IRQ_GPIO_10] = {
98 .primary = WM831X_GP_INT,
100 .mask = WM831X_GP10_EINT,
102 [WM831X_IRQ_GPIO_11] = {
103 .primary = WM831X_GP_INT,
105 .mask = WM831X_GP11_EINT,
107 [WM831X_IRQ_GPIO_12] = {
108 .primary = WM831X_GP_INT,
110 .mask = WM831X_GP12_EINT,
112 [WM831X_IRQ_GPIO_13] = {
113 .primary = WM831X_GP_INT,
115 .mask = WM831X_GP13_EINT,
117 [WM831X_IRQ_GPIO_14] = {
118 .primary = WM831X_GP_INT,
120 .mask = WM831X_GP14_EINT,
122 [WM831X_IRQ_GPIO_15] = {
123 .primary = WM831X_GP_INT,
125 .mask = WM831X_GP15_EINT,
127 [WM831X_IRQ_GPIO_16] = {
128 .primary = WM831X_GP_INT,
130 .mask = WM831X_GP16_EINT,
133 .primary = WM831X_ON_PIN_INT,
135 .mask = WM831X_ON_PIN_EINT,
137 [WM831X_IRQ_PPM_SYSLO] = {
138 .primary = WM831X_PPM_INT,
140 .mask = WM831X_PPM_SYSLO_EINT,
142 [WM831X_IRQ_PPM_PWR_SRC] = {
143 .primary = WM831X_PPM_INT,
145 .mask = WM831X_PPM_PWR_SRC_EINT,
147 [WM831X_IRQ_PPM_USB_CURR] = {
148 .primary = WM831X_PPM_INT,
150 .mask = WM831X_PPM_USB_CURR_EINT,
152 [WM831X_IRQ_WDOG_TO] = {
153 .primary = WM831X_WDOG_INT,
155 .mask = WM831X_WDOG_TO_EINT,
157 [WM831X_IRQ_RTC_PER] = {
158 .primary = WM831X_RTC_INT,
160 .mask = WM831X_RTC_PER_EINT,
162 [WM831X_IRQ_RTC_ALM] = {
163 .primary = WM831X_RTC_INT,
165 .mask = WM831X_RTC_ALM_EINT,
167 [WM831X_IRQ_CHG_BATT_HOT] = {
168 .primary = WM831X_CHG_INT,
170 .mask = WM831X_CHG_BATT_HOT_EINT,
172 [WM831X_IRQ_CHG_BATT_COLD] = {
173 .primary = WM831X_CHG_INT,
175 .mask = WM831X_CHG_BATT_COLD_EINT,
177 [WM831X_IRQ_CHG_BATT_FAIL] = {
178 .primary = WM831X_CHG_INT,
180 .mask = WM831X_CHG_BATT_FAIL_EINT,
182 [WM831X_IRQ_CHG_OV] = {
183 .primary = WM831X_CHG_INT,
185 .mask = WM831X_CHG_OV_EINT,
187 [WM831X_IRQ_CHG_END] = {
188 .primary = WM831X_CHG_INT,
190 .mask = WM831X_CHG_END_EINT,
192 [WM831X_IRQ_CHG_TO] = {
193 .primary = WM831X_CHG_INT,
195 .mask = WM831X_CHG_TO_EINT,
197 [WM831X_IRQ_CHG_MODE] = {
198 .primary = WM831X_CHG_INT,
200 .mask = WM831X_CHG_MODE_EINT,
202 [WM831X_IRQ_CHG_START] = {
203 .primary = WM831X_CHG_INT,
205 .mask = WM831X_CHG_START_EINT,
207 [WM831X_IRQ_TCHDATA] = {
208 .primary = WM831X_TCHDATA_INT,
210 .mask = WM831X_TCHDATA_EINT,
212 [WM831X_IRQ_TCHPD] = {
213 .primary = WM831X_TCHPD_INT,
215 .mask = WM831X_TCHPD_EINT,
217 [WM831X_IRQ_AUXADC_DATA] = {
218 .primary = WM831X_AUXADC_INT,
220 .mask = WM831X_AUXADC_DATA_EINT,
222 [WM831X_IRQ_AUXADC_DCOMP1] = {
223 .primary = WM831X_AUXADC_INT,
225 .mask = WM831X_AUXADC_DCOMP1_EINT,
227 [WM831X_IRQ_AUXADC_DCOMP2] = {
228 .primary = WM831X_AUXADC_INT,
230 .mask = WM831X_AUXADC_DCOMP2_EINT,
232 [WM831X_IRQ_AUXADC_DCOMP3] = {
233 .primary = WM831X_AUXADC_INT,
235 .mask = WM831X_AUXADC_DCOMP3_EINT,
237 [WM831X_IRQ_AUXADC_DCOMP4] = {
238 .primary = WM831X_AUXADC_INT,
240 .mask = WM831X_AUXADC_DCOMP4_EINT,
243 .primary = WM831X_CS_INT,
245 .mask = WM831X_CS1_EINT,
248 .primary = WM831X_CS_INT,
250 .mask = WM831X_CS2_EINT,
252 [WM831X_IRQ_HC_DC1] = {
253 .primary = WM831X_HC_INT,
255 .mask = WM831X_HC_DC1_EINT,
257 [WM831X_IRQ_HC_DC2] = {
258 .primary = WM831X_HC_INT,
260 .mask = WM831X_HC_DC2_EINT,
262 [WM831X_IRQ_UV_LDO1] = {
263 .primary = WM831X_UV_INT,
265 .mask = WM831X_UV_LDO1_EINT,
267 [WM831X_IRQ_UV_LDO2] = {
268 .primary = WM831X_UV_INT,
270 .mask = WM831X_UV_LDO2_EINT,
272 [WM831X_IRQ_UV_LDO3] = {
273 .primary = WM831X_UV_INT,
275 .mask = WM831X_UV_LDO3_EINT,
277 [WM831X_IRQ_UV_LDO4] = {
278 .primary = WM831X_UV_INT,
280 .mask = WM831X_UV_LDO4_EINT,
282 [WM831X_IRQ_UV_LDO5] = {
283 .primary = WM831X_UV_INT,
285 .mask = WM831X_UV_LDO5_EINT,
287 [WM831X_IRQ_UV_LDO6] = {
288 .primary = WM831X_UV_INT,
290 .mask = WM831X_UV_LDO6_EINT,
292 [WM831X_IRQ_UV_LDO7] = {
293 .primary = WM831X_UV_INT,
295 .mask = WM831X_UV_LDO7_EINT,
297 [WM831X_IRQ_UV_LDO8] = {
298 .primary = WM831X_UV_INT,
300 .mask = WM831X_UV_LDO8_EINT,
302 [WM831X_IRQ_UV_LDO9] = {
303 .primary = WM831X_UV_INT,
305 .mask = WM831X_UV_LDO9_EINT,
307 [WM831X_IRQ_UV_LDO10] = {
308 .primary = WM831X_UV_INT,
310 .mask = WM831X_UV_LDO10_EINT,
312 [WM831X_IRQ_UV_DC1] = {
313 .primary = WM831X_UV_INT,
315 .mask = WM831X_UV_DC1_EINT,
317 [WM831X_IRQ_UV_DC2] = {
318 .primary = WM831X_UV_INT,
320 .mask = WM831X_UV_DC2_EINT,
322 [WM831X_IRQ_UV_DC3] = {
323 .primary = WM831X_UV_INT,
325 .mask = WM831X_UV_DC3_EINT,
327 [WM831X_IRQ_UV_DC4] = {
328 .primary = WM831X_UV_INT,
330 .mask = WM831X_UV_DC4_EINT,
334 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
336 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
339 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
341 return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
344 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
347 return &wm831x_irqs[irq - wm831x->irq_base];
350 static void wm831x_irq_lock(unsigned int irq)
352 struct wm831x *wm831x = get_irq_chip_data(irq);
354 mutex_lock(&wm831x->irq_lock);
357 static void wm831x_irq_sync_unlock(unsigned int irq)
359 struct wm831x *wm831x = get_irq_chip_data(irq);
362 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
363 /* If there's been a change in the mask write it back
364 * to the hardware. */
365 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
366 wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
367 wm831x_reg_write(wm831x,
368 WM831X_INTERRUPT_STATUS_1_MASK + i,
369 wm831x->irq_masks_cur[i]);
373 mutex_unlock(&wm831x->irq_lock);
376 static void wm831x_irq_unmask(unsigned int irq)
378 struct wm831x *wm831x = get_irq_chip_data(irq);
379 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
381 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
384 static void wm831x_irq_mask(unsigned int irq)
386 struct wm831x *wm831x = get_irq_chip_data(irq);
387 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
389 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
392 static int wm831x_irq_set_type(unsigned int irq, unsigned int type)
394 struct wm831x *wm831x = get_irq_chip_data(irq);
397 irq = irq - wm831x->irq_base;
399 if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11)
403 case IRQ_TYPE_EDGE_BOTH:
404 val = WM831X_GPN_INT_MODE;
406 case IRQ_TYPE_EDGE_RISING:
407 val = WM831X_GPN_POL;
409 case IRQ_TYPE_EDGE_FALLING:
416 return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + irq,
417 WM831X_GPN_INT_MODE | WM831X_GPN_POL, val);
420 static struct irq_chip wm831x_irq_chip = {
422 .bus_lock = wm831x_irq_lock,
423 .bus_sync_unlock = wm831x_irq_sync_unlock,
424 .mask = wm831x_irq_mask,
425 .unmask = wm831x_irq_unmask,
426 .set_type = wm831x_irq_set_type,
429 /* The processing of the primary interrupt occurs in a thread so that
430 * we can interact with the device over I2C or SPI. */
431 static irqreturn_t wm831x_irq_thread(int irq, void *data)
433 struct wm831x *wm831x = data;
436 int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
437 int read[WM831X_NUM_IRQ_REGS] = { 0 };
440 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
442 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
447 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
448 int offset = wm831x_irqs[i].reg - 1;
450 if (!(primary & wm831x_irqs[i].primary))
453 status = &status_regs[offset];
455 /* Hopefully there should only be one register to read
456 * each time otherwise we ought to do a block read. */
458 *status = wm831x_reg_read(wm831x,
459 irq_data_to_status_reg(&wm831x_irqs[i]));
462 "Failed to read IRQ status: %d\n",
470 /* Report it if it isn't masked, or forget the status. */
471 if ((*status & ~wm831x->irq_masks_cur[offset])
472 & wm831x_irqs[i].mask)
473 handle_nested_irq(wm831x->irq_base + i);
475 *status &= ~wm831x_irqs[i].mask;
479 for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
481 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
488 int wm831x_irq_init(struct wm831x *wm831x, int irq)
490 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
493 mutex_init(&wm831x->irq_lock);
496 dev_warn(wm831x->dev,
497 "No interrupt specified - functionality limited\n");
501 if (!pdata || !pdata->irq_base) {
503 "No interrupt base specified, no interrupts\n");
508 wm831x->irq_base = pdata->irq_base;
510 /* Mask the individual interrupt sources */
511 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
512 wm831x->irq_masks_cur[i] = 0xffff;
513 wm831x->irq_masks_cache[i] = 0xffff;
514 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
518 /* Register them with genirq */
519 for (cur_irq = wm831x->irq_base;
520 cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
522 set_irq_chip_data(cur_irq, wm831x);
523 set_irq_chip_and_handler(cur_irq, &wm831x_irq_chip,
525 set_irq_nested_thread(cur_irq, 1);
527 /* ARM needs us to explicitly flag the IRQ as valid
528 * and will set them noprobe when we do so. */
530 set_irq_flags(cur_irq, IRQF_VALID);
532 set_irq_noprobe(cur_irq);
536 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
537 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
540 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
545 /* Enable top level interrupts, we mask at secondary level */
546 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
551 void wm831x_irq_exit(struct wm831x *wm831x)
554 free_irq(wm831x->irq, wm831x);