2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
19 #include <linux/delay.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pci-bridge.h> /* for struct pci_controller */
23 #include <asm/pnv-pci.h>
28 #define CXL_PCI_VSEC_ID 0x1280
29 #define CXL_VSEC_MIN_SIZE 0x80
31 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
33 pci_read_config_word(dev, vsec + 0x6, dest); \
36 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
37 pci_read_config_byte(dev, vsec + 0x8, dest)
39 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
40 pci_read_config_byte(dev, vsec + 0x9, dest)
41 #define CXL_STATUS_SECOND_PORT 0x80
42 #define CXL_STATUS_MSI_X_FULL 0x40
43 #define CXL_STATUS_MSI_X_SINGLE 0x20
44 #define CXL_STATUS_FLASH_RW 0x08
45 #define CXL_STATUS_FLASH_RO 0x04
46 #define CXL_STATUS_LOADABLE_AFU 0x02
47 #define CXL_STATUS_LOADABLE_PSL 0x01
48 /* If we see these features we won't try to use the card */
49 #define CXL_UNSUPPORTED_FEATURES \
50 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
52 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
53 pci_read_config_byte(dev, vsec + 0xa, dest)
54 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
55 pci_write_config_byte(dev, vsec + 0xa, val)
56 #define CXL_VSEC_PROTOCOL_MASK 0xe0
57 #define CXL_VSEC_PROTOCOL_1024TB 0x80
58 #define CXL_VSEC_PROTOCOL_512TB 0x40
59 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */
60 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
62 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
63 pci_read_config_word(dev, vsec + 0xc, dest)
64 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
65 pci_read_config_byte(dev, vsec + 0xe, dest)
66 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
67 pci_read_config_byte(dev, vsec + 0xf, dest)
68 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
69 pci_read_config_word(dev, vsec + 0x10, dest)
71 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
72 pci_read_config_byte(dev, vsec + 0x13, dest)
73 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
74 pci_write_config_byte(dev, vsec + 0x13, val)
75 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
76 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
77 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
79 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
80 pci_read_config_dword(dev, vsec + 0x20, dest)
81 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x24, dest)
83 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x28, dest)
85 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x2c, dest)
89 /* This works a little different than the p1/p2 register accesses to make it
90 * easier to pull out individual fields */
91 #define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off)
92 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
93 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
95 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
96 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
97 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
98 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
99 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
100 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
101 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
102 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
103 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
104 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
105 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
106 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
107 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
108 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
109 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
110 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
112 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
113 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
114 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
116 static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = {
117 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
118 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
119 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
120 { PCI_DEVICE_CLASS(0x120000, ~0), },
124 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
128 * Mostly using these wrappers to avoid confusion:
129 * priv 1 is BAR2, while priv 2 is BAR0
131 static inline resource_size_t p1_base(struct pci_dev *dev)
133 return pci_resource_start(dev, 2);
136 static inline resource_size_t p1_size(struct pci_dev *dev)
138 return pci_resource_len(dev, 2);
141 static inline resource_size_t p2_base(struct pci_dev *dev)
143 return pci_resource_start(dev, 0);
146 static inline resource_size_t p2_size(struct pci_dev *dev)
148 return pci_resource_len(dev, 0);
151 static int find_cxl_vsec(struct pci_dev *dev)
156 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
157 pci_read_config_word(dev, vsec + 0x4, &val);
158 if (val == CXL_PCI_VSEC_ID)
165 static void dump_cxl_config_space(struct pci_dev *dev)
170 dev_info(&dev->dev, "dump_cxl_config_space\n");
172 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
173 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
174 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
175 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
177 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
179 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
181 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
183 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
185 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
186 p1_base(dev), p1_size(dev));
187 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
188 p1_base(dev), p2_size(dev));
189 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
190 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
192 if (!(vsec = find_cxl_vsec(dev)))
195 #define show_reg(name, what) \
196 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
198 pci_read_config_dword(dev, vsec + 0x0, &val);
199 show_reg("Cap ID", (val >> 0) & 0xffff);
200 show_reg("Cap Ver", (val >> 16) & 0xf);
201 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
202 pci_read_config_dword(dev, vsec + 0x4, &val);
203 show_reg("VSEC ID", (val >> 0) & 0xffff);
204 show_reg("VSEC Rev", (val >> 16) & 0xf);
205 show_reg("VSEC Length", (val >> 20) & 0xfff);
206 pci_read_config_dword(dev, vsec + 0x8, &val);
207 show_reg("Num AFUs", (val >> 0) & 0xff);
208 show_reg("Status", (val >> 8) & 0xff);
209 show_reg("Mode Control", (val >> 16) & 0xff);
210 show_reg("Reserved", (val >> 24) & 0xff);
211 pci_read_config_dword(dev, vsec + 0xc, &val);
212 show_reg("PSL Rev", (val >> 0) & 0xffff);
213 show_reg("CAIA Ver", (val >> 16) & 0xffff);
214 pci_read_config_dword(dev, vsec + 0x10, &val);
215 show_reg("Base Image Rev", (val >> 0) & 0xffff);
216 show_reg("Reserved", (val >> 16) & 0x0fff);
217 show_reg("Image Control", (val >> 28) & 0x3);
218 show_reg("Reserved", (val >> 30) & 0x1);
219 show_reg("Image Loaded", (val >> 31) & 0x1);
221 pci_read_config_dword(dev, vsec + 0x14, &val);
222 show_reg("Reserved", val);
223 pci_read_config_dword(dev, vsec + 0x18, &val);
224 show_reg("Reserved", val);
225 pci_read_config_dword(dev, vsec + 0x1c, &val);
226 show_reg("Reserved", val);
228 pci_read_config_dword(dev, vsec + 0x20, &val);
229 show_reg("AFU Descriptor Offset", val);
230 pci_read_config_dword(dev, vsec + 0x24, &val);
231 show_reg("AFU Descriptor Size", val);
232 pci_read_config_dword(dev, vsec + 0x28, &val);
233 show_reg("Problem State Offset", val);
234 pci_read_config_dword(dev, vsec + 0x2c, &val);
235 show_reg("Problem State Size", val);
237 pci_read_config_dword(dev, vsec + 0x30, &val);
238 show_reg("Reserved", val);
239 pci_read_config_dword(dev, vsec + 0x34, &val);
240 show_reg("Reserved", val);
241 pci_read_config_dword(dev, vsec + 0x38, &val);
242 show_reg("Reserved", val);
243 pci_read_config_dword(dev, vsec + 0x3c, &val);
244 show_reg("Reserved", val);
246 pci_read_config_dword(dev, vsec + 0x40, &val);
247 show_reg("PSL Programming Port", val);
248 pci_read_config_dword(dev, vsec + 0x44, &val);
249 show_reg("PSL Programming Control", val);
251 pci_read_config_dword(dev, vsec + 0x48, &val);
252 show_reg("Reserved", val);
253 pci_read_config_dword(dev, vsec + 0x4c, &val);
254 show_reg("Reserved", val);
256 pci_read_config_dword(dev, vsec + 0x50, &val);
257 show_reg("Flash Address Register", val);
258 pci_read_config_dword(dev, vsec + 0x54, &val);
259 show_reg("Flash Size Register", val);
260 pci_read_config_dword(dev, vsec + 0x58, &val);
261 show_reg("Flash Status/Control Register", val);
262 pci_read_config_dword(dev, vsec + 0x58, &val);
263 show_reg("Flash Data Port", val);
268 static void dump_afu_descriptor(struct cxl_afu *afu)
272 #define show_reg(name, what) \
273 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
275 val = AFUD_READ_INFO(afu);
276 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
277 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
278 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
279 show_reg("req_prog_mode", val & 0xffffULL);
281 val = AFUD_READ(afu, 0x8);
282 show_reg("Reserved", val);
283 val = AFUD_READ(afu, 0x10);
284 show_reg("Reserved", val);
285 val = AFUD_READ(afu, 0x18);
286 show_reg("Reserved", val);
288 val = AFUD_READ_CR(afu);
289 show_reg("Reserved", (val >> (63-7)) & 0xff);
290 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
292 val = AFUD_READ_CR_OFF(afu);
293 show_reg("AFU_CR_offset", val);
295 val = AFUD_READ_PPPSA(afu);
296 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
297 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
299 val = AFUD_READ_PPPSA_OFF(afu);
300 show_reg("PerProcessPSA_offset", val);
302 val = AFUD_READ_EB(afu);
303 show_reg("Reserved", (val >> (63-7)) & 0xff);
304 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
306 val = AFUD_READ_EB_OFF(afu);
307 show_reg("AFU_EB_offset", val);
312 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
314 struct device_node *np;
319 if (!(np = pnv_pci_to_phb_node(dev)))
322 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
323 np = of_get_next_parent(np);
326 chipid = be32_to_cpup(prop);
329 /* Tell PSL where to route data to */
330 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
331 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
332 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
333 /* snoop write mask */
334 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
336 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
337 /* for debugging with trace arrays */
338 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
343 static int init_implementation_afu_regs(struct cxl_afu *afu)
345 /* read/write masks for this slice */
346 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
347 /* APC read/write masks for this slice */
348 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
349 /* for debugging with trace arrays */
350 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
351 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, 0xF000000000000000ULL);
356 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
359 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
361 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
364 int cxl_alloc_one_irq(struct cxl *adapter)
366 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
368 return pnv_cxl_alloc_hwirqs(dev, 1);
371 void cxl_release_one_irq(struct cxl *adapter, int hwirq)
373 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
375 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
378 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num)
380 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
382 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
385 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter)
387 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
389 pnv_cxl_release_hwirq_ranges(irqs, dev);
392 static int setup_cxl_bars(struct pci_dev *dev)
394 /* Safety check in case we get backported to < 3.17 without M64 */
395 if ((p1_base(dev) < 0x100000000ULL) ||
396 (p2_base(dev) < 0x100000000ULL)) {
397 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
402 * BAR 4/5 has a special meaning for CXL and must be programmed with a
403 * special value corresponding to the CXL protocol address range.
404 * For POWER 8 that means bits 48:49 must be set to 10
406 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
407 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
412 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
413 static int switch_card_to_cxl(struct pci_dev *dev)
419 dev_info(&dev->dev, "switch card to CXL\n");
421 if (!(vsec = find_cxl_vsec(dev))) {
422 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
426 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
427 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
430 val &= ~CXL_VSEC_PROTOCOL_MASK;
431 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
432 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
433 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
437 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
438 * we must wait 100ms after this mode switch before touching
446 static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
448 u64 p1n_base, p2n_base, afu_desc;
449 const u64 p1n_size = 0x100;
450 const u64 p2n_size = 0x1000;
452 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
453 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
454 afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size));
455 afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size);
457 if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size)))
459 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
462 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size)))
468 iounmap(afu->p2n_mmio);
470 iounmap(afu->p1n_mmio);
472 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
476 static void cxl_unmap_slice_regs(struct cxl_afu *afu)
479 iounmap(afu->p2n_mmio);
481 iounmap(afu->p1n_mmio);
484 static void cxl_release_afu(struct device *dev)
486 struct cxl_afu *afu = to_cxl_afu(dev);
488 pr_devel("cxl_release_afu\n");
493 static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
497 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
500 afu->adapter = adapter;
501 afu->dev.parent = &adapter->dev;
502 afu->dev.release = cxl_release_afu;
504 idr_init(&afu->contexts_idr);
505 spin_lock_init(&afu->contexts_lock);
506 spin_lock_init(&afu->afu_cntl_lock);
507 mutex_init(&afu->spa_mutex);
509 afu->prefault_mode = CXL_PREFAULT_NONE;
510 afu->irqs_max = afu->adapter->user_irqs;
515 /* Expects AFU struct to have recently been zeroed out */
516 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
520 val = AFUD_READ_INFO(afu);
521 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
522 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
524 if (AFUD_AFU_DIRECTED(val))
525 afu->modes_supported |= CXL_MODE_DIRECTED;
526 if (AFUD_DEDICATED_PROCESS(val))
527 afu->modes_supported |= CXL_MODE_DEDICATED;
528 if (AFUD_TIME_SLICED(val))
529 afu->modes_supported |= CXL_MODE_TIME_SLICED;
531 val = AFUD_READ_PPPSA(afu);
532 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
533 afu->psa = AFUD_PPPSA_PSA(val);
534 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
535 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
540 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
542 if (afu->psa && afu->adapter->ps_size <
543 (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
544 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
548 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
549 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
554 static int sanitise_afu_regs(struct cxl_afu *afu)
559 * Clear out any regs that contain either an IVTE or address or may be
560 * waiting on an acknowledgement to try to be a bit safer as we bring
563 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
564 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
565 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg);
566 if (cxl_afu_reset(afu))
568 if (cxl_afu_disable(afu))
570 if (cxl_psl_purge(afu))
573 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
574 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
575 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
576 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
577 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
578 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
579 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
580 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
581 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
582 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
583 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
584 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
586 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg);
587 if (reg & CXL_PSL_DSISR_TRANS)
588 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
590 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
592 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
595 dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg);
596 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
598 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
600 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg);
601 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
607 static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
613 if (!(afu = cxl_alloc_afu(adapter, slice)))
616 if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice)))
619 if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
622 if ((rc = sanitise_afu_regs(afu)))
625 /* We need to reset the AFU before we can read the AFU descriptor */
626 if ((rc = cxl_afu_reset(afu)))
630 dump_afu_descriptor(afu);
632 if ((rc = cxl_read_afu_descriptor(afu)))
635 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
638 if ((rc = init_implementation_afu_regs(afu)))
641 if ((rc = cxl_register_serr_irq(afu)))
644 if ((rc = cxl_register_psl_irq(afu)))
647 /* Don't care if this fails */
648 cxl_debugfs_afu_add(afu);
651 * After we call this function we must not free the afu directly, even
652 * if it returns an error!
654 if ((rc = cxl_register_afu(afu)))
657 if ((rc = cxl_sysfs_afu_add(afu)))
661 if ((rc = cxl_afu_select_best_mode(afu)))
664 adapter->afu[afu->slice] = afu;
669 cxl_sysfs_afu_remove(afu);
671 device_unregister(&afu->dev);
673 cxl_debugfs_afu_remove(afu);
674 cxl_release_psl_irq(afu);
676 cxl_release_serr_irq(afu);
678 cxl_unmap_slice_regs(afu);
685 static void cxl_remove_afu(struct cxl_afu *afu)
687 pr_devel("cxl_remove_afu\n");
692 cxl_sysfs_afu_remove(afu);
693 cxl_debugfs_afu_remove(afu);
695 spin_lock(&afu->adapter->afu_list_lock);
696 afu->adapter->afu[afu->slice] = NULL;
697 spin_unlock(&afu->adapter->afu_list_lock);
699 cxl_context_detach_all(afu);
700 cxl_afu_deactivate_mode(afu);
702 cxl_release_psl_irq(afu);
703 cxl_release_serr_irq(afu);
704 cxl_unmap_slice_regs(afu);
706 device_unregister(&afu->dev);
710 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
712 if (pci_request_region(dev, 2, "priv 2 regs"))
714 if (pci_request_region(dev, 0, "priv 1 regs"))
717 pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",
718 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
720 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
723 if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
729 iounmap(adapter->p1_mmio);
730 adapter->p1_mmio = NULL;
732 pci_release_region(dev, 0);
734 pci_release_region(dev, 2);
739 static void cxl_unmap_adapter_regs(struct cxl *adapter)
741 if (adapter->p1_mmio)
742 iounmap(adapter->p1_mmio);
743 if (adapter->p2_mmio)
744 iounmap(adapter->p2_mmio);
747 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
750 u32 afu_desc_off, afu_desc_size;
755 if (!(vsec = find_cxl_vsec(dev))) {
756 dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n");
760 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
761 if (vseclen < CXL_VSEC_MIN_SIZE) {
762 pr_err("ABORTING: CXL VSEC too short\n");
766 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
767 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
768 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
769 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
770 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
771 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
772 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
773 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
774 adapter->perst_select_user = !!(image_state & CXL_VSEC_PERST_SELECT_USER);
776 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
777 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
778 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
779 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
780 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
782 /* Convert everything to bytes, because there is NO WAY I'd look at the
783 * code a month later and forget what units these are in ;-) */
784 adapter->ps_off = ps_off * 64 * 1024;
785 adapter->ps_size = ps_size * 64 * 1024;
786 adapter->afu_desc_off = afu_desc_off * 64 * 1024;
787 adapter->afu_desc_size = afu_desc_size *64 * 1024;
789 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
790 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
795 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
797 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
800 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
801 dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n");
805 if (!adapter->slices) {
806 /* Once we support dynamic reprogramming we can use the card if
807 * it supports loadable AFUs */
808 dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n");
812 if (!adapter->afu_desc_off || !adapter->afu_desc_size) {
813 dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n");
817 if (adapter->ps_size > p2_size(dev) - adapter->ps_off) {
818 dev_err(&adapter->dev, "ABORTING: Problem state size larger than "
819 "available in BAR2: 0x%llx > 0x%llx\n",
820 adapter->ps_size, p2_size(dev) - adapter->ps_off);
827 static void cxl_release_adapter(struct device *dev)
829 struct cxl *adapter = to_cxl_adapter(dev);
831 pr_devel("cxl_release_adapter\n");
836 static struct cxl *cxl_alloc_adapter(struct pci_dev *dev)
840 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
843 adapter->dev.parent = &dev->dev;
844 adapter->dev.release = cxl_release_adapter;
845 pci_set_drvdata(dev, adapter);
846 spin_lock_init(&adapter->afu_list_lock);
851 static int sanitise_adapter_regs(struct cxl *adapter)
853 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
854 return cxl_tlb_slb_invalidate(adapter);
857 static struct cxl *cxl_init_adapter(struct pci_dev *dev)
864 if (!(adapter = cxl_alloc_adapter(dev)))
865 return ERR_PTR(-ENOMEM);
867 if ((rc = switch_card_to_cxl(dev)))
870 if ((rc = cxl_alloc_adapter_nr(adapter)))
873 if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)))
876 if ((rc = cxl_read_vsec(adapter, dev)))
879 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
882 if ((rc = cxl_map_adapter_regs(adapter, dev)))
885 if ((rc = sanitise_adapter_regs(adapter)))
888 if ((rc = init_implementation_adapter_regs(adapter, dev)))
891 if ((rc = pnv_phb_to_cxl(dev)))
894 if ((rc = cxl_register_psl_err_irq(adapter)))
897 /* Don't care if this one fails: */
898 cxl_debugfs_adapter_add(adapter);
901 * After we call this function we must not free the adapter directly,
902 * even if it returns an error!
904 if ((rc = cxl_register_adapter(adapter)))
907 if ((rc = cxl_sysfs_adapter_add(adapter)))
913 device_unregister(&adapter->dev);
915 cxl_debugfs_adapter_remove(adapter);
916 cxl_release_psl_err_irq(adapter);
918 cxl_unmap_adapter_regs(adapter);
920 cxl_remove_adapter_nr(adapter);
927 static void cxl_remove_adapter(struct cxl *adapter)
929 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
931 pr_devel("cxl_release_adapter\n");
933 cxl_sysfs_adapter_remove(adapter);
934 cxl_debugfs_adapter_remove(adapter);
935 cxl_release_psl_err_irq(adapter);
936 cxl_unmap_adapter_regs(adapter);
937 cxl_remove_adapter_nr(adapter);
939 device_unregister(&adapter->dev);
941 pci_release_region(pdev, 0);
942 pci_release_region(pdev, 2);
943 pci_disable_device(pdev);
946 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
955 dump_cxl_config_space(dev);
957 if ((rc = setup_cxl_bars(dev)))
960 if ((rc = pci_enable_device(dev))) {
961 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
965 adapter = cxl_init_adapter(dev);
966 if (IS_ERR(adapter)) {
967 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
968 return PTR_ERR(adapter);
971 for (slice = 0; slice < adapter->slices; slice++) {
972 if ((rc = cxl_init_afu(adapter, slice, dev)))
973 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
979 static void cxl_remove(struct pci_dev *dev)
981 struct cxl *adapter = pci_get_drvdata(dev);
984 dev_warn(&dev->dev, "pci remove\n");
987 * Lock to prevent someone grabbing a ref through the adapter list as
990 for (afu = 0; afu < adapter->slices; afu++)
991 cxl_remove_afu(adapter->afu[afu]);
992 cxl_remove_adapter(adapter);
995 struct pci_driver cxl_pci_driver = {
997 .id_table = cxl_pci_tbl,
999 .remove = cxl_remove,