drivers/misc/cxl/pci.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/pci_regs.h>
  11 #include <linux/pci_ids.h>
  12 #include <linux/device.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/sort.h>
  17 #include <linux/pci.h>
  18 #include <linux/of.h>
  19 #include <linux/delay.h>
  20 #include <asm/opal.h>
  21 #include <asm/msi_bitmap.h>
  22 #include <asm/pci-bridge.h> /* for struct pci_controller */
  23 #include <asm/pnv-pci.h>
  24 #include <asm/io.h>
  25
  26 #include "cxl.h"
  27
  28
  29 #define CXL_PCI_VSEC_ID 0x1280
  30 #define CXL_VSEC_MIN_SIZE 0x80
  31
  32 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
  33         {                                                       \
  34                 pci_read_config_word(dev, vsec + 0x6, dest);    \
  35                 *dest >>= 4;                                    \
  36         }
  37 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
  38         pci_read_config_byte(dev, vsec + 0x8, dest)
  39
  40 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
  41         pci_read_config_byte(dev, vsec + 0x9, dest)
  42 #define CXL_STATUS_SECOND_PORT  0x80
  43 #define CXL_STATUS_MSI_X_FULL   0x40
  44 #define CXL_STATUS_MSI_X_SINGLE 0x20
  45 #define CXL_STATUS_FLASH_RW     0x08
  46 #define CXL_STATUS_FLASH_RO     0x04
  47 #define CXL_STATUS_LOADABLE_AFU 0x02
  48 #define CXL_STATUS_LOADABLE_PSL 0x01
  49 /* If we see these features we won't try to use the card */
  50 #define CXL_UNSUPPORTED_FEATURES \
  51         (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
  52
  53 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
  54         pci_read_config_byte(dev, vsec + 0xa, dest)
  55 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
  56         pci_write_config_byte(dev, vsec + 0xa, val)
  57 #define CXL_VSEC_PROTOCOL_MASK   0xe0
  58 #define CXL_VSEC_PROTOCOL_1024TB 0x80
  59 #define CXL_VSEC_PROTOCOL_512TB  0x40
  60 #define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8 uses this */
  61 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
  62
  63 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
  64         pci_read_config_word(dev, vsec + 0xc, dest)
  65 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
  66         pci_read_config_byte(dev, vsec + 0xe, dest)
  67 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
  68         pci_read_config_byte(dev, vsec + 0xf, dest)
  69 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
  70         pci_read_config_word(dev, vsec + 0x10, dest)
  71
  72 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
  73         pci_read_config_byte(dev, vsec + 0x13, dest)
  74 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
  75         pci_write_config_byte(dev, vsec + 0x13, val)
  76 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
  77 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
  78 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
  79
  80 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
  81         pci_read_config_dword(dev, vsec + 0x20, dest)
  82 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
  83         pci_read_config_dword(dev, vsec + 0x24, dest)
  84 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
  85         pci_read_config_dword(dev, vsec + 0x28, dest)
  86 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
  87         pci_read_config_dword(dev, vsec + 0x2c, dest)
  88
  89
  90 /* This works a little different than the p1/p2 register accesses to make it
  91  * easier to pull out individual fields */
  92 #define AFUD_READ(afu, off)             in_be64(afu->afu_desc_mmio + off)
  93 #define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
  94 #define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
  95
  96 #define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
  97 #define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
  98 #define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
  99 #define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
 100 #define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
 101 #define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
 102 #define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
 103 #define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
 104 #define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
 105 #define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
 106 #define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 107 #define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
 108 #define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
 109 #define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
 110 #define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
 111 #define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
 112 #define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
 113 #define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
 114 #define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 115 #define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
 116
 117 static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = {
 118         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
 119         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
 120         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
 121         { PCI_DEVICE_CLASS(0x120000, ~0), },
 122
 123         { }
 124 };
 125 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
 126
 127
 128 /*
 129  * Mostly using these wrappers to avoid confusion:
 130  * priv 1 is BAR2, while priv 2 is BAR0
 131  */
 132 static inline resource_size_t p1_base(struct pci_dev *dev)
 133 {
 134         return pci_resource_start(dev, 2);
 135 }
 136
 137 static inline resource_size_t p1_size(struct pci_dev *dev)
 138 {
 139         return pci_resource_len(dev, 2);
 140 }
 141
 142 static inline resource_size_t p2_base(struct pci_dev *dev)
 143 {
 144         return pci_resource_start(dev, 0);
 145 }
 146
 147 static inline resource_size_t p2_size(struct pci_dev *dev)
 148 {
 149         return pci_resource_len(dev, 0);
 150 }
 151
 152 static int find_cxl_vsec(struct pci_dev *dev)
 153 {
 154         int vsec = 0;
 155         u16 val;
 156
 157         while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
 158                 pci_read_config_word(dev, vsec + 0x4, &val);
 159                 if (val == CXL_PCI_VSEC_ID)
 160                         return vsec;
 161         }
 162         return 0;
 163
 164 }
 165
 166 static void dump_cxl_config_space(struct pci_dev *dev)
 167 {
 168         int vsec;
 169         u32 val;
 170
 171         dev_info(&dev->dev, "dump_cxl_config_space\n");
 172
 173         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
 174         dev_info(&dev->dev, "BAR0: %#.8x\n", val);
 175         pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
 176         dev_info(&dev->dev, "BAR1: %#.8x\n", val);
 177         pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
 178         dev_info(&dev->dev, "BAR2: %#.8x\n", val);
 179         pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
 180         dev_info(&dev->dev, "BAR3: %#.8x\n", val);
 181         pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
 182         dev_info(&dev->dev, "BAR4: %#.8x\n", val);
 183         pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
 184         dev_info(&dev->dev, "BAR5: %#.8x\n", val);
 185
 186         dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
 187                 p1_base(dev), p1_size(dev));
 188         dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
 189                 p1_base(dev), p2_size(dev));
 190         dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
 191                 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
 192
 193         if (!(vsec = find_cxl_vsec(dev)))
 194                 return;
 195
 196 #define show_reg(name, what) \
 197         dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
 198
 199         pci_read_config_dword(dev, vsec + 0x0, &val);
 200         show_reg("Cap ID", (val >> 0) & 0xffff);
 201         show_reg("Cap Ver", (val >> 16) & 0xf);
 202         show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
 203         pci_read_config_dword(dev, vsec + 0x4, &val);
 204         show_reg("VSEC ID", (val >> 0) & 0xffff);
 205         show_reg("VSEC Rev", (val >> 16) & 0xf);
 206         show_reg("VSEC Length", (val >> 20) & 0xfff);
 207         pci_read_config_dword(dev, vsec + 0x8, &val);
 208         show_reg("Num AFUs", (val >> 0) & 0xff);
 209         show_reg("Status", (val >> 8) & 0xff);
 210         show_reg("Mode Control", (val >> 16) & 0xff);
 211         show_reg("Reserved", (val >> 24) & 0xff);
 212         pci_read_config_dword(dev, vsec + 0xc, &val);
 213         show_reg("PSL Rev", (val >> 0) & 0xffff);
 214         show_reg("CAIA Ver", (val >> 16) & 0xffff);
 215         pci_read_config_dword(dev, vsec + 0x10, &val);
 216         show_reg("Base Image Rev", (val >> 0) & 0xffff);
 217         show_reg("Reserved", (val >> 16) & 0x0fff);
 218         show_reg("Image Control", (val >> 28) & 0x3);
 219         show_reg("Reserved", (val >> 30) & 0x1);
 220         show_reg("Image Loaded", (val >> 31) & 0x1);
 221
 222         pci_read_config_dword(dev, vsec + 0x14, &val);
 223         show_reg("Reserved", val);
 224         pci_read_config_dword(dev, vsec + 0x18, &val);
 225         show_reg("Reserved", val);
 226         pci_read_config_dword(dev, vsec + 0x1c, &val);
 227         show_reg("Reserved", val);
 228
 229         pci_read_config_dword(dev, vsec + 0x20, &val);
 230         show_reg("AFU Descriptor Offset", val);
 231         pci_read_config_dword(dev, vsec + 0x24, &val);
 232         show_reg("AFU Descriptor Size", val);
 233         pci_read_config_dword(dev, vsec + 0x28, &val);
 234         show_reg("Problem State Offset", val);
 235         pci_read_config_dword(dev, vsec + 0x2c, &val);
 236         show_reg("Problem State Size", val);
 237
 238         pci_read_config_dword(dev, vsec + 0x30, &val);
 239         show_reg("Reserved", val);
 240         pci_read_config_dword(dev, vsec + 0x34, &val);
 241         show_reg("Reserved", val);
 242         pci_read_config_dword(dev, vsec + 0x38, &val);
 243         show_reg("Reserved", val);
 244         pci_read_config_dword(dev, vsec + 0x3c, &val);
 245         show_reg("Reserved", val);
 246
 247         pci_read_config_dword(dev, vsec + 0x40, &val);
 248         show_reg("PSL Programming Port", val);
 249         pci_read_config_dword(dev, vsec + 0x44, &val);
 250         show_reg("PSL Programming Control", val);
 251
 252         pci_read_config_dword(dev, vsec + 0x48, &val);
 253         show_reg("Reserved", val);
 254         pci_read_config_dword(dev, vsec + 0x4c, &val);
 255         show_reg("Reserved", val);
 256
 257         pci_read_config_dword(dev, vsec + 0x50, &val);
 258         show_reg("Flash Address Register", val);
 259         pci_read_config_dword(dev, vsec + 0x54, &val);
 260         show_reg("Flash Size Register", val);
 261         pci_read_config_dword(dev, vsec + 0x58, &val);
 262         show_reg("Flash Status/Control Register", val);
 263         pci_read_config_dword(dev, vsec + 0x58, &val);
 264         show_reg("Flash Data Port", val);
 265
 266 #undef show_reg
 267 }
 268
 269 static void dump_afu_descriptor(struct cxl_afu *afu)
 270 {
 271         u64 val;
 272
 273 #define show_reg(name, what) \
 274         dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
 275
 276         val = AFUD_READ_INFO(afu);
 277         show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
 278         show_reg("num_of_processes", AFUD_NUM_PROCS(val));
 279         show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
 280         show_reg("req_prog_mode", val & 0xffffULL);
 281
 282         val = AFUD_READ(afu, 0x8);
 283         show_reg("Reserved", val);
 284         val = AFUD_READ(afu, 0x10);
 285         show_reg("Reserved", val);
 286         val = AFUD_READ(afu, 0x18);
 287         show_reg("Reserved", val);
 288
 289         val = AFUD_READ_CR(afu);
 290         show_reg("Reserved", (val >> (63-7)) & 0xff);
 291         show_reg("AFU_CR_len", AFUD_CR_LEN(val));
 292
 293         val = AFUD_READ_CR_OFF(afu);
 294         show_reg("AFU_CR_offset", val);
 295
 296         val = AFUD_READ_PPPSA(afu);
 297         show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
 298         show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
 299
 300         val = AFUD_READ_PPPSA_OFF(afu);
 301         show_reg("PerProcessPSA_offset", val);
 302
 303         val = AFUD_READ_EB(afu);
 304         show_reg("Reserved", (val >> (63-7)) & 0xff);
 305         show_reg("AFU_EB_len", AFUD_EB_LEN(val));
 306
 307         val = AFUD_READ_EB_OFF(afu);
 308         show_reg("AFU_EB_offset", val);
 309
 310 #undef show_reg
 311 }
 312
 313 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
 314 {
 315         struct device_node *np;
 316         const __be32 *prop;
 317         u64 psl_dsnctl;
 318         u64 chipid;
 319
 320         if (!(np = pnv_pci_get_phb_node(dev)))
 321                 return -ENODEV;
 322
 323         while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
 324                 np = of_get_next_parent(np);
 325         if (!np)
 326                 return -ENODEV;
 327         chipid = be32_to_cpup(prop);
 328         of_node_put(np);
 329
 330         /* Tell PSL where to route data to */
 331         psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
 332         cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
 333         cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
 334         /* snoop write mask */
 335         cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
 336         /* set fir_accum */
 337         cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
 338         /* for debugging with trace arrays */
 339         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
 340
 341         return 0;
 342 }
 343
 344 static int init_implementation_afu_regs(struct cxl_afu *afu)
 345 {
 346         /* read/write masks for this slice */
 347         cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
 348         /* APC read/write masks for this slice */
 349         cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
 350         /* for debugging with trace arrays */
 351         cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
 352         cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
 353
 354         return 0;
 355 }
 356
 357 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
 358                          unsigned int virq)
 359 {
 360         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 361
 362         return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
 363 }
 364
 365 int cxl_update_image_control(struct cxl *adapter)
 366 {
 367         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 368         int rc;
 369         int vsec;
 370         u8 image_state;
 371
 372         if (!(vsec = find_cxl_vsec(dev))) {
 373                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 374                 return -ENODEV;
 375         }
 376
 377         if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
 378                 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
 379                 return rc;
 380         }
 381
 382         if (adapter->perst_loads_image)
 383                 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
 384         else
 385                 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
 386
 387         if (adapter->perst_select_user)
 388                 image_state |= CXL_VSEC_PERST_SELECT_USER;
 389         else
 390                 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
 391
 392         if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
 393                 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
 394                 return rc;
 395         }
 396
 397         return 0;
 398 }
 399
 400 int cxl_alloc_one_irq(struct cxl *adapter)
 401 {
 402         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 403
 404         return pnv_cxl_alloc_hwirqs(dev, 1);
 405 }
 406
 407 void cxl_release_one_irq(struct cxl *adapter, int hwirq)
 408 {
 409         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 410
 411         return pnv_cxl_release_hwirqs(dev, hwirq, 1);
 412 }
 413
 414 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num)
 415 {
 416         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 417
 418         return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
 419 }
 420
 421 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter)
 422 {
 423         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 424
 425         pnv_cxl_release_hwirq_ranges(irqs, dev);
 426 }
 427
 428 static int setup_cxl_bars(struct pci_dev *dev)
 429 {
 430         /* Safety check in case we get backported to < 3.17 without M64 */
 431         if ((p1_base(dev) < 0x100000000ULL) ||
 432             (p2_base(dev) < 0x100000000ULL)) {
 433                 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
 434                 return -ENODEV;
 435         }
 436
 437         /*
 438          * BAR 4/5 has a special meaning for CXL and must be programmed with a
 439          * special value corresponding to the CXL protocol address range.
 440          * For POWER 8 that means bits 48:49 must be set to 10
 441          */
 442         pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
 443         pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
 444
 445         return 0;
 446 }
 447
 448 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
 449 static int switch_card_to_cxl(struct pci_dev *dev)
 450 {
 451         int vsec;
 452         u8 val;
 453         int rc;
 454
 455         dev_info(&dev->dev, "switch card to CXL\n");
 456
 457         if (!(vsec = find_cxl_vsec(dev))) {
 458                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 459                 return -ENODEV;
 460         }
 461
 462         if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
 463                 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
 464                 return rc;
 465         }
 466         val &= ~CXL_VSEC_PROTOCOL_MASK;
 467         val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
 468         if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
 469                 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
 470                 return rc;
 471         }
 472         /*
 473          * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
 474          * we must wait 100ms after this mode switch before touching
 475          * PCIe config space.
 476          */
 477         msleep(100);
 478
 479         return 0;
 480 }
 481
 482 static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
 483 {
 484         u64 p1n_base, p2n_base, afu_desc;
 485         const u64 p1n_size = 0x100;
 486         const u64 p2n_size = 0x1000;
 487
 488         p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
 489         p2n_base = p2_base(dev) + (afu->slice * p2n_size);
 490         afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size));
 491         afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size);
 492
 493         if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size)))
 494                 goto err;
 495         if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
 496                 goto err1;
 497         if (afu_desc) {
 498                 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size)))
 499                         goto err2;
 500         }
 501
 502         return 0;
 503 err2:
 504         iounmap(afu->p2n_mmio);
 505 err1:
 506         iounmap(afu->p1n_mmio);
 507 err:
 508         dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
 509         return -ENOMEM;
 510 }
 511
 512 static void cxl_unmap_slice_regs(struct cxl_afu *afu)
 513 {
 514         if (afu->p1n_mmio)
 515                 iounmap(afu->p2n_mmio);
 516         if (afu->p1n_mmio)
 517                 iounmap(afu->p1n_mmio);
 518 }
 519
 520 static void cxl_release_afu(struct device *dev)
 521 {
 522         struct cxl_afu *afu = to_cxl_afu(dev);
 523
 524         pr_devel("cxl_release_afu\n");
 525
 526         kfree(afu);
 527 }
 528
 529 static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
 530 {
 531         struct cxl_afu *afu;
 532
 533         if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
 534                 return NULL;
 535
 536         afu->adapter = adapter;
 537         afu->dev.parent = &adapter->dev;
 538         afu->dev.release = cxl_release_afu;
 539         afu->slice = slice;
 540         idr_init(&afu->contexts_idr);
 541         mutex_init(&afu->contexts_lock);
 542         spin_lock_init(&afu->afu_cntl_lock);
 543         mutex_init(&afu->spa_mutex);
 544
 545         afu->prefault_mode = CXL_PREFAULT_NONE;
 546         afu->irqs_max = afu->adapter->user_irqs;
 547
 548         return afu;
 549 }
 550
 551 /* Expects AFU struct to have recently been zeroed out */
 552 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
 553 {
 554         u64 val;
 555
 556         val = AFUD_READ_INFO(afu);
 557         afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
 558         afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
 559
 560         if (AFUD_AFU_DIRECTED(val))
 561                 afu->modes_supported |= CXL_MODE_DIRECTED;
 562         if (AFUD_DEDICATED_PROCESS(val))
 563                 afu->modes_supported |= CXL_MODE_DEDICATED;
 564         if (AFUD_TIME_SLICED(val))
 565                 afu->modes_supported |= CXL_MODE_TIME_SLICED;
 566
 567         val = AFUD_READ_PPPSA(afu);
 568         afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
 569         afu->psa = AFUD_PPPSA_PSA(val);
 570         if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
 571                 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
 572
 573         return 0;
 574 }
 575
 576 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
 577 {
 578         if (afu->psa && afu->adapter->ps_size <
 579                         (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
 580                 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
 581                 return -ENODEV;
 582         }
 583
 584         if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
 585                 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
 586
 587         return 0;
 588 }
 589
 590 static int sanitise_afu_regs(struct cxl_afu *afu)
 591 {
 592         u64 reg;
 593
 594         /*
 595          * Clear out any regs that contain either an IVTE or address or may be
 596          * waiting on an acknowledgement to try to be a bit safer as we bring
 597          * it online
 598          */
 599         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 600         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 601                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg);
 602                 if (cxl_afu_reset(afu))
 603                         return -EIO;
 604                 if (cxl_afu_disable(afu))
 605                         return -EIO;
 606                 if (cxl_psl_purge(afu))
 607                         return -EIO;
 608         }
 609         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 610         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
 611         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
 612         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
 613         cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
 614         cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
 615         cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
 616         cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
 617         cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
 618         cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
 619         cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
 620         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 621         if (reg) {
 622                 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg);
 623                 if (reg & CXL_PSL_DSISR_TRANS)
 624                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 625                 else
 626                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 627         }
 628         reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 629         if (reg) {
 630                 if (reg & ~0xffff)
 631                         dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg);
 632                 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
 633         }
 634         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 635         if (reg) {
 636                 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg);
 637                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
 644 {
 645         struct cxl_afu *afu;
 646         bool free = true;
 647         int rc;
 648
 649         if (!(afu = cxl_alloc_afu(adapter, slice)))
 650                 return -ENOMEM;
 651
 652         if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice)))
 653                 goto err1;
 654
 655         if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
 656                 goto err1;
 657
 658         if ((rc = sanitise_afu_regs(afu)))
 659                 goto err2;
 660
 661         /* We need to reset the AFU before we can read the AFU descriptor */
 662         if ((rc = cxl_afu_reset(afu)))
 663                 goto err2;
 664
 665         if (cxl_verbose)
 666                 dump_afu_descriptor(afu);
 667
 668         if ((rc = cxl_read_afu_descriptor(afu)))
 669                 goto err2;
 670
 671         if ((rc = cxl_afu_descriptor_looks_ok(afu)))
 672                 goto err2;
 673
 674         if ((rc = init_implementation_afu_regs(afu)))
 675                 goto err2;
 676
 677         if ((rc = cxl_register_serr_irq(afu)))
 678                 goto err2;
 679
 680         if ((rc = cxl_register_psl_irq(afu)))
 681                 goto err3;
 682
 683         /* Don't care if this fails */
 684         cxl_debugfs_afu_add(afu);
 685
 686         /*
 687          * After we call this function we must not free the afu directly, even
 688          * if it returns an error!
 689          */
 690         if ((rc = cxl_register_afu(afu)))
 691                 goto err_put1;
 692
 693         if ((rc = cxl_sysfs_afu_add(afu)))
 694                 goto err_put1;
 695
 696
 697         if ((rc = cxl_afu_select_best_mode(afu)))
 698                 goto err_put2;
 699
 700         adapter->afu[afu->slice] = afu;
 701
 702         return 0;
 703
 704 err_put2:
 705         cxl_sysfs_afu_remove(afu);
 706 err_put1:
 707         device_unregister(&afu->dev);
 708         free = false;
 709         cxl_debugfs_afu_remove(afu);
 710         cxl_release_psl_irq(afu);
 711 err3:
 712         cxl_release_serr_irq(afu);
 713 err2:
 714         cxl_unmap_slice_regs(afu);
 715 err1:
 716         if (free)
 717                 kfree(afu);
 718         return rc;
 719 }
 720
 721 static void cxl_remove_afu(struct cxl_afu *afu)
 722 {
 723         pr_devel("cxl_remove_afu\n");
 724
 725         if (!afu)
 726                 return;
 727
 728         cxl_sysfs_afu_remove(afu);
 729         cxl_debugfs_afu_remove(afu);
 730
 731         spin_lock(&afu->adapter->afu_list_lock);
 732         afu->adapter->afu[afu->slice] = NULL;
 733         spin_unlock(&afu->adapter->afu_list_lock);
 734
 735         cxl_context_detach_all(afu);
 736         cxl_afu_deactivate_mode(afu);
 737
 738         cxl_release_psl_irq(afu);
 739         cxl_release_serr_irq(afu);
 740         cxl_unmap_slice_regs(afu);
 741
 742         device_unregister(&afu->dev);
 743 }
 744
 745 int cxl_reset(struct cxl *adapter)
 746 {
 747         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 748         int rc;
 749         int i;
 750         u32 val;
 751
 752         dev_info(&dev->dev, "CXL reset\n");
 753
 754         for (i = 0; i < adapter->slices; i++)
 755                 cxl_remove_afu(adapter->afu[i]);
 756
 757         /* pcie_warm_reset requests a fundamental pci reset which includes a
 758          * PERST assert/deassert.  PERST triggers a loading of the image
 759          * if "user" or "factory" is selected in sysfs */
 760         if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
 761                 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
 762                 return rc;
 763         }
 764
 765         /* the PERST done above fences the PHB.  So, reset depends on EEH
 766          * to unbind the driver, tell Sapphire to reinit the PHB, and rebind
 767          * the driver.  Do an mmio read explictly to ensure EEH notices the
 768          * fenced PHB.  Retry for a few seconds before giving up. */
 769         i = 0;
 770         while (((val = mmio_read32be(adapter->p1_mmio)) != 0xffffffff) &&
 771                 (i < 5)) {
 772                 msleep(500);
 773                 i++;
 774         }
 775
 776         if (val != 0xffffffff)
 777                 dev_err(&dev->dev, "cxl: PERST failed to trigger EEH\n");
 778
 779         return rc;
 780 }
 781
 782 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
 783 {
 784         if (pci_request_region(dev, 2, "priv 2 regs"))
 785                 goto err1;
 786         if (pci_request_region(dev, 0, "priv 1 regs"))
 787                 goto err2;
 788
 789         pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",
 790                         p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
 791
 792         if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
 793                 goto err3;
 794
 795         if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
 796                 goto err4;
 797
 798         return 0;
 799
 800 err4:
 801         iounmap(adapter->p1_mmio);
 802         adapter->p1_mmio = NULL;
 803 err3:
 804         pci_release_region(dev, 0);
 805 err2:
 806         pci_release_region(dev, 2);
 807 err1:
 808         return -ENOMEM;
 809 }
 810
 811 static void cxl_unmap_adapter_regs(struct cxl *adapter)
 812 {
 813         if (adapter->p1_mmio)
 814                 iounmap(adapter->p1_mmio);
 815         if (adapter->p2_mmio)
 816                 iounmap(adapter->p2_mmio);
 817 }
 818
 819 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
 820 {
 821         int vsec;
 822         u32 afu_desc_off, afu_desc_size;
 823         u32 ps_off, ps_size;
 824         u16 vseclen;
 825         u8 image_state;
 826
 827         if (!(vsec = find_cxl_vsec(dev))) {
 828                 dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n");
 829                 return -ENODEV;
 830         }
 831
 832         CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
 833         if (vseclen < CXL_VSEC_MIN_SIZE) {
 834                 pr_err("ABORTING: CXL VSEC too short\n");
 835                 return -EINVAL;
 836         }
 837
 838         CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
 839         CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
 840         CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
 841         CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
 842         CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
 843         CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
 844         adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
 845         adapter->perst_loads_image = true;
 846         adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
 847
 848         CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
 849         CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
 850         CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
 851         CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
 852         CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
 853
 854         /* Convert everything to bytes, because there is NO WAY I'd look at the
 855          * code a month later and forget what units these are in ;-) */
 856         adapter->ps_off = ps_off * 64 * 1024;
 857         adapter->ps_size = ps_size * 64 * 1024;
 858         adapter->afu_desc_off = afu_desc_off * 64 * 1024;
 859         adapter->afu_desc_size = afu_desc_size *64 * 1024;
 860
 861         /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
 862         adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
 863
 864         return 0;
 865 }
 866
 867 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
 868 {
 869         if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
 870                 return -EBUSY;
 871
 872         if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
 873                 dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n");
 874                 return -EINVAL;
 875         }
 876
 877         if (!adapter->slices) {
 878                 /* Once we support dynamic reprogramming we can use the card if
 879                  * it supports loadable AFUs */
 880                 dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n");
 881                 return -EINVAL;
 882         }
 883
 884         if (!adapter->afu_desc_off || !adapter->afu_desc_size) {
 885                 dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n");
 886                 return -EINVAL;
 887         }
 888
 889         if (adapter->ps_size > p2_size(dev) - adapter->ps_off) {
 890                 dev_err(&adapter->dev, "ABORTING: Problem state size larger than "
 891                                    "available in BAR2: 0x%llx > 0x%llx\n",
 892                          adapter->ps_size, p2_size(dev) - adapter->ps_off);
 893                 return -EINVAL;
 894         }
 895
 896         return 0;
 897 }
 898
 899 static void cxl_release_adapter(struct device *dev)
 900 {
 901         struct cxl *adapter = to_cxl_adapter(dev);
 902
 903         pr_devel("cxl_release_adapter\n");
 904
 905         kfree(adapter);
 906 }
 907
 908 static struct cxl *cxl_alloc_adapter(struct pci_dev *dev)
 909 {
 910         struct cxl *adapter;
 911
 912         if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
 913                 return NULL;
 914
 915         adapter->dev.parent = &dev->dev;
 916         adapter->dev.release = cxl_release_adapter;
 917         pci_set_drvdata(dev, adapter);
 918         spin_lock_init(&adapter->afu_list_lock);
 919
 920         return adapter;
 921 }
 922
 923 static int sanitise_adapter_regs(struct cxl *adapter)
 924 {
 925         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
 926         return cxl_tlb_slb_invalidate(adapter);
 927 }
 928
 929 static struct cxl *cxl_init_adapter(struct pci_dev *dev)
 930 {
 931         struct cxl *adapter;
 932         bool free = true;
 933         int rc;
 934
 935
 936         if (!(adapter = cxl_alloc_adapter(dev)))
 937                 return ERR_PTR(-ENOMEM);
 938
 939         if ((rc = switch_card_to_cxl(dev)))
 940                 goto err1;
 941
 942         if ((rc = cxl_alloc_adapter_nr(adapter)))
 943                 goto err1;
 944
 945         if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)))
 946                 goto err2;
 947
 948         if ((rc = cxl_read_vsec(adapter, dev)))
 949                 goto err2;
 950
 951         if ((rc = cxl_vsec_looks_ok(adapter, dev)))
 952                 goto err2;
 953
 954         if ((rc = cxl_update_image_control(adapter)))
 955                 goto err2;
 956
 957         if ((rc = cxl_map_adapter_regs(adapter, dev)))
 958                 goto err2;
 959
 960         if ((rc = sanitise_adapter_regs(adapter)))
 961                 goto err2;
 962
 963         if ((rc = init_implementation_adapter_regs(adapter, dev)))
 964                 goto err3;
 965
 966         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
 967                 goto err3;
 968
 969         /* If recovery happened, the last step is to turn on snooping.
 970          * In the non-recovery case this has no effect */
 971         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {
 972                 goto err3;
 973         }
 974
 975         if ((rc = cxl_register_psl_err_irq(adapter)))
 976                 goto err3;
 977
 978         /* Don't care if this one fails: */
 979         cxl_debugfs_adapter_add(adapter);
 980
 981         /*
 982          * After we call this function we must not free the adapter directly,
 983          * even if it returns an error!
 984          */
 985         if ((rc = cxl_register_adapter(adapter)))
 986                 goto err_put1;
 987
 988         if ((rc = cxl_sysfs_adapter_add(adapter)))
 989                 goto err_put1;
 990
 991         return adapter;
 992
 993 err_put1:
 994         device_unregister(&adapter->dev);
 995         free = false;
 996         cxl_debugfs_adapter_remove(adapter);
 997         cxl_release_psl_err_irq(adapter);
 998 err3:
 999         cxl_unmap_adapter_regs(adapter);
1000 err2:
1001         cxl_remove_adapter_nr(adapter);
1002 err1:
1003         if (free)
1004                 kfree(adapter);
1005         return ERR_PTR(rc);
1006 }
1007
1008 static void cxl_remove_adapter(struct cxl *adapter)
1009 {
1010         struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1011
1012         pr_devel("cxl_release_adapter\n");
1013
1014         cxl_sysfs_adapter_remove(adapter);
1015         cxl_debugfs_adapter_remove(adapter);
1016         cxl_release_psl_err_irq(adapter);
1017         cxl_unmap_adapter_regs(adapter);
1018         cxl_remove_adapter_nr(adapter);
1019
1020         device_unregister(&adapter->dev);
1021
1022         pci_release_region(pdev, 0);
1023         pci_release_region(pdev, 2);
1024         pci_disable_device(pdev);
1025 }
1026
1027 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1028 {
1029         struct cxl *adapter;
1030         int slice;
1031         int rc;
1032
1033         pci_dev_get(dev);
1034
1035         if (cxl_verbose)
1036                 dump_cxl_config_space(dev);
1037
1038         if ((rc = setup_cxl_bars(dev)))
1039                 return rc;
1040
1041         if ((rc = pci_enable_device(dev))) {
1042                 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1043                 return rc;
1044         }
1045
1046         adapter = cxl_init_adapter(dev);
1047         if (IS_ERR(adapter)) {
1048                 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1049                 return PTR_ERR(adapter);
1050         }
1051
1052         for (slice = 0; slice < adapter->slices; slice++) {
1053                 if ((rc = cxl_init_afu(adapter, slice, dev)))
1054                         dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1055         }
1056
1057         return 0;
1058 }
1059
1060 static void cxl_remove(struct pci_dev *dev)
1061 {
1062         struct cxl *adapter = pci_get_drvdata(dev);
1063         int afu;
1064
1065         dev_warn(&dev->dev, "pci remove\n");
1066
1067         /*
1068          * Lock to prevent someone grabbing a ref through the adapter list as
1069          * we are removing it
1070          */
1071         for (afu = 0; afu < adapter->slices; afu++)
1072                 cxl_remove_afu(adapter->afu[afu]);
1073         cxl_remove_adapter(adapter);
1074 }
1075
1076 struct pci_driver cxl_pci_driver = {
1077         .name = "cxl-pci",
1078         .id_table = cxl_pci_tbl,
1079         .probe = cxl_probe,
1080         .remove = cxl_remove,
1081 };