2 * IBM Accelerator Family 'GenWQE'
4 * (C) Copyright IBM Corp. 2013
6 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
7 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
8 * Author: Michael Jung <mijung@de.ibm.com>
9 * Author: Michael Ruettger <michael@ibmra.de>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License (version 2 only)
13 * as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * Device Driver Control Block (DDCB) queue support. Definition of
23 * interrupt handlers for queue support as well as triggering the
24 * health monitor code in case of problems. The current hardware uses
25 * an MSI interrupt which is shared between error handling and
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/sched.h>
32 #include <linux/wait.h>
33 #include <linux/pci.h>
34 #include <linux/string.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include <linux/interrupt.h>
39 #include <linux/crc-itu-t.h>
41 #include "card_base.h"
42 #include "card_ddcb.h"
45 * N: next DDCB, this is where the next DDCB will be put.
46 * A: active DDCB, this is where the code will look for the next completion.
47 * x: DDCB is enqueued, we are waiting for its completion.
49 * Situation (1): Empty queue
50 * +---+---+---+---+---+---+---+---+
51 * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
53 * +---+---+---+---+---+---+---+---+
55 * enqueued_ddcbs = A - N = 2 - 2 = 0
57 * Situation (2): Wrapped, N > A
58 * +---+---+---+---+---+---+---+---+
59 * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
60 * | | | x | x | | | | |
61 * +---+---+---+---+---+---+---+---+
63 * enqueued_ddcbs = N - A = 4 - 2 = 2
65 * Situation (3): Queue wrapped, A > N
66 * +---+---+---+---+---+---+---+---+
67 * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
68 * | x | x | | | x | x | x | x |
69 * +---+---+---+---+---+---+---+---+
71 * enqueued_ddcbs = queue_max - (A - N) = 8 - (4 - 2) = 6
73 * Situation (4a): Queue full N > A
74 * +---+---+---+---+---+---+---+---+
75 * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
76 * | x | x | x | x | x | x | x | |
77 * +---+---+---+---+---+---+---+---+
80 * enqueued_ddcbs = N - A = 7 - 0 = 7
82 * Situation (4a): Queue full A > N
83 * +---+---+---+---+---+---+---+---+
84 * | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
85 * | x | x | x | | x | x | x | x |
86 * +---+---+---+---+---+---+---+---+
88 * enqueued_ddcbs = queue_max - (A - N) = 8 - (4 - 3) = 7
91 static int queue_empty(struct ddcb_queue *queue)
93 return queue->ddcb_next == queue->ddcb_act;
96 static int queue_enqueued_ddcbs(struct ddcb_queue *queue)
98 if (queue->ddcb_next >= queue->ddcb_act)
99 return queue->ddcb_next - queue->ddcb_act;
101 return queue->ddcb_max - (queue->ddcb_act - queue->ddcb_next);
104 static int queue_free_ddcbs(struct ddcb_queue *queue)
106 int free_ddcbs = queue->ddcb_max - queue_enqueued_ddcbs(queue) - 1;
108 if (WARN_ON_ONCE(free_ddcbs < 0)) { /* must never ever happen! */
115 * Use of the PRIV field in the DDCB for queue debugging:
117 * (1) Trying to get rid of a DDCB which saw a timeout:
118 * pddcb->priv[6] = 0xcc; # cleared
120 * (2) Append a DDCB via NEXT bit:
121 * pddcb->priv[7] = 0xaa; # appended
123 * (3) DDCB needed tapping:
124 * pddcb->priv[7] = 0xbb; # tapped
126 * (4) DDCB marked as correctly finished:
127 * pddcb->priv[6] = 0xff; # finished
130 static inline void ddcb_mark_tapped(struct ddcb *pddcb)
132 pddcb->priv[7] = 0xbb; /* tapped */
135 static inline void ddcb_mark_appended(struct ddcb *pddcb)
137 pddcb->priv[7] = 0xaa; /* appended */
140 static inline void ddcb_mark_cleared(struct ddcb *pddcb)
142 pddcb->priv[6] = 0xcc; /* cleared */
145 static inline void ddcb_mark_finished(struct ddcb *pddcb)
147 pddcb->priv[6] = 0xff; /* finished */
150 static inline void ddcb_mark_unused(struct ddcb *pddcb)
152 pddcb->priv_64 = cpu_to_be64(0); /* not tapped */
156 * genwqe_crc16() - Generate 16-bit crc as required for DDCBs
157 * @buff: pointer to data buffer
158 * @len: length of data for calculation
159 * @init: initial crc (0xffff at start)
161 * Polynomial = x^16 + x^12 + x^5 + 1 (0x1021)
162 * Example: 4 bytes 0x01 0x02 0x03 0x04 with init = 0xffff
163 * should result in a crc16 of 0x89c3
165 * Return: crc16 checksum in big endian format !
167 static inline u16 genwqe_crc16(const u8 *buff, size_t len, u16 init)
169 return crc_itu_t(init, buff, len);
172 static void print_ddcb_info(struct genwqe_dev *cd, struct ddcb_queue *queue)
177 struct pci_dev *pci_dev = cd->pci_dev;
179 spin_lock_irqsave(&cd->print_lock, flags);
181 dev_info(&pci_dev->dev,
182 "DDCB list for card #%d (ddcb_act=%d / ddcb_next=%d):\n",
183 cd->card_idx, queue->ddcb_act, queue->ddcb_next);
185 pddcb = queue->ddcb_vaddr;
186 for (i = 0; i < queue->ddcb_max; i++) {
187 dev_err(&pci_dev->dev,
188 " %c %-3d: RETC=%03x SEQ=%04x "
189 "HSI=%02X SHI=%02x PRIV=%06llx CMD=%03x\n",
190 i == queue->ddcb_act ? '>' : ' ',
192 be16_to_cpu(pddcb->retc_16),
193 be16_to_cpu(pddcb->seqnum_16),
196 be64_to_cpu(pddcb->priv_64),
200 spin_unlock_irqrestore(&cd->print_lock, flags);
203 struct genwqe_ddcb_cmd *ddcb_requ_alloc(void)
205 struct ddcb_requ *req;
207 req = kzalloc(sizeof(*req), GFP_ATOMIC);
214 void ddcb_requ_free(struct genwqe_ddcb_cmd *cmd)
216 struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
220 static inline enum genwqe_requ_state ddcb_requ_get_state(struct ddcb_requ *req)
222 return req->req_state;
225 static inline void ddcb_requ_set_state(struct ddcb_requ *req,
226 enum genwqe_requ_state new_state)
228 req->req_state = new_state;
231 static inline int ddcb_requ_collect_debug_data(struct ddcb_requ *req)
233 return req->cmd.ddata_addr != 0x0;
237 * ddcb_requ_finished() - Returns the hardware state of the associated DDCB
238 * @cd: pointer to genwqe device descriptor
239 * @req: DDCB work request
241 * Status of ddcb_requ mirrors this hardware state, but is copied in
242 * the ddcb_requ on interrupt/polling function. The lowlevel code
243 * should check the hardware state directly, the higher level code
244 * should check the copy.
246 * This function will also return true if the state of the queue is
247 * not GENWQE_CARD_USED. This enables us to purge all DDCBs in the
250 static int ddcb_requ_finished(struct genwqe_dev *cd, struct ddcb_requ *req)
252 return (ddcb_requ_get_state(req) == GENWQE_REQU_FINISHED) ||
253 (cd->card_state != GENWQE_CARD_USED);
257 * enqueue_ddcb() - Enqueue a DDCB
258 * @cd: pointer to genwqe device descriptor
259 * @queue: queue this operation should be done on
260 * @ddcb_no: pointer to ddcb number being tapped
262 * Start execution of DDCB by tapping or append to queue via NEXT
263 * bit. This is done by an atomic 'compare and swap' instruction and
264 * checking SHI and HSI of the previous DDCB.
266 * This function must only be called with ddcb_lock held.
268 * Return: 1 if new DDCB is appended to previous
269 * 2 if DDCB queue is tapped via register/simulation
271 #define RET_DDCB_APPENDED 1
272 #define RET_DDCB_TAPPED 2
274 static int enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_queue *queue,
275 struct ddcb *pddcb, int ddcb_no)
279 struct ddcb *prev_ddcb;
280 __be32 old, new, icrc_hsi_shi;
284 * For performance checks a Dispatch Timestamp can be put into
285 * DDCB It is supposed to use the SLU's free running counter,
286 * but this requires PCIe cycles.
288 ddcb_mark_unused(pddcb);
290 /* check previous DDCB if already fetched */
291 prev_no = (ddcb_no == 0) ? queue->ddcb_max - 1 : ddcb_no - 1;
292 prev_ddcb = &queue->ddcb_vaddr[prev_no];
295 * It might have happened that the HSI.FETCHED bit is
296 * set. Retry in this case. Therefore I expect maximum 2 times
299 ddcb_mark_appended(pddcb);
300 for (try = 0; try < 2; try++) {
301 old = prev_ddcb->icrc_hsi_shi_32; /* read SHI/HSI in BE32 */
303 /* try to append via NEXT bit if prev DDCB is not completed */
304 if ((old & DDCB_COMPLETED_BE32) != 0x00000000)
307 new = (old | DDCB_NEXT_BE32);
310 icrc_hsi_shi = cmpxchg(&prev_ddcb->icrc_hsi_shi_32, old, new);
312 if (icrc_hsi_shi == old)
313 return RET_DDCB_APPENDED; /* appended to queue */
316 /* Queue must be re-started by updating QUEUE_OFFSET */
317 ddcb_mark_tapped(pddcb);
318 num = (u64)ddcb_no << 8;
321 __genwqe_writeq(cd, queue->IO_QUEUE_OFFSET, num); /* start queue */
323 return RET_DDCB_TAPPED;
327 * copy_ddcb_results() - Copy output state from real DDCB to request
329 * Copy DDCB ASV to request struct. There is no endian
330 * conversion made, since data structure in ASV is still
334 * - genwqe_purge_ddcb()
335 * - genwqe_check_ddcb_queue()
337 static void copy_ddcb_results(struct ddcb_requ *req, int ddcb_no)
339 struct ddcb_queue *queue = req->queue;
340 struct ddcb *pddcb = &queue->ddcb_vaddr[req->num];
342 memcpy(&req->cmd.asv[0], &pddcb->asv[0], DDCB_ASV_LENGTH);
344 /* copy status flags of the variant part */
345 req->cmd.vcrc = be16_to_cpu(pddcb->vcrc_16);
346 req->cmd.deque_ts = be64_to_cpu(pddcb->deque_ts_64);
347 req->cmd.cmplt_ts = be64_to_cpu(pddcb->cmplt_ts_64);
349 req->cmd.attn = be16_to_cpu(pddcb->attn_16);
350 req->cmd.progress = be32_to_cpu(pddcb->progress_32);
351 req->cmd.retc = be16_to_cpu(pddcb->retc_16);
353 if (ddcb_requ_collect_debug_data(req)) {
354 int prev_no = (ddcb_no == 0) ?
355 queue->ddcb_max - 1 : ddcb_no - 1;
356 struct ddcb *prev_pddcb = &queue->ddcb_vaddr[prev_no];
358 memcpy(&req->debug_data.ddcb_finished, pddcb,
359 sizeof(req->debug_data.ddcb_finished));
360 memcpy(&req->debug_data.ddcb_prev, prev_pddcb,
361 sizeof(req->debug_data.ddcb_prev));
366 * genwqe_check_ddcb_queue() - Checks DDCB queue for completed work equests.
367 * @cd: pointer to genwqe device descriptor
369 * Return: Number of DDCBs which were finished
371 static int genwqe_check_ddcb_queue(struct genwqe_dev *cd,
372 struct ddcb_queue *queue)
375 int ddcbs_finished = 0;
376 struct pci_dev *pci_dev = cd->pci_dev;
378 spin_lock_irqsave(&queue->ddcb_lock, flags);
380 /* FIXME avoid soft locking CPU */
381 while (!queue_empty(queue) && (ddcbs_finished < queue->ddcb_max)) {
384 struct ddcb_requ *req;
385 u16 vcrc, vcrc_16, retc_16;
387 pddcb = &queue->ddcb_vaddr[queue->ddcb_act];
389 if ((pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) ==
391 goto go_home; /* not completed, continue waiting */
393 /* Note: DDCB could be purged */
395 req = queue->ddcb_req[queue->ddcb_act];
397 /* this occurs if DDCB is purged, not an error */
398 /* Move active DDCB further; Nothing to do anymore. */
403 * HSI=0x44 (fetched and completed), but RETC is
404 * 0x101, or even worse 0x000.
406 * In case of seeing the queue in inconsistent state
407 * we read the errcnts and the queue status to provide
408 * a trigger for our PCIe analyzer stop capturing.
410 retc_16 = be16_to_cpu(pddcb->retc_16);
411 if ((pddcb->hsi == 0x44) && (retc_16 <= 0x101)) {
413 u64 ddcb_offs = (u64)pddcb - (u64)queue->ddcb_vaddr;
415 errcnts = __genwqe_readq(cd, queue->IO_QUEUE_ERRCNTS);
416 status = __genwqe_readq(cd, queue->IO_QUEUE_STATUS);
418 dev_err(&pci_dev->dev,
419 "[%s] SEQN=%04x HSI=%02x RETC=%03x "
420 " Q_ERRCNTS=%016llx Q_STATUS=%016llx\n"
421 " DDCB_DMA_ADDR=%016llx\n",
422 __func__, be16_to_cpu(pddcb->seqnum_16),
423 pddcb->hsi, retc_16, errcnts, status,
424 queue->ddcb_daddr + ddcb_offs);
427 copy_ddcb_results(req, queue->ddcb_act);
428 queue->ddcb_req[queue->ddcb_act] = NULL; /* take from queue */
430 dev_dbg(&pci_dev->dev, "FINISHED DDCB#%d\n", req->num);
431 genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
433 ddcb_mark_finished(pddcb);
435 /* calculate CRC_16 to see if VCRC is correct */
436 vcrc = genwqe_crc16(pddcb->asv,
437 VCRC_LENGTH(req->cmd.asv_length),
439 vcrc_16 = be16_to_cpu(pddcb->vcrc_16);
440 if (vcrc != vcrc_16) {
441 printk_ratelimited(KERN_ERR
442 "%s %s: err: wrong VCRC pre=%02x vcrc_len=%d "
443 "bytes vcrc_data=%04x is not vcrc_card=%04x\n",
444 GENWQE_DEVNAME, dev_name(&pci_dev->dev),
445 pddcb->pre, VCRC_LENGTH(req->cmd.asv_length),
449 ddcb_requ_set_state(req, GENWQE_REQU_FINISHED);
450 queue->ddcbs_completed++;
451 queue->ddcbs_in_flight--;
453 /* wake up process waiting for this DDCB */
454 wake_up_interruptible(&queue->ddcb_waitqs[queue->ddcb_act]);
457 queue->ddcb_act = (queue->ddcb_act + 1) % queue->ddcb_max;
462 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
463 return ddcbs_finished;
467 * __genwqe_wait_ddcb(): Waits until DDCB is completed
468 * @cd: pointer to genwqe device descriptor
469 * @req: pointer to requsted DDCB parameters
471 * The Service Layer will update the RETC in DDCB when processing is
474 * Return: > 0 remaining jiffies, DDCB completed
475 * -ETIMEDOUT when timeout
476 * -ERESTARTSYS when ^C
477 * -EINVAL when unknown error condition
479 * When an error is returned the called needs to ensure that
480 * purge_ddcb() is being called to get the &req removed from the
483 int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
486 unsigned int ddcb_no;
487 struct ddcb_queue *queue;
488 struct pci_dev *pci_dev = cd->pci_dev;
498 if (ddcb_no >= queue->ddcb_max)
501 rc = wait_event_interruptible_timeout(queue->ddcb_waitqs[ddcb_no],
502 ddcb_requ_finished(cd, req),
503 genwqe_ddcb_software_timeout * HZ);
506 * We need to distinguish 3 cases here:
507 * 1. rc == 0 timeout occured
508 * 2. rc == -ERESTARTSYS signal received
509 * 3. rc > 0 remaining jiffies condition is true
512 struct ddcb_queue *queue = req->queue;
516 * Timeout may be caused by long task switching time.
517 * When timeout happens, check if the request has
518 * meanwhile completed.
520 genwqe_check_ddcb_queue(cd, req->queue);
521 if (ddcb_requ_finished(cd, req))
524 dev_err(&pci_dev->dev,
525 "[%s] err: DDCB#%d timeout rc=%d state=%d req @ %p\n",
526 __func__, req->num, rc, ddcb_requ_get_state(req),
528 dev_err(&pci_dev->dev,
529 "[%s] IO_QUEUE_STATUS=0x%016llx\n", __func__,
530 __genwqe_readq(cd, queue->IO_QUEUE_STATUS));
532 pddcb = &queue->ddcb_vaddr[req->num];
533 genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
535 print_ddcb_info(cd, req->queue);
538 } else if (rc == -ERESTARTSYS) {
541 * EINTR: Stops the application
542 * ERESTARTSYS: Restartable systemcall; called again
546 dev_err(&pci_dev->dev,
547 "[%s] err: DDCB#%d unknown result (rc=%d) %d!\n",
548 __func__, req->num, rc, ddcb_requ_get_state(req));
552 /* Severe error occured. Driver is forced to stop operation */
553 if (cd->card_state != GENWQE_CARD_USED) {
554 dev_err(&pci_dev->dev,
555 "[%s] err: DDCB#%d forced to stop (rc=%d)\n",
556 __func__, req->num, rc);
563 * get_next_ddcb() - Get next available DDCB
564 * @cd: pointer to genwqe device descriptor
566 * DDCB's content is completely cleared but presets for PRE and
567 * SEQNUM. This function must only be called when ddcb_lock is held.
569 * Return: NULL if no empty DDCB available otherwise ptr to next DDCB.
571 static struct ddcb *get_next_ddcb(struct genwqe_dev *cd,
572 struct ddcb_queue *queue,
578 if (queue_free_ddcbs(queue) == 0) /* queue is full */
582 pddcb = &queue->ddcb_vaddr[queue->ddcb_next];
584 /* if it is not completed, we are not allowed to use it */
586 if ((pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) == 0x00000000)
589 *num = queue->ddcb_next; /* internal DDCB number */
590 queue->ddcb_next = (queue->ddcb_next + 1) % queue->ddcb_max;
592 /* clear important DDCB fields */
594 pu64[0] = 0ULL; /* offs 0x00 (ICRC,HSI,SHI,...) */
595 pu64[1] = 0ULL; /* offs 0x01 (ACFUNC,CMD...) */
597 /* destroy previous results in ASV */
598 pu64[0x80/8] = 0ULL; /* offs 0x80 (ASV + 0) */
599 pu64[0x88/8] = 0ULL; /* offs 0x88 (ASV + 0x08) */
600 pu64[0x90/8] = 0ULL; /* offs 0x90 (ASV + 0x10) */
601 pu64[0x98/8] = 0ULL; /* offs 0x98 (ASV + 0x18) */
602 pu64[0xd0/8] = 0ULL; /* offs 0xd0 (RETC,ATTN...) */
604 pddcb->pre = DDCB_PRESET_PRE; /* 128 */
605 pddcb->seqnum_16 = cpu_to_be16(queue->ddcb_seq++);
610 * __genwqe_purge_ddcb() - Remove a DDCB from the workqueue
611 * @cd: genwqe device descriptor
614 * This will fail when the request was already FETCHED. In this case
615 * we need to wait until it is finished. Else the DDCB can be
616 * reused. This function also ensures that the request data structure
617 * is removed from ddcb_req[].
619 * Do not forget to call this function when genwqe_wait_ddcb() fails,
620 * such that the request gets really removed from ddcb_req[].
624 int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
626 struct ddcb *pddcb = NULL;
629 struct ddcb_queue *queue = req->queue;
630 struct pci_dev *pci_dev = cd->pci_dev;
632 __be32 icrc_hsi_shi = 0x0000;
635 /* unsigned long flags; */
636 if (genwqe_ddcb_software_timeout <= 0) {
637 dev_err(&pci_dev->dev,
638 "[%s] err: software timeout is not set!\n", __func__);
642 pddcb = &queue->ddcb_vaddr[req->num];
644 for (t = 0; t < genwqe_ddcb_software_timeout * 10; t++) {
646 spin_lock_irqsave(&queue->ddcb_lock, flags);
648 /* Check if req was meanwhile finished */
649 if (ddcb_requ_get_state(req) == GENWQE_REQU_FINISHED)
652 /* try to set PURGE bit if FETCHED/COMPLETED are not set */
653 old = pddcb->icrc_hsi_shi_32; /* read SHI/HSI in BE32 */
654 if ((old & DDCB_FETCHED_BE32) == 0x00000000) {
656 new = (old | DDCB_PURGE_BE32);
657 icrc_hsi_shi = cmpxchg(&pddcb->icrc_hsi_shi_32,
659 if (icrc_hsi_shi == old)
663 /* normal finish with HSI bit */
665 icrc_hsi_shi = pddcb->icrc_hsi_shi_32;
666 if (icrc_hsi_shi & DDCB_COMPLETED_BE32)
669 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
672 * Here the check_ddcb() function will most likely
673 * discover this DDCB to be finished some point in
674 * time. It will mark the req finished and free it up
678 copy_ddcb_results(req, req->num); /* for the failing case */
679 msleep(100); /* sleep for 1/10 second and try again */
683 copy_ddcb_results(req, req->num);
684 ddcb_requ_set_state(req, GENWQE_REQU_FINISHED);
685 queue->ddcbs_in_flight--;
686 queue->ddcb_req[req->num] = NULL; /* delete from array */
687 ddcb_mark_cleared(pddcb);
689 /* Move active DDCB further; Nothing to do here anymore. */
692 * We need to ensure that there is at least one free
693 * DDCB in the queue. To do that, we must update
694 * ddcb_act only if the COMPLETED bit is set for the
695 * DDCB we are working on else we treat that DDCB even
696 * if we PURGED it as occupied (hardware is supposed
697 * to set the COMPLETED bit yet!).
699 icrc_hsi_shi = pddcb->icrc_hsi_shi_32;
700 if ((icrc_hsi_shi & DDCB_COMPLETED_BE32) &&
701 (queue->ddcb_act == req->num)) {
702 queue->ddcb_act = ((queue->ddcb_act + 1) %
706 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
711 * If the card is dead and the queue is forced to stop, we
712 * might see this in the queue status register.
714 queue_status = __genwqe_readq(cd, queue->IO_QUEUE_STATUS);
716 dev_dbg(&pci_dev->dev, "UN/FINISHED DDCB#%d\n", req->num);
717 genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
719 dev_err(&pci_dev->dev,
720 "[%s] err: DDCB#%d not purged and not completed "
721 "after %d seconds QSTAT=%016llx!!\n",
722 __func__, req->num, genwqe_ddcb_software_timeout,
725 print_ddcb_info(cd, req->queue);
730 int genwqe_init_debug_data(struct genwqe_dev *cd, struct genwqe_debug_data *d)
733 struct pci_dev *pci_dev = cd->pci_dev;
736 dev_err(&pci_dev->dev,
737 "[%s] err: invalid memory for debug data!\n",
742 len = sizeof(d->driver_version);
743 snprintf(d->driver_version, len, "%s", DRV_VERS_STRING);
744 d->slu_unitcfg = cd->slu_unitcfg;
745 d->app_unitcfg = cd->app_unitcfg;
750 * __genwqe_enqueue_ddcb() - Enqueue a DDCB
751 * @cd: pointer to genwqe device descriptor
752 * @req: pointer to DDCB execution request
754 * Return: 0 if enqueuing succeeded
755 * -EIO if card is unusable/PCIe problems
756 * -EBUSY if enqueuing failed
758 int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req)
762 struct ddcb_queue *queue;
763 struct pci_dev *pci_dev = cd->pci_dev;
766 if (cd->card_state != GENWQE_CARD_USED) {
767 printk_ratelimited(KERN_ERR
768 "%s %s: [%s] Card is unusable/PCIe problem Req#%d\n",
769 GENWQE_DEVNAME, dev_name(&pci_dev->dev),
774 queue = req->queue = &cd->queue;
776 /* FIXME circumvention to improve performance when no irq is
779 if (genwqe_polling_enabled)
780 genwqe_check_ddcb_queue(cd, queue);
783 * It must be ensured to process all DDCBs in successive
784 * order. Use a lock here in order to prevent nested DDCB
787 spin_lock_irqsave(&queue->ddcb_lock, flags);
789 pddcb = get_next_ddcb(cd, queue, &req->num); /* get ptr and num */
791 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
796 if (queue->ddcb_req[req->num] != NULL) {
797 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
799 dev_err(&pci_dev->dev,
800 "[%s] picked DDCB %d with req=%p still in use!!\n",
801 __func__, req->num, req);
804 ddcb_requ_set_state(req, GENWQE_REQU_ENQUEUED);
805 queue->ddcb_req[req->num] = req;
807 pddcb->cmdopts_16 = cpu_to_be16(req->cmd.cmdopts);
808 pddcb->cmd = req->cmd.cmd;
809 pddcb->acfunc = req->cmd.acfunc; /* functional unit */
812 * We know that we can get retc 0x104 with CRC error, do not
813 * stop the queue in those cases for this command. XDIR = 1
814 * does not work for old SLU versions.
816 * Last bitstream with the old XDIR behavior had SLU_ID
819 if ((cd->slu_unitcfg & 0xFFFF0ull) > 0x34199ull)
825 pddcb->psp = (((req->cmd.asiv_length / 8) << 4) |
826 ((req->cmd.asv_length / 8)));
827 pddcb->disp_ts_64 = cpu_to_be64(req->cmd.disp_ts);
830 * If copying the whole DDCB_ASIV_LENGTH is impacting
831 * performance we need to change it to
832 * req->cmd.asiv_length. But simulation benefits from some
833 * non-architectured bits behind the architectured content.
835 * How much data is copied depends on the availability of the
836 * ATS field, which was introduced late. If the ATS field is
837 * supported ASIV is 8 bytes shorter than it used to be. Since
838 * the ATS field is copied too, the code should do exactly
839 * what it did before, but I wanted to make copying of the ATS
840 * field very explicit.
842 if (genwqe_get_slu_id(cd) <= 0x2) {
843 memcpy(&pddcb->__asiv[0], /* destination */
844 &req->cmd.__asiv[0], /* source */
845 DDCB_ASIV_LENGTH); /* req->cmd.asiv_length */
847 pddcb->n.ats_64 = cpu_to_be64(req->cmd.ats);
848 memcpy(&pddcb->n.asiv[0], /* destination */
849 &req->cmd.asiv[0], /* source */
850 DDCB_ASIV_LENGTH_ATS); /* req->cmd.asiv_length */
853 pddcb->icrc_hsi_shi_32 = cpu_to_be32(0x00000000); /* for crc */
856 * Calculate CRC_16 for corresponding range PSP(7:4). Include
857 * empty 4 bytes prior to the data.
859 icrc = genwqe_crc16((const u8 *)pddcb,
860 ICRC_LENGTH(req->cmd.asiv_length), 0xffff);
861 pddcb->icrc_hsi_shi_32 = cpu_to_be32((u32)icrc << 16);
863 /* enable DDCB completion irq */
864 if (!genwqe_polling_enabled)
865 pddcb->icrc_hsi_shi_32 |= DDCB_INTR_BE32;
867 dev_dbg(&pci_dev->dev, "INPUT DDCB#%d\n", req->num);
868 genwqe_hexdump(pci_dev, pddcb, sizeof(*pddcb));
870 if (ddcb_requ_collect_debug_data(req)) {
871 /* use the kernel copy of debug data. copying back to
872 user buffer happens later */
874 genwqe_init_debug_data(cd, &req->debug_data);
875 memcpy(&req->debug_data.ddcb_before, pddcb,
876 sizeof(req->debug_data.ddcb_before));
879 enqueue_ddcb(cd, queue, pddcb, req->num);
880 queue->ddcbs_in_flight++;
882 if (queue->ddcbs_in_flight > queue->ddcbs_max_in_flight)
883 queue->ddcbs_max_in_flight = queue->ddcbs_in_flight;
885 ddcb_requ_set_state(req, GENWQE_REQU_TAPPED);
886 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
887 wake_up_interruptible(&cd->queue_waitq);
893 * __genwqe_execute_raw_ddcb() - Setup and execute DDCB
894 * @cd: pointer to genwqe device descriptor
895 * @req: user provided DDCB request
897 int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
898 struct genwqe_ddcb_cmd *cmd)
901 struct pci_dev *pci_dev = cd->pci_dev;
902 struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
904 if (cmd->asiv_length > DDCB_ASIV_LENGTH) {
905 dev_err(&pci_dev->dev, "[%s] err: wrong asiv_length of %d\n",
906 __func__, cmd->asiv_length);
909 if (cmd->asv_length > DDCB_ASV_LENGTH) {
910 dev_err(&pci_dev->dev, "[%s] err: wrong asv_length of %d\n",
911 __func__, cmd->asiv_length);
914 rc = __genwqe_enqueue_ddcb(cd, req);
918 rc = __genwqe_wait_ddcb(cd, req);
919 if (rc < 0) /* error or signal interrupt */
922 if (ddcb_requ_collect_debug_data(req)) {
923 if (copy_to_user((struct genwqe_debug_data __user *)
924 (unsigned long)cmd->ddata_addr,
926 sizeof(struct genwqe_debug_data)))
931 * Higher values than 0x102 indicate completion with faults,
932 * lower values than 0x102 indicate processing faults. Note
933 * that DDCB might have been purged. E.g. Cntl+C.
935 if (cmd->retc != DDCB_RETC_COMPLETE) {
936 /* This might happen e.g. flash read, and needs to be
937 handled by the upper layer code. */
938 rc = -EBADMSG; /* not processed/error retc */
944 __genwqe_purge_ddcb(cd, req);
946 if (ddcb_requ_collect_debug_data(req)) {
947 if (copy_to_user((struct genwqe_debug_data __user *)
948 (unsigned long)cmd->ddata_addr,
950 sizeof(struct genwqe_debug_data)))
957 * genwqe_next_ddcb_ready() - Figure out if the next DDCB is already finished
959 * We use this as condition for our wait-queue code.
961 static int genwqe_next_ddcb_ready(struct genwqe_dev *cd)
965 struct ddcb_queue *queue = &cd->queue;
967 spin_lock_irqsave(&queue->ddcb_lock, flags);
969 if (queue_empty(queue)) { /* emtpy queue */
970 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
974 pddcb = &queue->ddcb_vaddr[queue->ddcb_act];
975 if (pddcb->icrc_hsi_shi_32 & DDCB_COMPLETED_BE32) { /* ddcb ready */
976 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
980 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
985 * genwqe_ddcbs_in_flight() - Check how many DDCBs are in flight
987 * Keep track on the number of DDCBs which ware currently in the
988 * queue. This is needed for statistics as well as conditon if we want
989 * to wait or better do polling in case of no interrupts available.
991 int genwqe_ddcbs_in_flight(struct genwqe_dev *cd)
994 int ddcbs_in_flight = 0;
995 struct ddcb_queue *queue = &cd->queue;
997 spin_lock_irqsave(&queue->ddcb_lock, flags);
998 ddcbs_in_flight += queue->ddcbs_in_flight;
999 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
1001 return ddcbs_in_flight;
1004 static int setup_ddcb_queue(struct genwqe_dev *cd, struct ddcb_queue *queue)
1009 unsigned int queue_size;
1010 struct pci_dev *pci_dev = cd->pci_dev;
1012 if (genwqe_ddcb_max < 2)
1015 queue_size = roundup(genwqe_ddcb_max * sizeof(struct ddcb), PAGE_SIZE);
1017 queue->ddcbs_in_flight = 0; /* statistics */
1018 queue->ddcbs_max_in_flight = 0;
1019 queue->ddcbs_completed = 0;
1022 queue->ddcb_seq = 0x100; /* start sequence number */
1023 queue->ddcb_max = genwqe_ddcb_max; /* module parameter */
1024 queue->ddcb_vaddr = __genwqe_alloc_consistent(cd, queue_size,
1025 &queue->ddcb_daddr);
1026 if (queue->ddcb_vaddr == NULL) {
1027 dev_err(&pci_dev->dev,
1028 "[%s] **err: could not allocate DDCB **\n", __func__);
1031 memset(queue->ddcb_vaddr, 0, queue_size);
1033 queue->ddcb_req = kzalloc(sizeof(struct ddcb_requ *) *
1034 queue->ddcb_max, GFP_KERNEL);
1035 if (!queue->ddcb_req) {
1040 queue->ddcb_waitqs = kzalloc(sizeof(wait_queue_head_t) *
1041 queue->ddcb_max, GFP_KERNEL);
1042 if (!queue->ddcb_waitqs) {
1047 for (i = 0; i < queue->ddcb_max; i++) {
1048 pddcb = &queue->ddcb_vaddr[i]; /* DDCBs */
1049 pddcb->icrc_hsi_shi_32 = DDCB_COMPLETED_BE32;
1050 pddcb->retc_16 = cpu_to_be16(0xfff);
1052 queue->ddcb_req[i] = NULL; /* requests */
1053 init_waitqueue_head(&queue->ddcb_waitqs[i]); /* waitqueues */
1056 queue->ddcb_act = 0;
1057 queue->ddcb_next = 0; /* queue is empty */
1059 spin_lock_init(&queue->ddcb_lock);
1060 init_waitqueue_head(&queue->ddcb_waitq);
1062 val64 = ((u64)(queue->ddcb_max - 1) << 8); /* lastptr */
1063 __genwqe_writeq(cd, queue->IO_QUEUE_CONFIG, 0x07); /* iCRC/vCRC */
1064 __genwqe_writeq(cd, queue->IO_QUEUE_SEGMENT, queue->ddcb_daddr);
1065 __genwqe_writeq(cd, queue->IO_QUEUE_INITSQN, queue->ddcb_seq);
1066 __genwqe_writeq(cd, queue->IO_QUEUE_WRAP, val64);
1070 kfree(queue->ddcb_req);
1071 queue->ddcb_req = NULL;
1073 __genwqe_free_consistent(cd, queue_size, queue->ddcb_vaddr,
1075 queue->ddcb_vaddr = NULL;
1076 queue->ddcb_daddr = 0ull;
1081 static int ddcb_queue_initialized(struct ddcb_queue *queue)
1083 return queue->ddcb_vaddr != NULL;
1086 static void free_ddcb_queue(struct genwqe_dev *cd, struct ddcb_queue *queue)
1088 unsigned int queue_size;
1090 queue_size = roundup(queue->ddcb_max * sizeof(struct ddcb), PAGE_SIZE);
1092 kfree(queue->ddcb_req);
1093 queue->ddcb_req = NULL;
1095 if (queue->ddcb_vaddr) {
1096 __genwqe_free_consistent(cd, queue_size, queue->ddcb_vaddr,
1098 queue->ddcb_vaddr = NULL;
1099 queue->ddcb_daddr = 0ull;
1103 static irqreturn_t genwqe_pf_isr(int irq, void *dev_id)
1106 struct genwqe_dev *cd = (struct genwqe_dev *)dev_id;
1107 struct pci_dev *pci_dev = cd->pci_dev;
1110 * In case of fatal FIR error the queue is stopped, such that
1111 * we can safely check it without risking anything.
1113 cd->irqs_processed++;
1114 wake_up_interruptible(&cd->queue_waitq);
1117 * Checking for errors before kicking the queue might be
1118 * safer, but slower for the good-case ... See above.
1120 gfir = __genwqe_readq(cd, IO_SLC_CFGREG_GFIR);
1121 if (((gfir & GFIR_ERR_TRIGGER) != 0x0) &&
1122 !pci_channel_offline(pci_dev)) {
1124 if (cd->use_platform_recovery) {
1126 * Since we use raw accessors, EEH errors won't be
1127 * detected by the platform until we do a non-raw
1128 * MMIO or config space read
1130 readq(cd->mmio + IO_SLC_CFGREG_GFIR);
1132 /* Don't do anything if the PCI channel is frozen */
1133 if (pci_channel_offline(pci_dev))
1137 wake_up_interruptible(&cd->health_waitq);
1140 * By default GFIRs causes recovery actions. This
1141 * count is just for debug when recovery is masked.
1143 dev_err_ratelimited(&pci_dev->dev,
1144 "[%s] GFIR=%016llx\n",
1152 static irqreturn_t genwqe_vf_isr(int irq, void *dev_id)
1154 struct genwqe_dev *cd = (struct genwqe_dev *)dev_id;
1156 cd->irqs_processed++;
1157 wake_up_interruptible(&cd->queue_waitq);
1163 * genwqe_card_thread() - Work thread for the DDCB queue
1165 * The idea is to check if there are DDCBs in processing. If there are
1166 * some finished DDCBs, we process them and wakeup the
1167 * requestors. Otherwise we give other processes time using
1170 static int genwqe_card_thread(void *data)
1172 int should_stop = 0, rc = 0;
1173 struct genwqe_dev *cd = (struct genwqe_dev *)data;
1175 while (!kthread_should_stop()) {
1177 genwqe_check_ddcb_queue(cd, &cd->queue);
1179 if (genwqe_polling_enabled) {
1180 rc = wait_event_interruptible_timeout(
1182 genwqe_ddcbs_in_flight(cd) ||
1183 (should_stop = kthread_should_stop()), 1);
1185 rc = wait_event_interruptible_timeout(
1187 genwqe_next_ddcb_ready(cd) ||
1188 (should_stop = kthread_should_stop()), HZ);
1194 * Avoid soft lockups on heavy loads; we do not want
1195 * to disable our interrupts.
1203 * genwqe_setup_service_layer() - Setup DDCB queue
1204 * @cd: pointer to genwqe device descriptor
1206 * Allocate DDCBs. Configure Service Layer Controller (SLC).
1210 int genwqe_setup_service_layer(struct genwqe_dev *cd)
1213 struct ddcb_queue *queue;
1214 struct pci_dev *pci_dev = cd->pci_dev;
1216 if (genwqe_is_privileged(cd)) {
1217 rc = genwqe_card_reset(cd);
1219 dev_err(&pci_dev->dev,
1220 "[%s] err: reset failed.\n", __func__);
1223 genwqe_read_softreset(cd);
1227 queue->IO_QUEUE_CONFIG = IO_SLC_QUEUE_CONFIG;
1228 queue->IO_QUEUE_STATUS = IO_SLC_QUEUE_STATUS;
1229 queue->IO_QUEUE_SEGMENT = IO_SLC_QUEUE_SEGMENT;
1230 queue->IO_QUEUE_INITSQN = IO_SLC_QUEUE_INITSQN;
1231 queue->IO_QUEUE_OFFSET = IO_SLC_QUEUE_OFFSET;
1232 queue->IO_QUEUE_WRAP = IO_SLC_QUEUE_WRAP;
1233 queue->IO_QUEUE_WTIME = IO_SLC_QUEUE_WTIME;
1234 queue->IO_QUEUE_ERRCNTS = IO_SLC_QUEUE_ERRCNTS;
1235 queue->IO_QUEUE_LRW = IO_SLC_QUEUE_LRW;
1237 rc = setup_ddcb_queue(cd, queue);
1243 init_waitqueue_head(&cd->queue_waitq);
1244 cd->card_thread = kthread_run(genwqe_card_thread, cd,
1245 GENWQE_DEVNAME "%d_thread",
1247 if (IS_ERR(cd->card_thread)) {
1248 rc = PTR_ERR(cd->card_thread);
1249 cd->card_thread = NULL;
1250 goto stop_free_queue;
1253 rc = genwqe_set_interrupt_capability(cd, GENWQE_MSI_IRQS);
1260 * We must have all wait-queues initialized when we enable the
1261 * interrupts. Otherwise we might crash if we get an early
1264 init_waitqueue_head(&cd->health_waitq);
1266 if (genwqe_is_privileged(cd)) {
1267 rc = request_irq(pci_dev->irq, genwqe_pf_isr, IRQF_SHARED,
1268 GENWQE_DEVNAME, cd);
1270 rc = request_irq(pci_dev->irq, genwqe_vf_isr, IRQF_SHARED,
1271 GENWQE_DEVNAME, cd);
1274 dev_err(&pci_dev->dev, "irq %d not free.\n", pci_dev->irq);
1278 cd->card_state = GENWQE_CARD_USED;
1282 genwqe_reset_interrupt_capability(cd);
1284 kthread_stop(cd->card_thread);
1285 cd->card_thread = NULL;
1287 free_ddcb_queue(cd, queue);
1293 * queue_wake_up_all() - Handles fatal error case
1295 * The PCI device got unusable and we have to stop all pending
1296 * requests as fast as we can. The code after this must purge the
1297 * DDCBs in question and ensure that all mappings are freed.
1299 static int queue_wake_up_all(struct genwqe_dev *cd)
1302 unsigned long flags;
1303 struct ddcb_queue *queue = &cd->queue;
1305 spin_lock_irqsave(&queue->ddcb_lock, flags);
1307 for (i = 0; i < queue->ddcb_max; i++)
1308 wake_up_interruptible(&queue->ddcb_waitqs[queue->ddcb_act]);
1310 spin_unlock_irqrestore(&queue->ddcb_lock, flags);
1316 * genwqe_finish_queue() - Remove any genwqe devices and user-interfaces
1318 * Relies on the pre-condition that there are no users of the card
1319 * device anymore e.g. with open file-descriptors.
1321 * This function must be robust enough to be called twice.
1323 int genwqe_finish_queue(struct genwqe_dev *cd)
1325 int i, rc = 0, in_flight;
1326 int waitmax = genwqe_ddcb_software_timeout;
1327 struct pci_dev *pci_dev = cd->pci_dev;
1328 struct ddcb_queue *queue = &cd->queue;
1330 if (!ddcb_queue_initialized(queue))
1333 /* Do not wipe out the error state. */
1334 if (cd->card_state == GENWQE_CARD_USED)
1335 cd->card_state = GENWQE_CARD_UNUSED;
1337 /* Wake up all requests in the DDCB queue such that they
1338 should be removed nicely. */
1339 queue_wake_up_all(cd);
1341 /* We must wait to get rid of the DDCBs in flight */
1342 for (i = 0; i < waitmax; i++) {
1343 in_flight = genwqe_ddcbs_in_flight(cd);
1348 dev_dbg(&pci_dev->dev,
1349 " DEBUG [%d/%d] waiting for queue to get empty: "
1350 "%d requests!\n", i, waitmax, in_flight);
1353 * Severe severe error situation: The card itself has
1354 * 16 DDCB queues, each queue has e.g. 32 entries,
1355 * each DDBC has a hardware timeout of currently 250
1356 * msec but the PFs have a hardware timeout of 8 sec
1357 * ... so I take something large.
1362 dev_err(&pci_dev->dev, " [%s] err: queue is not empty!!\n",
1370 * genwqe_release_service_layer() - Shutdown DDCB queue
1371 * @cd: genwqe device descriptor
1373 * This function must be robust enough to be called twice.
1375 int genwqe_release_service_layer(struct genwqe_dev *cd)
1377 struct pci_dev *pci_dev = cd->pci_dev;
1379 if (!ddcb_queue_initialized(&cd->queue))
1382 free_irq(pci_dev->irq, cd);
1383 genwqe_reset_interrupt_capability(cd);
1385 if (cd->card_thread != NULL) {
1386 kthread_stop(cd->card_thread);
1387 cd->card_thread = NULL;
1390 free_ddcb_queue(cd, &cd->queue);