2 * IBM Accelerator Family 'GenWQE'
4 * (C) Copyright IBM Corp. 2013
6 * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
7 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
8 * Author: Michael Jung <mijung@gmx.net>
9 * Author: Michael Ruettger <michael@ibmra.de>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License (version 2 only)
13 * as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * Character device representation of the GenWQE device. This allows
23 * user-space applications to communicate with the card.
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
32 #include <linux/sched.h>
33 #include <linux/wait.h>
34 #include <linux/delay.h>
35 #include <linux/atomic.h>
37 #include "card_base.h"
38 #include "card_ddcb.h"
40 static int genwqe_open_files(struct genwqe_dev *cd)
45 spin_lock_irqsave(&cd->file_lock, flags);
46 rc = list_empty(&cd->file_list);
47 spin_unlock_irqrestore(&cd->file_lock, flags);
51 static void genwqe_add_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
55 cfile->owner = current;
56 spin_lock_irqsave(&cd->file_lock, flags);
57 list_add(&cfile->list, &cd->file_list);
58 spin_unlock_irqrestore(&cd->file_lock, flags);
61 static int genwqe_del_file(struct genwqe_dev *cd, struct genwqe_file *cfile)
65 spin_lock_irqsave(&cd->file_lock, flags);
66 list_del(&cfile->list);
67 spin_unlock_irqrestore(&cd->file_lock, flags);
72 static void genwqe_add_pin(struct genwqe_file *cfile, struct dma_mapping *m)
76 spin_lock_irqsave(&cfile->pin_lock, flags);
77 list_add(&m->pin_list, &cfile->pin_list);
78 spin_unlock_irqrestore(&cfile->pin_lock, flags);
81 static int genwqe_del_pin(struct genwqe_file *cfile, struct dma_mapping *m)
85 spin_lock_irqsave(&cfile->pin_lock, flags);
86 list_del(&m->pin_list);
87 spin_unlock_irqrestore(&cfile->pin_lock, flags);
93 * genwqe_search_pin() - Search for the mapping for a userspace address
94 * @cfile: Descriptor of opened file
95 * @u_addr: User virtual address
96 * @size: Size of buffer
97 * @dma_addr: DMA address to be updated
99 * Return: Pointer to the corresponding mapping NULL if not found
101 static struct dma_mapping *genwqe_search_pin(struct genwqe_file *cfile,
102 unsigned long u_addr,
107 struct dma_mapping *m;
109 spin_lock_irqsave(&cfile->pin_lock, flags);
111 list_for_each_entry(m, &cfile->pin_list, pin_list) {
112 if ((((u64)m->u_vaddr) <= (u_addr)) &&
113 (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
116 *virt_addr = m->k_vaddr +
117 (u_addr - (u64)m->u_vaddr);
119 spin_unlock_irqrestore(&cfile->pin_lock, flags);
123 spin_unlock_irqrestore(&cfile->pin_lock, flags);
127 static void __genwqe_add_mapping(struct genwqe_file *cfile,
128 struct dma_mapping *dma_map)
132 spin_lock_irqsave(&cfile->map_lock, flags);
133 list_add(&dma_map->card_list, &cfile->map_list);
134 spin_unlock_irqrestore(&cfile->map_lock, flags);
137 static void __genwqe_del_mapping(struct genwqe_file *cfile,
138 struct dma_mapping *dma_map)
142 spin_lock_irqsave(&cfile->map_lock, flags);
143 list_del(&dma_map->card_list);
144 spin_unlock_irqrestore(&cfile->map_lock, flags);
149 * __genwqe_search_mapping() - Search for the mapping for a userspace address
150 * @cfile: descriptor of opened file
151 * @u_addr: user virtual address
152 * @size: size of buffer
153 * @dma_addr: DMA address to be updated
154 * Return: Pointer to the corresponding mapping NULL if not found
156 static struct dma_mapping *__genwqe_search_mapping(struct genwqe_file *cfile,
157 unsigned long u_addr,
159 dma_addr_t *dma_addr,
163 struct dma_mapping *m;
164 struct pci_dev *pci_dev = cfile->cd->pci_dev;
166 spin_lock_irqsave(&cfile->map_lock, flags);
167 list_for_each_entry(m, &cfile->map_list, card_list) {
169 if ((((u64)m->u_vaddr) <= (u_addr)) &&
170 (((u64)m->u_vaddr + m->size) >= (u_addr + size))) {
172 /* match found: current is as expected and
175 *dma_addr = m->dma_addr +
176 (u_addr - (u64)m->u_vaddr);
179 *virt_addr = m->k_vaddr +
180 (u_addr - (u64)m->u_vaddr);
182 spin_unlock_irqrestore(&cfile->map_lock, flags);
186 spin_unlock_irqrestore(&cfile->map_lock, flags);
188 dev_err(&pci_dev->dev,
189 "[%s] Entry not found: u_addr=%lx, size=%x\n",
190 __func__, u_addr, size);
195 static void genwqe_remove_mappings(struct genwqe_file *cfile)
198 struct list_head *node, *next;
199 struct dma_mapping *dma_map;
200 struct genwqe_dev *cd = cfile->cd;
201 struct pci_dev *pci_dev = cfile->cd->pci_dev;
203 list_for_each_safe(node, next, &cfile->map_list) {
204 dma_map = list_entry(node, struct dma_mapping, card_list);
206 list_del_init(&dma_map->card_list);
209 * This is really a bug, because those things should
210 * have been already tidied up.
212 * GENWQE_MAPPING_RAW should have been removed via mmunmap().
213 * GENWQE_MAPPING_SGL_TEMP should be removed by tidy up code.
215 dev_err(&pci_dev->dev,
216 "[%s] %d. cleanup mapping: u_vaddr=%p u_kaddr=%016lx dma_addr=%lx\n",
217 __func__, i++, dma_map->u_vaddr,
218 (unsigned long)dma_map->k_vaddr,
219 (unsigned long)dma_map->dma_addr);
221 if (dma_map->type == GENWQE_MAPPING_RAW) {
222 /* we allocated this dynamically */
223 __genwqe_free_consistent(cd, dma_map->size,
227 } else if (dma_map->type == GENWQE_MAPPING_SGL_TEMP) {
228 /* we use dma_map statically from the request */
229 genwqe_user_vunmap(cd, dma_map, NULL);
234 static void genwqe_remove_pinnings(struct genwqe_file *cfile)
236 struct list_head *node, *next;
237 struct dma_mapping *dma_map;
238 struct genwqe_dev *cd = cfile->cd;
240 list_for_each_safe(node, next, &cfile->pin_list) {
241 dma_map = list_entry(node, struct dma_mapping, pin_list);
244 * This is not a bug, because a killed processed might
245 * not call the unpin ioctl, which is supposed to free
248 * Pinnings are dymically allocated and need to be
251 list_del_init(&dma_map->pin_list);
252 genwqe_user_vunmap(cd, dma_map, NULL);
258 * genwqe_kill_fasync() - Send signal to all processes with open GenWQE files
260 * E.g. genwqe_send_signal(cd, SIGIO);
262 static int genwqe_kill_fasync(struct genwqe_dev *cd, int sig)
264 unsigned int files = 0;
266 struct genwqe_file *cfile;
268 spin_lock_irqsave(&cd->file_lock, flags);
269 list_for_each_entry(cfile, &cd->file_list, list) {
270 if (cfile->async_queue)
271 kill_fasync(&cfile->async_queue, sig, POLL_HUP);
274 spin_unlock_irqrestore(&cd->file_lock, flags);
278 static int genwqe_force_sig(struct genwqe_dev *cd, int sig)
280 unsigned int files = 0;
282 struct genwqe_file *cfile;
284 spin_lock_irqsave(&cd->file_lock, flags);
285 list_for_each_entry(cfile, &cd->file_list, list) {
286 force_sig(sig, cfile->owner);
289 spin_unlock_irqrestore(&cd->file_lock, flags);
294 * genwqe_open() - file open
295 * @inode: file system information
298 * This function is executed whenever an application calls
299 * open("/dev/genwqe",..).
301 * Return: 0 if successful or <0 if errors
303 static int genwqe_open(struct inode *inode, struct file *filp)
305 struct genwqe_dev *cd;
306 struct genwqe_file *cfile;
307 struct pci_dev *pci_dev;
309 cfile = kzalloc(sizeof(*cfile), GFP_KERNEL);
313 cd = container_of(inode->i_cdev, struct genwqe_dev, cdev_genwqe);
314 pci_dev = cd->pci_dev;
317 cfile->client = NULL;
319 spin_lock_init(&cfile->map_lock); /* list of raw memory allocations */
320 INIT_LIST_HEAD(&cfile->map_list);
322 spin_lock_init(&cfile->pin_lock); /* list of user pinned memory */
323 INIT_LIST_HEAD(&cfile->pin_list);
325 filp->private_data = cfile;
327 genwqe_add_file(cd, cfile);
332 * genwqe_fasync() - Setup process to receive SIGIO.
333 * @fd: file descriptor
337 * Sending a signal is working as following:
339 * if (cdev->async_queue)
340 * kill_fasync(&cdev->async_queue, SIGIO, POLL_IN);
342 * Some devices also implement asynchronous notification to indicate
343 * when the device can be written; in this case, of course,
344 * kill_fasync must be called with a mode of POLL_OUT.
346 static int genwqe_fasync(int fd, struct file *filp, int mode)
348 struct genwqe_file *cdev = (struct genwqe_file *)filp->private_data;
350 return fasync_helper(fd, filp, mode, &cdev->async_queue);
355 * genwqe_release() - file close
356 * @inode: file system information
359 * This function is executed whenever an application calls 'close(fd_genwqe)'
363 static int genwqe_release(struct inode *inode, struct file *filp)
365 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
366 struct genwqe_dev *cd = cfile->cd;
368 /* there must be no entries in these lists! */
369 genwqe_remove_mappings(cfile);
370 genwqe_remove_pinnings(cfile);
372 /* remove this filp from the asynchronously notified filp's */
373 genwqe_fasync(-1, filp, 0);
376 * For this to work we must not release cd when this cfile is
377 * not yet released, otherwise the list entry is invalid,
378 * because the list itself gets reinstantiated!
380 genwqe_del_file(cd, cfile);
385 static void genwqe_vma_open(struct vm_area_struct *vma)
391 * genwqe_vma_close() - Called each time when vma is unmapped
393 * Free memory which got allocated by GenWQE mmap().
395 static void genwqe_vma_close(struct vm_area_struct *vma)
397 unsigned long vsize = vma->vm_end - vma->vm_start;
398 struct inode *inode = file_inode(vma->vm_file);
399 struct dma_mapping *dma_map;
400 struct genwqe_dev *cd = container_of(inode->i_cdev, struct genwqe_dev,
402 struct pci_dev *pci_dev = cd->pci_dev;
403 dma_addr_t d_addr = 0;
404 struct genwqe_file *cfile = vma->vm_private_data;
406 dma_map = __genwqe_search_mapping(cfile, vma->vm_start, vsize,
408 if (dma_map == NULL) {
409 dev_err(&pci_dev->dev,
410 " [%s] err: mapping not found: v=%lx, p=%lx s=%lx\n",
411 __func__, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
415 __genwqe_del_mapping(cfile, dma_map);
416 __genwqe_free_consistent(cd, dma_map->size, dma_map->k_vaddr,
421 static struct vm_operations_struct genwqe_vma_ops = {
422 .open = genwqe_vma_open,
423 .close = genwqe_vma_close,
427 * genwqe_mmap() - Provide contignous buffers to userspace
429 * We use mmap() to allocate contignous buffers used for DMA
430 * transfers. After the buffer is allocated we remap it to user-space
431 * and remember a reference to our dma_mapping data structure, where
432 * we store the associated DMA address and allocated size.
434 * When we receive a DDCB execution request with the ATS bits set to
435 * plain buffer, we lookup our dma_mapping list to find the
436 * corresponding DMA address for the associated user-space address.
438 static int genwqe_mmap(struct file *filp, struct vm_area_struct *vma)
441 unsigned long pfn, vsize = vma->vm_end - vma->vm_start;
442 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
443 struct genwqe_dev *cd = cfile->cd;
444 struct dma_mapping *dma_map;
449 if (get_order(vsize) > MAX_ORDER)
452 dma_map = kzalloc(sizeof(struct dma_mapping), GFP_ATOMIC);
456 genwqe_mapping_init(dma_map, GENWQE_MAPPING_RAW);
457 dma_map->u_vaddr = (void *)vma->vm_start;
458 dma_map->size = vsize;
459 dma_map->nr_pages = DIV_ROUND_UP(vsize, PAGE_SIZE);
460 dma_map->k_vaddr = __genwqe_alloc_consistent(cd, vsize,
462 if (dma_map->k_vaddr == NULL) {
467 if (capable(CAP_SYS_ADMIN) && (vsize > sizeof(dma_addr_t)))
468 *(dma_addr_t *)dma_map->k_vaddr = dma_map->dma_addr;
470 pfn = virt_to_phys(dma_map->k_vaddr) >> PAGE_SHIFT;
471 rc = remap_pfn_range(vma,
481 vma->vm_private_data = cfile;
482 vma->vm_ops = &genwqe_vma_ops;
483 __genwqe_add_mapping(cfile, dma_map);
488 __genwqe_free_consistent(cd, dma_map->size,
497 * do_flash_update() - Excute flash update (write image or CVPD)
499 * @load: details about image load
501 * Return: 0 if successful
504 #define FLASH_BLOCK 0x40000 /* we use 256k blocks */
506 static int do_flash_update(struct genwqe_file *cfile,
507 struct genwqe_bitstream *load)
518 struct genwqe_dev *cd = cfile->cd;
519 struct file *filp = cfile->filp;
520 struct pci_dev *pci_dev = cd->pci_dev;
522 if ((load->size & 0x3) != 0)
525 if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
528 /* FIXME Bits have changed for new service layer! */
529 switch ((char)load->partition) {
532 break; /* download/erase_first/part_0 */
535 break; /* download/erase_first/part_1 */
538 break; /* download/erase_first/vpd */
543 buf = (u8 __user *)load->data_addr;
544 xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
548 blocks_to_flash = load->size / FLASH_BLOCK;
550 struct genwqe_ddcb_cmd *req;
553 * We must be 4 byte aligned. Buffer must be 0 appened
554 * to have defined values when calculating CRC.
556 tocopy = min_t(size_t, load->size, FLASH_BLOCK);
558 rc = copy_from_user(xbuf, buf, tocopy);
563 crc = genwqe_crc32(xbuf, tocopy, 0xffffffff);
565 dev_dbg(&pci_dev->dev,
566 "[%s] DMA: %lx CRC: %08x SZ: %ld %d\n",
567 __func__, (unsigned long)dma_addr, crc, tocopy,
570 /* prepare DDCB for SLU process */
571 req = ddcb_requ_alloc();
577 req->cmd = SLCMD_MOVE_FLASH;
578 req->cmdopts = cmdopts;
580 /* prepare invariant values */
581 if (genwqe_get_slu_id(cd) <= 0x2) {
582 *(__be64 *)&req->__asiv[0] = cpu_to_be64(dma_addr);
583 *(__be64 *)&req->__asiv[8] = cpu_to_be64(tocopy);
584 *(__be64 *)&req->__asiv[16] = cpu_to_be64(flash);
585 *(__be32 *)&req->__asiv[24] = cpu_to_be32(0);
586 req->__asiv[24] = load->uid;
587 *(__be32 *)&req->__asiv[28] = cpu_to_be32(crc);
589 /* for simulation only */
590 *(__be64 *)&req->__asiv[88] = cpu_to_be64(load->slu_id);
591 *(__be64 *)&req->__asiv[96] = cpu_to_be64(load->app_id);
592 req->asiv_length = 32; /* bytes included in crc calc */
593 } else { /* setup DDCB for ATS architecture */
594 *(__be64 *)&req->asiv[0] = cpu_to_be64(dma_addr);
595 *(__be32 *)&req->asiv[8] = cpu_to_be32(tocopy);
596 *(__be32 *)&req->asiv[12] = cpu_to_be32(0); /* resvd */
597 *(__be64 *)&req->asiv[16] = cpu_to_be64(flash);
598 *(__be32 *)&req->asiv[24] = cpu_to_be32(load->uid<<24);
599 *(__be32 *)&req->asiv[28] = cpu_to_be32(crc);
601 /* for simulation only */
602 *(__be64 *)&req->asiv[80] = cpu_to_be64(load->slu_id);
603 *(__be64 *)&req->asiv[88] = cpu_to_be64(load->app_id);
606 req->ats = 0x4ULL << 44;
607 req->asiv_length = 40; /* bytes included in crc calc */
611 /* For Genwqe5 we get back the calculated CRC */
612 *(u64 *)&req->asv[0] = 0ULL; /* 0x80 */
614 rc = __genwqe_execute_raw_ddcb(cd, req, filp->f_flags);
616 load->retc = req->retc;
617 load->attn = req->attn;
618 load->progress = req->progress;
625 if (req->retc != DDCB_RETC_COMPLETE) {
631 load->size -= tocopy;
639 __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
643 static int do_flash_read(struct genwqe_file *cfile,
644 struct genwqe_bitstream *load)
646 int rc, blocks_to_flash;
653 struct genwqe_dev *cd = cfile->cd;
654 struct file *filp = cfile->filp;
655 struct pci_dev *pci_dev = cd->pci_dev;
656 struct genwqe_ddcb_cmd *cmd;
658 if ((load->size & 0x3) != 0)
661 if (((unsigned long)(load->data_addr) & ~PAGE_MASK) != 0)
664 /* FIXME Bits have changed for new service layer! */
665 switch ((char)load->partition) {
668 break; /* upload/part_0 */
671 break; /* upload/part_1 */
674 break; /* upload/vpd */
679 buf = (u8 __user *)load->data_addr;
680 xbuf = __genwqe_alloc_consistent(cd, FLASH_BLOCK, &dma_addr);
684 blocks_to_flash = load->size / FLASH_BLOCK;
687 * We must be 4 byte aligned. Buffer must be 0 appened
688 * to have defined values when calculating CRC.
690 tocopy = min_t(size_t, load->size, FLASH_BLOCK);
692 dev_dbg(&pci_dev->dev,
693 "[%s] DMA: %lx SZ: %ld %d\n",
694 __func__, (unsigned long)dma_addr, tocopy,
697 /* prepare DDCB for SLU process */
698 cmd = ddcb_requ_alloc();
703 cmd->cmd = SLCMD_MOVE_FLASH;
704 cmd->cmdopts = cmdopts;
706 /* prepare invariant values */
707 if (genwqe_get_slu_id(cd) <= 0x2) {
708 *(__be64 *)&cmd->__asiv[0] = cpu_to_be64(dma_addr);
709 *(__be64 *)&cmd->__asiv[8] = cpu_to_be64(tocopy);
710 *(__be64 *)&cmd->__asiv[16] = cpu_to_be64(flash);
711 *(__be32 *)&cmd->__asiv[24] = cpu_to_be32(0);
712 cmd->__asiv[24] = load->uid;
713 *(__be32 *)&cmd->__asiv[28] = cpu_to_be32(0) /* CRC */;
714 cmd->asiv_length = 32; /* bytes included in crc calc */
715 } else { /* setup DDCB for ATS architecture */
716 *(__be64 *)&cmd->asiv[0] = cpu_to_be64(dma_addr);
717 *(__be32 *)&cmd->asiv[8] = cpu_to_be32(tocopy);
718 *(__be32 *)&cmd->asiv[12] = cpu_to_be32(0); /* resvd */
719 *(__be64 *)&cmd->asiv[16] = cpu_to_be64(flash);
720 *(__be32 *)&cmd->asiv[24] = cpu_to_be32(load->uid<<24);
721 *(__be32 *)&cmd->asiv[28] = cpu_to_be32(0); /* CRC */
724 cmd->ats = 0x5ULL << 44;
725 cmd->asiv_length = 40; /* bytes included in crc calc */
729 /* we only get back the calculated CRC */
730 *(u64 *)&cmd->asv[0] = 0ULL; /* 0x80 */
732 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
734 load->retc = cmd->retc;
735 load->attn = cmd->attn;
736 load->progress = cmd->progress;
738 if ((rc < 0) && (rc != -EBADMSG)) {
743 rc = copy_to_user(buf, xbuf, tocopy);
750 /* We know that we can get retc 0x104 with CRC err */
751 if (((cmd->retc == DDCB_RETC_FAULT) &&
752 (cmd->attn != 0x02)) || /* Normally ignore CRC error */
753 ((cmd->retc == DDCB_RETC_COMPLETE) &&
754 (cmd->attn != 0x00))) { /* Everything was fine */
760 load->size -= tocopy;
769 __genwqe_free_consistent(cd, FLASH_BLOCK, xbuf, dma_addr);
773 static int genwqe_pin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
776 struct genwqe_dev *cd = cfile->cd;
777 struct pci_dev *pci_dev = cfile->cd->pci_dev;
778 struct dma_mapping *dma_map;
779 unsigned long map_addr;
780 unsigned long map_size;
782 if ((m->addr == 0x0) || (m->size == 0))
785 map_addr = (m->addr & PAGE_MASK);
786 map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
788 dma_map = kzalloc(sizeof(struct dma_mapping), GFP_ATOMIC);
792 genwqe_mapping_init(dma_map, GENWQE_MAPPING_SGL_PINNED);
793 rc = genwqe_user_vmap(cd, dma_map, (void *)map_addr, map_size, NULL);
795 dev_err(&pci_dev->dev,
796 "[%s] genwqe_user_vmap rc=%d\n", __func__, rc);
801 genwqe_add_pin(cfile, dma_map);
805 static int genwqe_unpin_mem(struct genwqe_file *cfile, struct genwqe_mem *m)
807 struct genwqe_dev *cd = cfile->cd;
808 struct dma_mapping *dma_map;
809 unsigned long map_addr;
810 unsigned long map_size;
815 map_addr = (m->addr & PAGE_MASK);
816 map_size = round_up(m->size + (m->addr & ~PAGE_MASK), PAGE_SIZE);
818 dma_map = genwqe_search_pin(cfile, map_addr, map_size, NULL);
822 genwqe_del_pin(cfile, dma_map);
823 genwqe_user_vunmap(cd, dma_map, NULL);
829 * ddcb_cmd_cleanup() - Remove dynamically created fixup entries
831 * Only if there are any. Pinnings are not removed.
833 static int ddcb_cmd_cleanup(struct genwqe_file *cfile, struct ddcb_requ *req)
836 struct dma_mapping *dma_map;
837 struct genwqe_dev *cd = cfile->cd;
839 for (i = 0; i < DDCB_FIXUPS; i++) {
840 dma_map = &req->dma_mappings[i];
842 if (dma_mapping_used(dma_map)) {
843 __genwqe_del_mapping(cfile, dma_map);
844 genwqe_user_vunmap(cd, dma_map, req);
846 if (req->sgls[i].sgl != NULL)
847 genwqe_free_sync_sgl(cd, &req->sgls[i]);
853 * ddcb_cmd_fixups() - Establish DMA fixups/sglists for user memory references
855 * Before the DDCB gets executed we need to handle the fixups. We
856 * replace the user-space addresses with DMA addresses or do
857 * additional setup work e.g. generating a scatter-gather list which
858 * is used to describe the memory referred to in the fixup.
860 static int ddcb_cmd_fixups(struct genwqe_file *cfile, struct ddcb_requ *req)
863 unsigned int asiv_offs, i;
864 struct genwqe_dev *cd = cfile->cd;
865 struct genwqe_ddcb_cmd *cmd = &req->cmd;
866 struct dma_mapping *m;
867 const char *type = "UNKNOWN";
869 for (i = 0, asiv_offs = 0x00; asiv_offs <= 0x58;
870 i++, asiv_offs += 0x08) {
877 ats_flags = ATS_GET_FLAGS(cmd->ats, asiv_offs);
882 break; /* nothing to do here */
884 case ATS_TYPE_FLAT_RDWR:
885 case ATS_TYPE_FLAT_RD: {
886 u_addr = be64_to_cpu(*((__be64 *)&cmd->
888 u_size = be32_to_cpu(*((__be32 *)&cmd->
889 asiv[asiv_offs + 0x08]));
892 * No data available. Ignore u_addr in this
893 * case and set addr to 0. Hardware must not
897 *((__be64 *)&cmd->asiv[asiv_offs]) =
902 m = __genwqe_search_mapping(cfile, u_addr, u_size,
909 *((__be64 *)&cmd->asiv[asiv_offs]) =
914 case ATS_TYPE_SGL_RDWR:
915 case ATS_TYPE_SGL_RD: {
918 u_addr = be64_to_cpu(*((__be64 *)
919 &cmd->asiv[asiv_offs]));
920 u_size = be32_to_cpu(*((__be32 *)
921 &cmd->asiv[asiv_offs + 0x08]));
924 * No data available. Ignore u_addr in this
925 * case and set addr to 0. Hardware must not
926 * fetch the empty sgl.
929 *((__be64 *)&cmd->asiv[asiv_offs]) =
934 m = genwqe_search_pin(cfile, u_addr, u_size, NULL);
937 page_offs = (u_addr -
938 (u64)m->u_vaddr)/PAGE_SIZE;
941 m = &req->dma_mappings[i];
943 genwqe_mapping_init(m,
944 GENWQE_MAPPING_SGL_TEMP);
945 rc = genwqe_user_vmap(cd, m, (void *)u_addr,
950 __genwqe_add_mapping(cfile, m);
954 /* create genwqe style scatter gather list */
955 rc = genwqe_alloc_sync_sgl(cd, &req->sgls[i],
956 (void __user *)u_addr,
961 genwqe_setup_sgl(cd, &req->sgls[i],
962 &m->dma_list[page_offs]);
964 *((__be64 *)&cmd->asiv[asiv_offs]) =
965 cpu_to_be64(req->sgls[i].sgl_dma_addr);
977 ddcb_cmd_cleanup(cfile, req);
982 * genwqe_execute_ddcb() - Execute DDCB using userspace address fixups
984 * The code will build up the translation tables or lookup the
985 * contignous memory allocation table to find the right translations
988 static int genwqe_execute_ddcb(struct genwqe_file *cfile,
989 struct genwqe_ddcb_cmd *cmd)
992 struct genwqe_dev *cd = cfile->cd;
993 struct file *filp = cfile->filp;
994 struct ddcb_requ *req = container_of(cmd, struct ddcb_requ, cmd);
996 rc = ddcb_cmd_fixups(cfile, req);
1000 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
1001 ddcb_cmd_cleanup(cfile, req);
1005 static int do_execute_ddcb(struct genwqe_file *cfile,
1006 unsigned long arg, int raw)
1009 struct genwqe_ddcb_cmd *cmd;
1010 struct ddcb_requ *req;
1011 struct genwqe_dev *cd = cfile->cd;
1012 struct file *filp = cfile->filp;
1014 cmd = ddcb_requ_alloc();
1018 req = container_of(cmd, struct ddcb_requ, cmd);
1020 if (copy_from_user(cmd, (void __user *)arg, sizeof(*cmd))) {
1021 ddcb_requ_free(cmd);
1026 rc = genwqe_execute_ddcb(cfile, cmd);
1028 rc = __genwqe_execute_raw_ddcb(cd, cmd, filp->f_flags);
1030 /* Copy back only the modifed fields. Do not copy ASIV
1031 back since the copy got modified by the driver. */
1032 if (copy_to_user((void __user *)arg, cmd,
1033 sizeof(*cmd) - DDCB_ASIV_LENGTH)) {
1034 ddcb_requ_free(cmd);
1038 ddcb_requ_free(cmd);
1043 * genwqe_ioctl() - IO control
1044 * @filp: file handle
1045 * @cmd: command identifier (passed from user)
1046 * @arg: argument (passed from user)
1050 static long genwqe_ioctl(struct file *filp, unsigned int cmd,
1054 struct genwqe_file *cfile = (struct genwqe_file *)filp->private_data;
1055 struct genwqe_dev *cd = cfile->cd;
1056 struct pci_dev *pci_dev = cd->pci_dev;
1057 struct genwqe_reg_io __user *io;
1061 /* Return -EIO if card hit EEH */
1062 if (pci_channel_offline(pci_dev))
1065 if (_IOC_TYPE(cmd) != GENWQE_IOC_CODE)
1070 case GENWQE_GET_CARD_STATE:
1071 put_user(cd->card_state, (enum genwqe_card_state __user *)arg);
1074 /* Register access */
1075 case GENWQE_READ_REG64: {
1076 io = (struct genwqe_reg_io __user *)arg;
1078 if (get_user(reg_offs, &io->num))
1081 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
1084 val = __genwqe_readq(cd, reg_offs);
1085 put_user(val, &io->val64);
1089 case GENWQE_WRITE_REG64: {
1090 io = (struct genwqe_reg_io __user *)arg;
1092 if (!capable(CAP_SYS_ADMIN))
1095 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1098 if (get_user(reg_offs, &io->num))
1101 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x7))
1104 if (get_user(val, &io->val64))
1107 __genwqe_writeq(cd, reg_offs, val);
1111 case GENWQE_READ_REG32: {
1112 io = (struct genwqe_reg_io __user *)arg;
1114 if (get_user(reg_offs, &io->num))
1117 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
1120 val = __genwqe_readl(cd, reg_offs);
1121 put_user(val, &io->val64);
1125 case GENWQE_WRITE_REG32: {
1126 io = (struct genwqe_reg_io __user *)arg;
1128 if (!capable(CAP_SYS_ADMIN))
1131 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1134 if (get_user(reg_offs, &io->num))
1137 if ((reg_offs >= cd->mmio_len) || (reg_offs & 0x3))
1140 if (get_user(val, &io->val64))
1143 __genwqe_writel(cd, reg_offs, val);
1147 /* Flash update/reading */
1148 case GENWQE_SLU_UPDATE: {
1149 struct genwqe_bitstream load;
1151 if (!genwqe_is_privileged(cd))
1154 if ((filp->f_flags & O_ACCMODE) == O_RDONLY)
1157 if (copy_from_user(&load, (void __user *)arg,
1161 rc = do_flash_update(cfile, &load);
1163 if (copy_to_user((void __user *)arg, &load, sizeof(load)))
1169 case GENWQE_SLU_READ: {
1170 struct genwqe_bitstream load;
1172 if (!genwqe_is_privileged(cd))
1175 if (genwqe_flash_readback_fails(cd))
1176 return -ENOSPC; /* known to fail for old versions */
1178 if (copy_from_user(&load, (void __user *)arg, sizeof(load)))
1181 rc = do_flash_read(cfile, &load);
1183 if (copy_to_user((void __user *)arg, &load, sizeof(load)))
1189 /* memory pinning and unpinning */
1190 case GENWQE_PIN_MEM: {
1191 struct genwqe_mem m;
1193 if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
1196 return genwqe_pin_mem(cfile, &m);
1199 case GENWQE_UNPIN_MEM: {
1200 struct genwqe_mem m;
1202 if (copy_from_user(&m, (void __user *)arg, sizeof(m)))
1205 return genwqe_unpin_mem(cfile, &m);
1208 /* launch an DDCB and wait for completion */
1209 case GENWQE_EXECUTE_DDCB:
1210 return do_execute_ddcb(cfile, arg, 0);
1212 case GENWQE_EXECUTE_RAW_DDCB: {
1214 if (!capable(CAP_SYS_ADMIN))
1217 return do_execute_ddcb(cfile, arg, 1);
1227 #if defined(CONFIG_COMPAT)
1229 * genwqe_compat_ioctl() - Compatibility ioctl
1231 * Called whenever a 32-bit process running under a 64-bit kernel
1232 * performs an ioctl on /dev/genwqe<n>_card.
1234 * @filp: file pointer.
1236 * @arg: user argument.
1237 * Return: zero on success or negative number on failure.
1239 static long genwqe_compat_ioctl(struct file *filp, unsigned int cmd,
1242 return genwqe_ioctl(filp, cmd, arg);
1244 #endif /* defined(CONFIG_COMPAT) */
1246 static const struct file_operations genwqe_fops = {
1247 .owner = THIS_MODULE,
1248 .open = genwqe_open,
1249 .fasync = genwqe_fasync,
1250 .mmap = genwqe_mmap,
1251 .unlocked_ioctl = genwqe_ioctl,
1252 #if defined(CONFIG_COMPAT)
1253 .compat_ioctl = genwqe_compat_ioctl,
1255 .release = genwqe_release,
1258 static int genwqe_device_initialized(struct genwqe_dev *cd)
1260 return cd->dev != NULL;
1264 * genwqe_device_create() - Create and configure genwqe char device
1265 * @cd: genwqe device descriptor
1267 * This function must be called before we create any more genwqe
1268 * character devices, because it is allocating the major and minor
1269 * number which are supposed to be used by the client drivers.
1271 int genwqe_device_create(struct genwqe_dev *cd)
1274 struct pci_dev *pci_dev = cd->pci_dev;
1277 * Here starts the individual setup per client. It must
1278 * initialize its own cdev data structure with its own fops.
1279 * The appropriate devnum needs to be created. The ranges must
1282 rc = alloc_chrdev_region(&cd->devnum_genwqe, 0,
1283 GENWQE_MAX_MINOR, GENWQE_DEVNAME);
1285 dev_err(&pci_dev->dev, "err: alloc_chrdev_region failed\n");
1289 cdev_init(&cd->cdev_genwqe, &genwqe_fops);
1290 cd->cdev_genwqe.owner = THIS_MODULE;
1292 rc = cdev_add(&cd->cdev_genwqe, cd->devnum_genwqe, 1);
1294 dev_err(&pci_dev->dev, "err: cdev_add failed\n");
1299 * Finally the device in /dev/... must be created. The rule is
1300 * to use card%d_clientname for each created device.
1302 cd->dev = device_create_with_groups(cd->class_genwqe,
1304 cd->devnum_genwqe, cd,
1305 genwqe_attribute_groups,
1306 GENWQE_DEVNAME "%u_card",
1308 if (IS_ERR(cd->dev)) {
1309 rc = PTR_ERR(cd->dev);
1313 rc = genwqe_init_debugfs(cd);
1320 device_destroy(cd->class_genwqe, cd->devnum_genwqe);
1322 cdev_del(&cd->cdev_genwqe);
1324 unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);
1330 static int genwqe_inform_and_stop_processes(struct genwqe_dev *cd)
1334 struct pci_dev *pci_dev = cd->pci_dev;
1336 if (!genwqe_open_files(cd))
1339 dev_warn(&pci_dev->dev, "[%s] send SIGIO and wait ...\n", __func__);
1341 rc = genwqe_kill_fasync(cd, SIGIO);
1343 /* give kill_timeout seconds to close file descriptors ... */
1344 for (i = 0; (i < genwqe_kill_timeout) &&
1345 genwqe_open_files(cd); i++) {
1346 dev_info(&pci_dev->dev, " %d sec ...", i);
1352 /* if no open files we can safely continue, else ... */
1353 if (!genwqe_open_files(cd))
1356 dev_warn(&pci_dev->dev,
1357 "[%s] send SIGKILL and wait ...\n", __func__);
1359 rc = genwqe_force_sig(cd, SIGKILL); /* force terminate */
1361 /* Give kill_timout more seconds to end processes */
1362 for (i = 0; (i < genwqe_kill_timeout) &&
1363 genwqe_open_files(cd); i++) {
1364 dev_warn(&pci_dev->dev, " %d sec ...", i);
1375 * genwqe_device_remove() - Remove genwqe's char device
1377 * This function must be called after the client devices are removed
1378 * because it will free the major/minor number range for the genwqe
1381 * This function must be robust enough to be called twice.
1383 int genwqe_device_remove(struct genwqe_dev *cd)
1386 struct pci_dev *pci_dev = cd->pci_dev;
1388 if (!genwqe_device_initialized(cd))
1391 genwqe_inform_and_stop_processes(cd);
1394 * We currently do wait until all filedescriptors are
1395 * closed. This leads to a problem when we abort the
1396 * application which will decrease this reference from
1397 * 1/unused to 0/illegal and not from 2/used 1/empty.
1399 rc = atomic_read(&cd->cdev_genwqe.kobj.kref.refcount);
1401 dev_err(&pci_dev->dev,
1402 "[%s] err: cdev_genwqe...refcount=%d\n", __func__, rc);
1403 panic("Fatal err: cannot free resources with pending references!");
1406 genqwe_exit_debugfs(cd);
1407 device_destroy(cd->class_genwqe, cd->devnum_genwqe);
1408 cdev_del(&cd->cdev_genwqe);
1409 unregister_chrdev_region(cd->devnum_genwqe, GENWQE_MAX_MINOR);