3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @dev: the device structure
32 * @offset: offset from which to read the data
34 * returns register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @dev: the device structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * returns ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @dev: the device structure
73 * returns ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @dev: the device structure
85 * returns H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @dev: the device structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_hw_config - configure hw dependent settings
110 static void mei_me_hw_config(struct mei_device *dev)
112 struct mei_me_hw *hw = to_me_hw(dev);
113 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
114 /* Doesn't change in runtime */
115 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
117 hw->pg_state = MEI_PG_OFF;
121 * mei_me_pg_state - translate internal pg state
122 * to the mei power gating state
125 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
127 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
129 struct mei_me_hw *hw = to_me_hw(dev);
135 * mei_clear_interrupts - clear and stop interrupts
137 * @dev: the device structure
139 static void mei_me_intr_clear(struct mei_device *dev)
141 struct mei_me_hw *hw = to_me_hw(dev);
142 u32 hcsr = mei_hcsr_read(hw);
144 if ((hcsr & H_IS) == H_IS)
145 mei_me_reg_write(hw, H_CSR, hcsr);
148 * mei_me_intr_enable - enables mei device interrupts
150 * @dev: the device structure
152 static void mei_me_intr_enable(struct mei_device *dev)
154 struct mei_me_hw *hw = to_me_hw(dev);
155 u32 hcsr = mei_hcsr_read(hw);
158 mei_hcsr_set(hw, hcsr);
162 * mei_disable_interrupts - disables mei device interrupts
164 * @dev: the device structure
166 static void mei_me_intr_disable(struct mei_device *dev)
168 struct mei_me_hw *hw = to_me_hw(dev);
169 u32 hcsr = mei_hcsr_read(hw);
172 mei_hcsr_set(hw, hcsr);
176 * mei_me_hw_reset_release - release device from the reset
178 * @dev: the device structure
180 static void mei_me_hw_reset_release(struct mei_device *dev)
182 struct mei_me_hw *hw = to_me_hw(dev);
183 u32 hcsr = mei_hcsr_read(hw);
187 mei_hcsr_set(hw, hcsr);
189 /* complete this write before we set host ready on another CPU */
193 * mei_me_hw_reset - resets fw via mei csr register.
195 * @dev: the device structure
196 * @intr_enable: if interrupt should be enabled after reset.
198 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
200 struct mei_me_hw *hw = to_me_hw(dev);
201 u32 hcsr = mei_hcsr_read(hw);
203 hcsr |= H_RST | H_IG | H_IS;
210 dev->recvd_hw_ready = false;
211 mei_me_reg_write(hw, H_CSR, hcsr);
214 * Host reads the H_CSR once to ensure that the
215 * posted write to H_CSR completes.
217 hcsr = mei_hcsr_read(hw);
219 if ((hcsr & H_RST) == 0)
220 dev_warn(&dev->pdev->dev, "H_RST is not set = 0x%08X", hcsr);
222 if ((hcsr & H_RDY) == H_RDY)
223 dev_warn(&dev->pdev->dev, "H_RDY is not cleared 0x%08X", hcsr);
225 if (intr_enable == false)
226 mei_me_hw_reset_release(dev);
232 * mei_me_host_set_ready - enable device
238 static void mei_me_host_set_ready(struct mei_device *dev)
240 struct mei_me_hw *hw = to_me_hw(dev);
242 hw->host_hw_state = mei_hcsr_read(hw);
243 hw->host_hw_state |= H_IE | H_IG | H_RDY;
244 mei_hcsr_set(hw, hw->host_hw_state);
247 * mei_me_host_is_ready - check whether the host has turned ready
252 static bool mei_me_host_is_ready(struct mei_device *dev)
254 struct mei_me_hw *hw = to_me_hw(dev);
256 hw->host_hw_state = mei_hcsr_read(hw);
257 return (hw->host_hw_state & H_RDY) == H_RDY;
261 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
266 static bool mei_me_hw_is_ready(struct mei_device *dev)
268 struct mei_me_hw *hw = to_me_hw(dev);
270 hw->me_hw_state = mei_me_mecsr_read(hw);
271 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
274 static int mei_me_hw_ready_wait(struct mei_device *dev)
276 mutex_unlock(&dev->device_lock);
277 wait_event_timeout(dev->wait_hw_ready,
279 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
280 mutex_lock(&dev->device_lock);
281 if (!dev->recvd_hw_ready) {
282 dev_err(&dev->pdev->dev, "wait hw ready failed\n");
286 dev->recvd_hw_ready = false;
290 static int mei_me_hw_start(struct mei_device *dev)
292 int ret = mei_me_hw_ready_wait(dev);
296 dev_dbg(&dev->pdev->dev, "hw is ready\n");
298 mei_me_host_set_ready(dev);
304 * mei_hbuf_filled_slots - gets number of device filled buffer slots
306 * @dev: the device structure
308 * returns number of filled slots
310 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
312 struct mei_me_hw *hw = to_me_hw(dev);
313 char read_ptr, write_ptr;
315 hw->host_hw_state = mei_hcsr_read(hw);
317 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
318 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
320 return (unsigned char) (write_ptr - read_ptr);
324 * mei_me_hbuf_is_empty - checks if host buffer is empty.
326 * @dev: the device structure
328 * returns true if empty, false - otherwise.
330 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
332 return mei_hbuf_filled_slots(dev) == 0;
336 * mei_me_hbuf_empty_slots - counts write empty slots.
338 * @dev: the device structure
340 * returns -EOVERFLOW if overflow, otherwise empty slots count
342 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
344 unsigned char filled_slots, empty_slots;
346 filled_slots = mei_hbuf_filled_slots(dev);
347 empty_slots = dev->hbuf_depth - filled_slots;
349 /* check for overflow */
350 if (filled_slots > dev->hbuf_depth)
356 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
358 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
363 * mei_me_write_message - writes a message to mei device.
365 * @dev: the device structure
366 * @header: mei HECI header of message
367 * @buf: message payload will be written
369 * This function returns -EIO if write has failed
371 static int mei_me_write_message(struct mei_device *dev,
372 struct mei_msg_hdr *header,
375 struct mei_me_hw *hw = to_me_hw(dev);
377 unsigned long length = header->length;
378 u32 *reg_buf = (u32 *)buf;
384 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
386 empty_slots = mei_hbuf_empty_slots(dev);
387 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
389 dw_cnt = mei_data2slots(length);
390 if (empty_slots < 0 || dw_cnt > empty_slots)
393 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
395 for (i = 0; i < length / 4; i++)
396 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
402 memcpy(®, &buf[length - rem], rem);
403 mei_me_reg_write(hw, H_CB_WW, reg);
406 hcsr = mei_hcsr_read(hw) | H_IG;
407 mei_hcsr_set(hw, hcsr);
408 if (!mei_me_hw_is_ready(dev))
415 * mei_me_count_full_read_slots - counts read full slots.
417 * @dev: the device structure
419 * returns -EOVERFLOW if overflow, otherwise filled slots count
421 static int mei_me_count_full_read_slots(struct mei_device *dev)
423 struct mei_me_hw *hw = to_me_hw(dev);
424 char read_ptr, write_ptr;
425 unsigned char buffer_depth, filled_slots;
427 hw->me_hw_state = mei_me_mecsr_read(hw);
428 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
429 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
430 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
431 filled_slots = (unsigned char) (write_ptr - read_ptr);
433 /* check for overflow */
434 if (filled_slots > buffer_depth)
437 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
438 return (int)filled_slots;
442 * mei_me_read_slots - reads a message from mei device.
444 * @dev: the device structure
445 * @buffer: message buffer will be written
446 * @buffer_length: message size will be read
448 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
449 unsigned long buffer_length)
451 struct mei_me_hw *hw = to_me_hw(dev);
452 u32 *reg_buf = (u32 *)buffer;
455 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
456 *reg_buf++ = mei_me_mecbrw_read(dev);
458 if (buffer_length > 0) {
459 u32 reg = mei_me_mecbrw_read(dev);
461 memcpy(reg_buf, ®, buffer_length);
464 hcsr = mei_hcsr_read(hw) | H_IG;
465 mei_hcsr_set(hw, hcsr);
470 * mei_me_pg_enter - write pg enter register
472 * @dev: the device structure
474 static void mei_me_pg_enter(struct mei_device *dev)
476 struct mei_me_hw *hw = to_me_hw(dev);
477 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
479 reg |= H_HPG_CSR_PGI;
480 mei_me_reg_write(hw, H_HPG_CSR, reg);
484 * mei_me_pg_exit - write pg exit register
486 * @dev: the device structure
488 static void mei_me_pg_exit(struct mei_device *dev)
490 struct mei_me_hw *hw = to_me_hw(dev);
491 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
493 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
495 reg |= H_HPG_CSR_PGIHEXR;
496 mei_me_reg_write(hw, H_HPG_CSR, reg);
500 * mei_me_pg_set_sync - perform pg entry procedure
502 * @dev: the device structure
504 * returns 0 on success an error code otherwise
506 int mei_me_pg_set_sync(struct mei_device *dev)
508 struct mei_me_hw *hw = to_me_hw(dev);
509 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
512 dev->pg_event = MEI_PG_EVENT_WAIT;
514 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
518 mutex_unlock(&dev->device_lock);
519 wait_event_timeout(dev->wait_pg,
520 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
521 mutex_lock(&dev->device_lock);
523 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
524 mei_me_pg_enter(dev);
530 dev->pg_event = MEI_PG_EVENT_IDLE;
531 hw->pg_state = MEI_PG_ON;
537 * mei_me_pg_unset_sync - perform pg exit procedure
539 * @dev: the device structure
541 * returns 0 on success an error code otherwise
543 int mei_me_pg_unset_sync(struct mei_device *dev)
545 struct mei_me_hw *hw = to_me_hw(dev);
546 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
549 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
552 dev->pg_event = MEI_PG_EVENT_WAIT;
556 mutex_unlock(&dev->device_lock);
557 wait_event_timeout(dev->wait_pg,
558 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
559 mutex_lock(&dev->device_lock);
562 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
563 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
567 dev->pg_event = MEI_PG_EVENT_IDLE;
568 hw->pg_state = MEI_PG_OFF;
574 * mei_me_pg_is_enabled - detect if PG is supported by HW
576 * @dev: the device structure
578 * returns: true is pg supported, false otherwise
580 static bool mei_me_pg_is_enabled(struct mei_device *dev)
582 struct mei_me_hw *hw = to_me_hw(dev);
583 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
585 if ((reg & ME_PGIC_HRA) == 0)
588 if (!dev->hbm_f_pg_supported)
594 dev_dbg(&dev->pdev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
595 !!(reg & ME_PGIC_HRA),
596 dev->version.major_version,
597 dev->version.minor_version,
598 HBM_MAJOR_VERSION_PGI,
599 HBM_MINOR_VERSION_PGI);
605 * mei_me_irq_quick_handler - The ISR of the MEI device
607 * @irq: The irq number
608 * @dev_id: pointer to the device structure
610 * returns irqreturn_t
613 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
615 struct mei_device *dev = (struct mei_device *) dev_id;
616 struct mei_me_hw *hw = to_me_hw(dev);
617 u32 csr_reg = mei_hcsr_read(hw);
619 if ((csr_reg & H_IS) != H_IS)
622 /* clear H_IS bit in H_CSR */
623 mei_me_reg_write(hw, H_CSR, csr_reg);
625 return IRQ_WAKE_THREAD;
629 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
632 * @irq: The irq number
633 * @dev_id: pointer to the device structure
635 * returns irqreturn_t
638 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
640 struct mei_device *dev = (struct mei_device *) dev_id;
641 struct mei_cl_cb complete_list;
645 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
646 /* initialize our complete list */
647 mutex_lock(&dev->device_lock);
648 mei_io_list_init(&complete_list);
650 /* Ack the interrupt here
651 * In case of MSI we don't go through the quick handler */
652 if (pci_dev_msi_enabled(dev->pdev))
653 mei_clear_interrupts(dev);
655 /* check if ME wants a reset */
656 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
657 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
658 schedule_work(&dev->reset_work);
662 /* check if we need to start the dev */
663 if (!mei_host_is_ready(dev)) {
664 if (mei_hw_is_ready(dev)) {
665 mei_me_hw_reset_release(dev);
666 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
668 dev->recvd_hw_ready = true;
669 wake_up(&dev->wait_hw_ready);
671 dev_dbg(&dev->pdev->dev, "Spurious Interrupt\n");
675 /* check slots available for reading */
676 slots = mei_count_full_read_slots(dev);
678 dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
679 rets = mei_irq_read_handler(dev, &complete_list, &slots);
680 /* There is a race between ME write and interrupt delivery:
681 * Not all data is always available immediately after the
682 * interrupt, so try to read again on the next interrupt.
684 if (rets == -ENODATA)
687 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
688 dev_err(&dev->pdev->dev, "mei_irq_read_handler ret = %d.\n",
690 schedule_work(&dev->reset_work);
695 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
698 * During PG handshake only allowed write is the replay to the
699 * PG exit message, so block calling write function
700 * if the pg state is not idle
702 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
703 rets = mei_irq_write_handler(dev, &complete_list);
704 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
707 mei_irq_compl_handler(dev, &complete_list);
710 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
711 mutex_unlock(&dev->device_lock);
715 static const struct mei_hw_ops mei_me_hw_ops = {
717 .pg_state = mei_me_pg_state,
719 .host_is_ready = mei_me_host_is_ready,
721 .hw_is_ready = mei_me_hw_is_ready,
722 .hw_reset = mei_me_hw_reset,
723 .hw_config = mei_me_hw_config,
724 .hw_start = mei_me_hw_start,
726 .pg_is_enabled = mei_me_pg_is_enabled,
728 .intr_clear = mei_me_intr_clear,
729 .intr_enable = mei_me_intr_enable,
730 .intr_disable = mei_me_intr_disable,
732 .hbuf_free_slots = mei_me_hbuf_empty_slots,
733 .hbuf_is_ready = mei_me_hbuf_is_empty,
734 .hbuf_max_len = mei_me_hbuf_max_len,
736 .write = mei_me_write_message,
738 .rdbuf_full_slots = mei_me_count_full_read_slots,
739 .read_hdr = mei_me_mecbrw_read,
740 .read = mei_me_read_slots
743 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
747 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
748 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
749 return (reg & 0x600) == 0x200;
752 #define MEI_CFG_FW_NM \
753 .quirk_probe = mei_me_fw_type_nm
755 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
758 /* Read ME FW Status check for SPS Firmware */
759 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
760 /* if bits [19:16] = 15, running SPS Firmware */
761 return (reg & 0xf0000) == 0xf0000;
764 #define MEI_CFG_FW_SPS \
765 .quirk_probe = mei_me_fw_type_sps
768 #define MEI_CFG_LEGACY_HFS \
771 #define MEI_CFG_ICH_HFS \
772 .fw_status.count = 1, \
773 .fw_status.status[0] = PCI_CFG_HFS_1
775 #define MEI_CFG_PCH_HFS \
776 .fw_status.count = 2, \
777 .fw_status.status[0] = PCI_CFG_HFS_1, \
778 .fw_status.status[1] = PCI_CFG_HFS_2
781 /* ICH Legacy devices */
782 const struct mei_cfg mei_me_legacy_cfg = {
787 const struct mei_cfg mei_me_ich_cfg = {
792 const struct mei_cfg mei_me_pch_cfg = {
797 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
798 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
803 /* PCH Lynx Point with quirk for SPS Firmware exclusion */
804 const struct mei_cfg mei_me_lpt_cfg = {
810 * mei_me_dev_init - allocates and initializes the mei device structure
812 * @pdev: The pci device structure
813 * @cfg: per device generation config
815 * returns The mei_device_device pointer on success, NULL on failure.
817 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
818 const struct mei_cfg *cfg)
820 struct mei_device *dev;
822 dev = kzalloc(sizeof(struct mei_device) +
823 sizeof(struct mei_me_hw), GFP_KERNEL);
827 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);