3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @hw: the me hardware structure
32 * @offset: offset from which to read the data
34 * Return: register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @hw: the me hardware structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * Return: ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @hw: the me hardware structure
73 * Return: ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @hw: the me hardware structure
85 * Return: H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @hw: the me hardware structure
97 * @hcsr: new register value
99 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
102 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_fw_status - read fw status register from pci config space
109 * @fw_status: fw status register values
111 * Return: 0 on success, error otherwise
113 static int mei_me_fw_status(struct mei_device *dev,
114 struct mei_fw_status *fw_status)
116 struct pci_dev *pdev = to_pci_dev(dev->dev);
117 struct mei_me_hw *hw = to_me_hw(dev);
118 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
125 fw_status->count = fw_src->count;
126 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
127 ret = pci_read_config_dword(pdev,
128 fw_src->status[i], &fw_status->status[i]);
137 * mei_me_hw_config - configure hw dependent settings
141 static void mei_me_hw_config(struct mei_device *dev)
143 struct mei_me_hw *hw = to_me_hw(dev);
144 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
145 /* Doesn't change in runtime */
146 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
148 hw->pg_state = MEI_PG_OFF;
152 * mei_me_pg_state - translate internal pg state
153 * to the mei power gating state
157 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
159 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
161 struct mei_me_hw *hw = to_me_hw(dev);
167 * mei_me_intr_clear - clear and stop interrupts
169 * @dev: the device structure
171 static void mei_me_intr_clear(struct mei_device *dev)
173 struct mei_me_hw *hw = to_me_hw(dev);
174 u32 hcsr = mei_hcsr_read(hw);
176 if ((hcsr & H_IS) == H_IS)
177 mei_me_reg_write(hw, H_CSR, hcsr);
180 * mei_me_intr_enable - enables mei device interrupts
182 * @dev: the device structure
184 static void mei_me_intr_enable(struct mei_device *dev)
186 struct mei_me_hw *hw = to_me_hw(dev);
187 u32 hcsr = mei_hcsr_read(hw);
190 mei_hcsr_set(hw, hcsr);
194 * mei_me_intr_disable - disables mei device interrupts
196 * @dev: the device structure
198 static void mei_me_intr_disable(struct mei_device *dev)
200 struct mei_me_hw *hw = to_me_hw(dev);
201 u32 hcsr = mei_hcsr_read(hw);
204 mei_hcsr_set(hw, hcsr);
208 * mei_me_hw_reset_release - release device from the reset
210 * @dev: the device structure
212 static void mei_me_hw_reset_release(struct mei_device *dev)
214 struct mei_me_hw *hw = to_me_hw(dev);
215 u32 hcsr = mei_hcsr_read(hw);
219 mei_hcsr_set(hw, hcsr);
221 /* complete this write before we set host ready on another CPU */
225 * mei_me_hw_reset - resets fw via mei csr register.
227 * @dev: the device structure
228 * @intr_enable: if interrupt should be enabled after reset.
232 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
234 struct mei_me_hw *hw = to_me_hw(dev);
235 u32 hcsr = mei_hcsr_read(hw);
237 hcsr |= H_RST | H_IG | H_IS;
244 dev->recvd_hw_ready = false;
245 mei_me_reg_write(hw, H_CSR, hcsr);
248 * Host reads the H_CSR once to ensure that the
249 * posted write to H_CSR completes.
251 hcsr = mei_hcsr_read(hw);
253 if ((hcsr & H_RST) == 0)
254 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
256 if ((hcsr & H_RDY) == H_RDY)
257 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
259 if (intr_enable == false)
260 mei_me_hw_reset_release(dev);
266 * mei_me_host_set_ready - enable device
270 static void mei_me_host_set_ready(struct mei_device *dev)
272 struct mei_me_hw *hw = to_me_hw(dev);
274 hw->host_hw_state = mei_hcsr_read(hw);
275 hw->host_hw_state |= H_IE | H_IG | H_RDY;
276 mei_hcsr_set(hw, hw->host_hw_state);
280 * mei_me_host_is_ready - check whether the host has turned ready
285 static bool mei_me_host_is_ready(struct mei_device *dev)
287 struct mei_me_hw *hw = to_me_hw(dev);
289 hw->host_hw_state = mei_hcsr_read(hw);
290 return (hw->host_hw_state & H_RDY) == H_RDY;
294 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
299 static bool mei_me_hw_is_ready(struct mei_device *dev)
301 struct mei_me_hw *hw = to_me_hw(dev);
303 hw->me_hw_state = mei_me_mecsr_read(hw);
304 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
308 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
309 * or timeout is reached
312 * Return: 0 on success, error otherwise
314 static int mei_me_hw_ready_wait(struct mei_device *dev)
316 mutex_unlock(&dev->device_lock);
317 wait_event_timeout(dev->wait_hw_ready,
319 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
320 mutex_lock(&dev->device_lock);
321 if (!dev->recvd_hw_ready) {
322 dev_err(dev->dev, "wait hw ready failed\n");
326 dev->recvd_hw_ready = false;
331 * mei_me_hw_start - hw start routine
334 * Return: 0 on success, error otherwise
336 static int mei_me_hw_start(struct mei_device *dev)
338 int ret = mei_me_hw_ready_wait(dev);
342 dev_dbg(dev->dev, "hw is ready\n");
344 mei_me_host_set_ready(dev);
350 * mei_hbuf_filled_slots - gets number of device filled buffer slots
352 * @dev: the device structure
354 * Return: number of filled slots
356 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
358 struct mei_me_hw *hw = to_me_hw(dev);
359 char read_ptr, write_ptr;
361 hw->host_hw_state = mei_hcsr_read(hw);
363 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
364 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
366 return (unsigned char) (write_ptr - read_ptr);
370 * mei_me_hbuf_is_empty - checks if host buffer is empty.
372 * @dev: the device structure
374 * Return: true if empty, false - otherwise.
376 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
378 return mei_hbuf_filled_slots(dev) == 0;
382 * mei_me_hbuf_empty_slots - counts write empty slots.
384 * @dev: the device structure
386 * Return: -EOVERFLOW if overflow, otherwise empty slots count
388 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
390 unsigned char filled_slots, empty_slots;
392 filled_slots = mei_hbuf_filled_slots(dev);
393 empty_slots = dev->hbuf_depth - filled_slots;
395 /* check for overflow */
396 if (filled_slots > dev->hbuf_depth)
403 * mei_me_hbuf_max_len - returns size of hw buffer.
405 * @dev: the device structure
407 * Return: size of hw buffer in bytes
409 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
411 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
416 * mei_me_write_message - writes a message to mei device.
418 * @dev: the device structure
419 * @header: mei HECI header of message
420 * @buf: message payload will be written
422 * Return: -EIO if write has failed
424 static int mei_me_write_message(struct mei_device *dev,
425 struct mei_msg_hdr *header,
428 struct mei_me_hw *hw = to_me_hw(dev);
430 unsigned long length = header->length;
431 u32 *reg_buf = (u32 *)buf;
437 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
439 empty_slots = mei_hbuf_empty_slots(dev);
440 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
442 dw_cnt = mei_data2slots(length);
443 if (empty_slots < 0 || dw_cnt > empty_slots)
446 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
448 for (i = 0; i < length / 4; i++)
449 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
455 memcpy(®, &buf[length - rem], rem);
456 mei_me_reg_write(hw, H_CB_WW, reg);
459 hcsr = mei_hcsr_read(hw) | H_IG;
460 mei_hcsr_set(hw, hcsr);
461 if (!mei_me_hw_is_ready(dev))
468 * mei_me_count_full_read_slots - counts read full slots.
470 * @dev: the device structure
472 * Return: -EOVERFLOW if overflow, otherwise filled slots count
474 static int mei_me_count_full_read_slots(struct mei_device *dev)
476 struct mei_me_hw *hw = to_me_hw(dev);
477 char read_ptr, write_ptr;
478 unsigned char buffer_depth, filled_slots;
480 hw->me_hw_state = mei_me_mecsr_read(hw);
481 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
482 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
483 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
484 filled_slots = (unsigned char) (write_ptr - read_ptr);
486 /* check for overflow */
487 if (filled_slots > buffer_depth)
490 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
491 return (int)filled_slots;
495 * mei_me_read_slots - reads a message from mei device.
497 * @dev: the device structure
498 * @buffer: message buffer will be written
499 * @buffer_length: message size will be read
503 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
504 unsigned long buffer_length)
506 struct mei_me_hw *hw = to_me_hw(dev);
507 u32 *reg_buf = (u32 *)buffer;
510 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
511 *reg_buf++ = mei_me_mecbrw_read(dev);
513 if (buffer_length > 0) {
514 u32 reg = mei_me_mecbrw_read(dev);
516 memcpy(reg_buf, ®, buffer_length);
519 hcsr = mei_hcsr_read(hw) | H_IG;
520 mei_hcsr_set(hw, hcsr);
525 * mei_me_pg_enter - write pg enter register
527 * @dev: the device structure
529 static void mei_me_pg_enter(struct mei_device *dev)
531 struct mei_me_hw *hw = to_me_hw(dev);
532 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
534 reg |= H_HPG_CSR_PGI;
535 mei_me_reg_write(hw, H_HPG_CSR, reg);
539 * mei_me_pg_exit - write pg exit register
541 * @dev: the device structure
543 static void mei_me_pg_exit(struct mei_device *dev)
545 struct mei_me_hw *hw = to_me_hw(dev);
546 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
548 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
550 reg |= H_HPG_CSR_PGIHEXR;
551 mei_me_reg_write(hw, H_HPG_CSR, reg);
555 * mei_me_pg_set_sync - perform pg entry procedure
557 * @dev: the device structure
559 * Return: 0 on success an error code otherwise
561 int mei_me_pg_set_sync(struct mei_device *dev)
563 struct mei_me_hw *hw = to_me_hw(dev);
564 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
567 dev->pg_event = MEI_PG_EVENT_WAIT;
569 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
573 mutex_unlock(&dev->device_lock);
574 wait_event_timeout(dev->wait_pg,
575 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
576 mutex_lock(&dev->device_lock);
578 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
579 mei_me_pg_enter(dev);
585 dev->pg_event = MEI_PG_EVENT_IDLE;
586 hw->pg_state = MEI_PG_ON;
592 * mei_me_pg_unset_sync - perform pg exit procedure
594 * @dev: the device structure
596 * Return: 0 on success an error code otherwise
598 int mei_me_pg_unset_sync(struct mei_device *dev)
600 struct mei_me_hw *hw = to_me_hw(dev);
601 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
604 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
607 dev->pg_event = MEI_PG_EVENT_WAIT;
611 mutex_unlock(&dev->device_lock);
612 wait_event_timeout(dev->wait_pg,
613 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
614 mutex_lock(&dev->device_lock);
617 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
618 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
622 dev->pg_event = MEI_PG_EVENT_IDLE;
623 hw->pg_state = MEI_PG_OFF;
629 * mei_me_pg_is_enabled - detect if PG is supported by HW
631 * @dev: the device structure
633 * Return: true is pg supported, false otherwise
635 static bool mei_me_pg_is_enabled(struct mei_device *dev)
637 struct mei_me_hw *hw = to_me_hw(dev);
638 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
640 if ((reg & ME_PGIC_HRA) == 0)
643 if (!dev->hbm_f_pg_supported)
649 dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
650 !!(reg & ME_PGIC_HRA),
651 dev->version.major_version,
652 dev->version.minor_version,
653 HBM_MAJOR_VERSION_PGI,
654 HBM_MINOR_VERSION_PGI);
660 * mei_me_irq_quick_handler - The ISR of the MEI device
662 * @irq: The irq number
663 * @dev_id: pointer to the device structure
665 * Return: irqreturn_t
668 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
670 struct mei_device *dev = (struct mei_device *) dev_id;
671 struct mei_me_hw *hw = to_me_hw(dev);
672 u32 csr_reg = mei_hcsr_read(hw);
674 if ((csr_reg & H_IS) != H_IS)
677 /* clear H_IS bit in H_CSR */
678 mei_me_reg_write(hw, H_CSR, csr_reg);
680 return IRQ_WAKE_THREAD;
684 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
687 * @irq: The irq number
688 * @dev_id: pointer to the device structure
690 * Return: irqreturn_t
693 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
695 struct mei_device *dev = (struct mei_device *) dev_id;
696 struct mei_cl_cb complete_list;
700 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
701 /* initialize our complete list */
702 mutex_lock(&dev->device_lock);
703 mei_io_list_init(&complete_list);
705 /* Ack the interrupt here
706 * In case of MSI we don't go through the quick handler */
707 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
708 mei_clear_interrupts(dev);
710 /* check if ME wants a reset */
711 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
712 dev_warn(dev->dev, "FW not ready: resetting.\n");
713 schedule_work(&dev->reset_work);
717 /* check if we need to start the dev */
718 if (!mei_host_is_ready(dev)) {
719 if (mei_hw_is_ready(dev)) {
720 mei_me_hw_reset_release(dev);
721 dev_dbg(dev->dev, "we need to start the dev.\n");
723 dev->recvd_hw_ready = true;
724 wake_up(&dev->wait_hw_ready);
726 dev_dbg(dev->dev, "Spurious Interrupt\n");
730 /* check slots available for reading */
731 slots = mei_count_full_read_slots(dev);
733 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
734 rets = mei_irq_read_handler(dev, &complete_list, &slots);
735 /* There is a race between ME write and interrupt delivery:
736 * Not all data is always available immediately after the
737 * interrupt, so try to read again on the next interrupt.
739 if (rets == -ENODATA)
742 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
743 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
745 schedule_work(&dev->reset_work);
750 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
753 * During PG handshake only allowed write is the replay to the
754 * PG exit message, so block calling write function
755 * if the pg state is not idle
757 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
758 rets = mei_irq_write_handler(dev, &complete_list);
759 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
762 mei_irq_compl_handler(dev, &complete_list);
765 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
766 mutex_unlock(&dev->device_lock);
770 static const struct mei_hw_ops mei_me_hw_ops = {
772 .fw_status = mei_me_fw_status,
773 .pg_state = mei_me_pg_state,
775 .host_is_ready = mei_me_host_is_ready,
777 .hw_is_ready = mei_me_hw_is_ready,
778 .hw_reset = mei_me_hw_reset,
779 .hw_config = mei_me_hw_config,
780 .hw_start = mei_me_hw_start,
782 .pg_is_enabled = mei_me_pg_is_enabled,
784 .intr_clear = mei_me_intr_clear,
785 .intr_enable = mei_me_intr_enable,
786 .intr_disable = mei_me_intr_disable,
788 .hbuf_free_slots = mei_me_hbuf_empty_slots,
789 .hbuf_is_ready = mei_me_hbuf_is_empty,
790 .hbuf_max_len = mei_me_hbuf_max_len,
792 .write = mei_me_write_message,
794 .rdbuf_full_slots = mei_me_count_full_read_slots,
795 .read_hdr = mei_me_mecbrw_read,
796 .read = mei_me_read_slots
799 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
803 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
804 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
805 return (reg & 0x600) == 0x200;
808 #define MEI_CFG_FW_NM \
809 .quirk_probe = mei_me_fw_type_nm
811 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
814 /* Read ME FW Status check for SPS Firmware */
815 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
816 /* if bits [19:16] = 15, running SPS Firmware */
817 return (reg & 0xf0000) == 0xf0000;
820 #define MEI_CFG_FW_SPS \
821 .quirk_probe = mei_me_fw_type_sps
824 #define MEI_CFG_LEGACY_HFS \
827 #define MEI_CFG_ICH_HFS \
828 .fw_status.count = 1, \
829 .fw_status.status[0] = PCI_CFG_HFS_1
831 #define MEI_CFG_PCH_HFS \
832 .fw_status.count = 2, \
833 .fw_status.status[0] = PCI_CFG_HFS_1, \
834 .fw_status.status[1] = PCI_CFG_HFS_2
837 /* ICH Legacy devices */
838 const struct mei_cfg mei_me_legacy_cfg = {
843 const struct mei_cfg mei_me_ich_cfg = {
848 const struct mei_cfg mei_me_pch_cfg = {
853 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
854 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
859 /* PCH Lynx Point with quirk for SPS Firmware exclusion */
860 const struct mei_cfg mei_me_lpt_cfg = {
866 * mei_me_dev_init - allocates and initializes the mei device structure
868 * @pdev: The pci device structure
869 * @cfg: per device generation config
871 * Return: The mei_device_device pointer on success, NULL on failure.
873 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
874 const struct mei_cfg *cfg)
876 struct mei_device *dev;
877 struct mei_me_hw *hw;
879 dev = kzalloc(sizeof(struct mei_device) +
880 sizeof(struct mei_me_hw), GFP_KERNEL);
885 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);