3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @hw: the me hardware structure
32 * @offset: offset from which to read the data
34 * Return: register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @hw: the me hardware structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * Return: ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @hw: the me hardware structure
73 * Return: ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @hw: the me hardware structure
85 * Return: H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @hw: the me hardware structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_me_reg_write(hw, H_CSR, hcsr);
105 * mei_me_fw_status - read fw status register from pci config space
108 * @fw_status: fw status register values
110 static int mei_me_fw_status(struct mei_device *dev,
111 struct mei_fw_status *fw_status)
113 struct pci_dev *pdev = to_pci_dev(dev->dev);
114 struct mei_me_hw *hw = to_me_hw(dev);
115 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
122 fw_status->count = fw_src->count;
123 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
124 ret = pci_read_config_dword(pdev,
125 fw_src->status[i], &fw_status->status[i]);
134 * mei_me_hw_config - configure hw dependent settings
138 static void mei_me_hw_config(struct mei_device *dev)
140 struct mei_me_hw *hw = to_me_hw(dev);
141 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
142 /* Doesn't change in runtime */
143 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
145 hw->pg_state = MEI_PG_OFF;
149 * mei_me_pg_state - translate internal pg state
150 * to the mei power gating state
153 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
155 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
157 struct mei_me_hw *hw = to_me_hw(dev);
163 * mei_clear_interrupts - clear and stop interrupts
165 * @dev: the device structure
167 static void mei_me_intr_clear(struct mei_device *dev)
169 struct mei_me_hw *hw = to_me_hw(dev);
170 u32 hcsr = mei_hcsr_read(hw);
172 if ((hcsr & H_IS) == H_IS)
173 mei_me_reg_write(hw, H_CSR, hcsr);
176 * mei_me_intr_enable - enables mei device interrupts
178 * @dev: the device structure
180 static void mei_me_intr_enable(struct mei_device *dev)
182 struct mei_me_hw *hw = to_me_hw(dev);
183 u32 hcsr = mei_hcsr_read(hw);
186 mei_hcsr_set(hw, hcsr);
190 * mei_disable_interrupts - disables mei device interrupts
192 * @dev: the device structure
194 static void mei_me_intr_disable(struct mei_device *dev)
196 struct mei_me_hw *hw = to_me_hw(dev);
197 u32 hcsr = mei_hcsr_read(hw);
200 mei_hcsr_set(hw, hcsr);
204 * mei_me_hw_reset_release - release device from the reset
206 * @dev: the device structure
208 static void mei_me_hw_reset_release(struct mei_device *dev)
210 struct mei_me_hw *hw = to_me_hw(dev);
211 u32 hcsr = mei_hcsr_read(hw);
215 mei_hcsr_set(hw, hcsr);
217 /* complete this write before we set host ready on another CPU */
221 * mei_me_hw_reset - resets fw via mei csr register.
223 * @dev: the device structure
224 * @intr_enable: if interrupt should be enabled after reset.
226 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
228 struct mei_me_hw *hw = to_me_hw(dev);
229 u32 hcsr = mei_hcsr_read(hw);
231 hcsr |= H_RST | H_IG | H_IS;
238 dev->recvd_hw_ready = false;
239 mei_me_reg_write(hw, H_CSR, hcsr);
242 * Host reads the H_CSR once to ensure that the
243 * posted write to H_CSR completes.
245 hcsr = mei_hcsr_read(hw);
247 if ((hcsr & H_RST) == 0)
248 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
250 if ((hcsr & H_RDY) == H_RDY)
251 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
253 if (intr_enable == false)
254 mei_me_hw_reset_release(dev);
260 * mei_me_host_set_ready - enable device
266 static void mei_me_host_set_ready(struct mei_device *dev)
268 struct mei_me_hw *hw = to_me_hw(dev);
270 hw->host_hw_state = mei_hcsr_read(hw);
271 hw->host_hw_state |= H_IE | H_IG | H_RDY;
272 mei_hcsr_set(hw, hw->host_hw_state);
275 * mei_me_host_is_ready - check whether the host has turned ready
280 static bool mei_me_host_is_ready(struct mei_device *dev)
282 struct mei_me_hw *hw = to_me_hw(dev);
284 hw->host_hw_state = mei_hcsr_read(hw);
285 return (hw->host_hw_state & H_RDY) == H_RDY;
289 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
294 static bool mei_me_hw_is_ready(struct mei_device *dev)
296 struct mei_me_hw *hw = to_me_hw(dev);
298 hw->me_hw_state = mei_me_mecsr_read(hw);
299 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
302 static int mei_me_hw_ready_wait(struct mei_device *dev)
304 mutex_unlock(&dev->device_lock);
305 wait_event_timeout(dev->wait_hw_ready,
307 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
308 mutex_lock(&dev->device_lock);
309 if (!dev->recvd_hw_ready) {
310 dev_err(dev->dev, "wait hw ready failed\n");
314 dev->recvd_hw_ready = false;
318 static int mei_me_hw_start(struct mei_device *dev)
320 int ret = mei_me_hw_ready_wait(dev);
324 dev_dbg(dev->dev, "hw is ready\n");
326 mei_me_host_set_ready(dev);
332 * mei_hbuf_filled_slots - gets number of device filled buffer slots
334 * @dev: the device structure
336 * Return: number of filled slots
338 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
340 struct mei_me_hw *hw = to_me_hw(dev);
341 char read_ptr, write_ptr;
343 hw->host_hw_state = mei_hcsr_read(hw);
345 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
346 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
348 return (unsigned char) (write_ptr - read_ptr);
352 * mei_me_hbuf_is_empty - checks if host buffer is empty.
354 * @dev: the device structure
356 * Return: true if empty, false - otherwise.
358 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
360 return mei_hbuf_filled_slots(dev) == 0;
364 * mei_me_hbuf_empty_slots - counts write empty slots.
366 * @dev: the device structure
368 * Return: -EOVERFLOW if overflow, otherwise empty slots count
370 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
372 unsigned char filled_slots, empty_slots;
374 filled_slots = mei_hbuf_filled_slots(dev);
375 empty_slots = dev->hbuf_depth - filled_slots;
377 /* check for overflow */
378 if (filled_slots > dev->hbuf_depth)
384 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
386 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
391 * mei_me_write_message - writes a message to mei device.
393 * @dev: the device structure
394 * @header: mei HECI header of message
395 * @buf: message payload will be written
397 * Return: -EIO if write has failed
399 static int mei_me_write_message(struct mei_device *dev,
400 struct mei_msg_hdr *header,
403 struct mei_me_hw *hw = to_me_hw(dev);
405 unsigned long length = header->length;
406 u32 *reg_buf = (u32 *)buf;
412 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
414 empty_slots = mei_hbuf_empty_slots(dev);
415 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
417 dw_cnt = mei_data2slots(length);
418 if (empty_slots < 0 || dw_cnt > empty_slots)
421 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
423 for (i = 0; i < length / 4; i++)
424 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
430 memcpy(®, &buf[length - rem], rem);
431 mei_me_reg_write(hw, H_CB_WW, reg);
434 hcsr = mei_hcsr_read(hw) | H_IG;
435 mei_hcsr_set(hw, hcsr);
436 if (!mei_me_hw_is_ready(dev))
443 * mei_me_count_full_read_slots - counts read full slots.
445 * @dev: the device structure
447 * Return: -EOVERFLOW if overflow, otherwise filled slots count
449 static int mei_me_count_full_read_slots(struct mei_device *dev)
451 struct mei_me_hw *hw = to_me_hw(dev);
452 char read_ptr, write_ptr;
453 unsigned char buffer_depth, filled_slots;
455 hw->me_hw_state = mei_me_mecsr_read(hw);
456 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
457 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
458 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
459 filled_slots = (unsigned char) (write_ptr - read_ptr);
461 /* check for overflow */
462 if (filled_slots > buffer_depth)
465 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
466 return (int)filled_slots;
470 * mei_me_read_slots - reads a message from mei device.
472 * @dev: the device structure
473 * @buffer: message buffer will be written
474 * @buffer_length: message size will be read
476 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
477 unsigned long buffer_length)
479 struct mei_me_hw *hw = to_me_hw(dev);
480 u32 *reg_buf = (u32 *)buffer;
483 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
484 *reg_buf++ = mei_me_mecbrw_read(dev);
486 if (buffer_length > 0) {
487 u32 reg = mei_me_mecbrw_read(dev);
489 memcpy(reg_buf, ®, buffer_length);
492 hcsr = mei_hcsr_read(hw) | H_IG;
493 mei_hcsr_set(hw, hcsr);
498 * mei_me_pg_enter - write pg enter register
500 * @dev: the device structure
502 static void mei_me_pg_enter(struct mei_device *dev)
504 struct mei_me_hw *hw = to_me_hw(dev);
505 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
507 reg |= H_HPG_CSR_PGI;
508 mei_me_reg_write(hw, H_HPG_CSR, reg);
512 * mei_me_pg_exit - write pg exit register
514 * @dev: the device structure
516 static void mei_me_pg_exit(struct mei_device *dev)
518 struct mei_me_hw *hw = to_me_hw(dev);
519 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
521 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
523 reg |= H_HPG_CSR_PGIHEXR;
524 mei_me_reg_write(hw, H_HPG_CSR, reg);
528 * mei_me_pg_set_sync - perform pg entry procedure
530 * @dev: the device structure
532 * Return: 0 on success an error code otherwise
534 int mei_me_pg_set_sync(struct mei_device *dev)
536 struct mei_me_hw *hw = to_me_hw(dev);
537 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
540 dev->pg_event = MEI_PG_EVENT_WAIT;
542 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
546 mutex_unlock(&dev->device_lock);
547 wait_event_timeout(dev->wait_pg,
548 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
549 mutex_lock(&dev->device_lock);
551 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
552 mei_me_pg_enter(dev);
558 dev->pg_event = MEI_PG_EVENT_IDLE;
559 hw->pg_state = MEI_PG_ON;
565 * mei_me_pg_unset_sync - perform pg exit procedure
567 * @dev: the device structure
569 * Return: 0 on success an error code otherwise
571 int mei_me_pg_unset_sync(struct mei_device *dev)
573 struct mei_me_hw *hw = to_me_hw(dev);
574 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
577 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
580 dev->pg_event = MEI_PG_EVENT_WAIT;
584 mutex_unlock(&dev->device_lock);
585 wait_event_timeout(dev->wait_pg,
586 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
587 mutex_lock(&dev->device_lock);
590 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
591 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
595 dev->pg_event = MEI_PG_EVENT_IDLE;
596 hw->pg_state = MEI_PG_OFF;
602 * mei_me_pg_is_enabled - detect if PG is supported by HW
604 * @dev: the device structure
606 * Return: true is pg supported, false otherwise
608 static bool mei_me_pg_is_enabled(struct mei_device *dev)
610 struct mei_me_hw *hw = to_me_hw(dev);
611 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
613 if ((reg & ME_PGIC_HRA) == 0)
616 if (!dev->hbm_f_pg_supported)
622 dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
623 !!(reg & ME_PGIC_HRA),
624 dev->version.major_version,
625 dev->version.minor_version,
626 HBM_MAJOR_VERSION_PGI,
627 HBM_MINOR_VERSION_PGI);
633 * mei_me_irq_quick_handler - The ISR of the MEI device
635 * @irq: The irq number
636 * @dev_id: pointer to the device structure
638 * Return: irqreturn_t
641 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
643 struct mei_device *dev = (struct mei_device *) dev_id;
644 struct mei_me_hw *hw = to_me_hw(dev);
645 u32 csr_reg = mei_hcsr_read(hw);
647 if ((csr_reg & H_IS) != H_IS)
650 /* clear H_IS bit in H_CSR */
651 mei_me_reg_write(hw, H_CSR, csr_reg);
653 return IRQ_WAKE_THREAD;
657 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
660 * @irq: The irq number
661 * @dev_id: pointer to the device structure
663 * Return: irqreturn_t
666 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
668 struct mei_device *dev = (struct mei_device *) dev_id;
669 struct mei_cl_cb complete_list;
673 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
674 /* initialize our complete list */
675 mutex_lock(&dev->device_lock);
676 mei_io_list_init(&complete_list);
678 /* Ack the interrupt here
679 * In case of MSI we don't go through the quick handler */
680 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
681 mei_clear_interrupts(dev);
683 /* check if ME wants a reset */
684 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
685 dev_warn(dev->dev, "FW not ready: resetting.\n");
686 schedule_work(&dev->reset_work);
690 /* check if we need to start the dev */
691 if (!mei_host_is_ready(dev)) {
692 if (mei_hw_is_ready(dev)) {
693 mei_me_hw_reset_release(dev);
694 dev_dbg(dev->dev, "we need to start the dev.\n");
696 dev->recvd_hw_ready = true;
697 wake_up(&dev->wait_hw_ready);
699 dev_dbg(dev->dev, "Spurious Interrupt\n");
703 /* check slots available for reading */
704 slots = mei_count_full_read_slots(dev);
706 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
707 rets = mei_irq_read_handler(dev, &complete_list, &slots);
708 /* There is a race between ME write and interrupt delivery:
709 * Not all data is always available immediately after the
710 * interrupt, so try to read again on the next interrupt.
712 if (rets == -ENODATA)
715 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
716 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
718 schedule_work(&dev->reset_work);
723 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
726 * During PG handshake only allowed write is the replay to the
727 * PG exit message, so block calling write function
728 * if the pg state is not idle
730 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
731 rets = mei_irq_write_handler(dev, &complete_list);
732 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
735 mei_irq_compl_handler(dev, &complete_list);
738 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
739 mutex_unlock(&dev->device_lock);
743 static const struct mei_hw_ops mei_me_hw_ops = {
745 .fw_status = mei_me_fw_status,
746 .pg_state = mei_me_pg_state,
748 .host_is_ready = mei_me_host_is_ready,
750 .hw_is_ready = mei_me_hw_is_ready,
751 .hw_reset = mei_me_hw_reset,
752 .hw_config = mei_me_hw_config,
753 .hw_start = mei_me_hw_start,
755 .pg_is_enabled = mei_me_pg_is_enabled,
757 .intr_clear = mei_me_intr_clear,
758 .intr_enable = mei_me_intr_enable,
759 .intr_disable = mei_me_intr_disable,
761 .hbuf_free_slots = mei_me_hbuf_empty_slots,
762 .hbuf_is_ready = mei_me_hbuf_is_empty,
763 .hbuf_max_len = mei_me_hbuf_max_len,
765 .write = mei_me_write_message,
767 .rdbuf_full_slots = mei_me_count_full_read_slots,
768 .read_hdr = mei_me_mecbrw_read,
769 .read = mei_me_read_slots
772 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
776 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
777 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
778 return (reg & 0x600) == 0x200;
781 #define MEI_CFG_FW_NM \
782 .quirk_probe = mei_me_fw_type_nm
784 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
787 /* Read ME FW Status check for SPS Firmware */
788 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
789 /* if bits [19:16] = 15, running SPS Firmware */
790 return (reg & 0xf0000) == 0xf0000;
793 #define MEI_CFG_FW_SPS \
794 .quirk_probe = mei_me_fw_type_sps
797 #define MEI_CFG_LEGACY_HFS \
800 #define MEI_CFG_ICH_HFS \
801 .fw_status.count = 1, \
802 .fw_status.status[0] = PCI_CFG_HFS_1
804 #define MEI_CFG_PCH_HFS \
805 .fw_status.count = 2, \
806 .fw_status.status[0] = PCI_CFG_HFS_1, \
807 .fw_status.status[1] = PCI_CFG_HFS_2
810 /* ICH Legacy devices */
811 const struct mei_cfg mei_me_legacy_cfg = {
816 const struct mei_cfg mei_me_ich_cfg = {
821 const struct mei_cfg mei_me_pch_cfg = {
826 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
827 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
832 /* PCH Lynx Point with quirk for SPS Firmware exclusion */
833 const struct mei_cfg mei_me_lpt_cfg = {
839 * mei_me_dev_init - allocates and initializes the mei device structure
841 * @pdev: The pci device structure
842 * @cfg: per device generation config
844 * Return: The mei_device_device pointer on success, NULL on failure.
846 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
847 const struct mei_cfg *cfg)
849 struct mei_device *dev;
850 struct mei_me_hw *hw;
852 dev = kzalloc(sizeof(struct mei_device) +
853 sizeof(struct mei_me_hw), GFP_KERNEL);
858 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);