3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @dev: the device structure
32 * @offset: offset from which to read the data
34 * returns register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @dev: the device structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * returns ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @dev: the device structure
73 * returns ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @dev: the device structure
85 * returns H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @dev: the device structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_hw_config - configure hw dependent settings
110 static void mei_me_hw_config(struct mei_device *dev)
112 struct mei_me_hw *hw = to_me_hw(dev);
113 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
114 /* Doesn't change in runtime */
115 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
117 hw->pg_state = MEI_PG_OFF;
121 * mei_me_pg_state - translate internal pg state
122 * to the mei power gating state
125 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
127 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
129 struct mei_me_hw *hw = to_me_hw(dev);
134 * mei_clear_interrupts - clear and stop interrupts
136 * @dev: the device structure
138 static void mei_me_intr_clear(struct mei_device *dev)
140 struct mei_me_hw *hw = to_me_hw(dev);
141 u32 hcsr = mei_hcsr_read(hw);
142 if ((hcsr & H_IS) == H_IS)
143 mei_me_reg_write(hw, H_CSR, hcsr);
146 * mei_me_intr_enable - enables mei device interrupts
148 * @dev: the device structure
150 static void mei_me_intr_enable(struct mei_device *dev)
152 struct mei_me_hw *hw = to_me_hw(dev);
153 u32 hcsr = mei_hcsr_read(hw);
155 mei_hcsr_set(hw, hcsr);
159 * mei_disable_interrupts - disables mei device interrupts
161 * @dev: the device structure
163 static void mei_me_intr_disable(struct mei_device *dev)
165 struct mei_me_hw *hw = to_me_hw(dev);
166 u32 hcsr = mei_hcsr_read(hw);
168 mei_hcsr_set(hw, hcsr);
172 * mei_me_hw_reset_release - release device from the reset
174 * @dev: the device structure
176 static void mei_me_hw_reset_release(struct mei_device *dev)
178 struct mei_me_hw *hw = to_me_hw(dev);
179 u32 hcsr = mei_hcsr_read(hw);
183 mei_hcsr_set(hw, hcsr);
185 /* complete this write before we set host ready on another CPU */
189 * mei_me_hw_reset - resets fw via mei csr register.
191 * @dev: the device structure
192 * @intr_enable: if interrupt should be enabled after reset.
194 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
196 struct mei_me_hw *hw = to_me_hw(dev);
197 u32 hcsr = mei_hcsr_read(hw);
199 hcsr |= H_RST | H_IG | H_IS;
206 dev->recvd_hw_ready = false;
207 mei_me_reg_write(hw, H_CSR, hcsr);
210 * Host reads the H_CSR once to ensure that the
211 * posted write to H_CSR completes.
213 hcsr = mei_hcsr_read(hw);
215 if ((hcsr & H_RST) == 0)
216 dev_warn(&dev->pdev->dev, "H_RST is not set = 0x%08X", hcsr);
218 if ((hcsr & H_RDY) == H_RDY)
219 dev_warn(&dev->pdev->dev, "H_RDY is not cleared 0x%08X", hcsr);
221 if (intr_enable == false)
222 mei_me_hw_reset_release(dev);
228 * mei_me_host_set_ready - enable device
234 static void mei_me_host_set_ready(struct mei_device *dev)
236 struct mei_me_hw *hw = to_me_hw(dev);
237 hw->host_hw_state = mei_hcsr_read(hw);
238 hw->host_hw_state |= H_IE | H_IG | H_RDY;
239 mei_hcsr_set(hw, hw->host_hw_state);
242 * mei_me_host_is_ready - check whether the host has turned ready
247 static bool mei_me_host_is_ready(struct mei_device *dev)
249 struct mei_me_hw *hw = to_me_hw(dev);
250 hw->host_hw_state = mei_hcsr_read(hw);
251 return (hw->host_hw_state & H_RDY) == H_RDY;
255 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
260 static bool mei_me_hw_is_ready(struct mei_device *dev)
262 struct mei_me_hw *hw = to_me_hw(dev);
263 hw->me_hw_state = mei_me_mecsr_read(hw);
264 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
267 static int mei_me_hw_ready_wait(struct mei_device *dev)
271 mutex_unlock(&dev->device_lock);
272 err = wait_event_interruptible_timeout(dev->wait_hw_ready,
274 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
275 mutex_lock(&dev->device_lock);
276 if (!err && !dev->recvd_hw_ready) {
279 dev_err(&dev->pdev->dev,
280 "wait hw ready failed. status = %d\n", err);
284 dev->recvd_hw_ready = false;
288 static int mei_me_hw_start(struct mei_device *dev)
290 int ret = mei_me_hw_ready_wait(dev);
293 dev_dbg(&dev->pdev->dev, "hw is ready\n");
295 mei_me_host_set_ready(dev);
301 * mei_hbuf_filled_slots - gets number of device filled buffer slots
303 * @dev: the device structure
305 * returns number of filled slots
307 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
309 struct mei_me_hw *hw = to_me_hw(dev);
310 char read_ptr, write_ptr;
312 hw->host_hw_state = mei_hcsr_read(hw);
314 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
315 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
317 return (unsigned char) (write_ptr - read_ptr);
321 * mei_me_hbuf_is_empty - checks if host buffer is empty.
323 * @dev: the device structure
325 * returns true if empty, false - otherwise.
327 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
329 return mei_hbuf_filled_slots(dev) == 0;
333 * mei_me_hbuf_empty_slots - counts write empty slots.
335 * @dev: the device structure
337 * returns -EOVERFLOW if overflow, otherwise empty slots count
339 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
341 unsigned char filled_slots, empty_slots;
343 filled_slots = mei_hbuf_filled_slots(dev);
344 empty_slots = dev->hbuf_depth - filled_slots;
346 /* check for overflow */
347 if (filled_slots > dev->hbuf_depth)
353 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
355 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
360 * mei_me_write_message - writes a message to mei device.
362 * @dev: the device structure
363 * @header: mei HECI header of message
364 * @buf: message payload will be written
366 * This function returns -EIO if write has failed
368 static int mei_me_write_message(struct mei_device *dev,
369 struct mei_msg_hdr *header,
372 struct mei_me_hw *hw = to_me_hw(dev);
374 unsigned long length = header->length;
375 u32 *reg_buf = (u32 *)buf;
381 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
383 empty_slots = mei_hbuf_empty_slots(dev);
384 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
386 dw_cnt = mei_data2slots(length);
387 if (empty_slots < 0 || dw_cnt > empty_slots)
390 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
392 for (i = 0; i < length / 4; i++)
393 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
398 memcpy(®, &buf[length - rem], rem);
399 mei_me_reg_write(hw, H_CB_WW, reg);
402 hcsr = mei_hcsr_read(hw) | H_IG;
403 mei_hcsr_set(hw, hcsr);
404 if (!mei_me_hw_is_ready(dev))
411 * mei_me_count_full_read_slots - counts read full slots.
413 * @dev: the device structure
415 * returns -EOVERFLOW if overflow, otherwise filled slots count
417 static int mei_me_count_full_read_slots(struct mei_device *dev)
419 struct mei_me_hw *hw = to_me_hw(dev);
420 char read_ptr, write_ptr;
421 unsigned char buffer_depth, filled_slots;
423 hw->me_hw_state = mei_me_mecsr_read(hw);
424 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
425 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
426 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
427 filled_slots = (unsigned char) (write_ptr - read_ptr);
429 /* check for overflow */
430 if (filled_slots > buffer_depth)
433 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
434 return (int)filled_slots;
438 * mei_me_read_slots - reads a message from mei device.
440 * @dev: the device structure
441 * @buffer: message buffer will be written
442 * @buffer_length: message size will be read
444 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
445 unsigned long buffer_length)
447 struct mei_me_hw *hw = to_me_hw(dev);
448 u32 *reg_buf = (u32 *)buffer;
451 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
452 *reg_buf++ = mei_me_mecbrw_read(dev);
454 if (buffer_length > 0) {
455 u32 reg = mei_me_mecbrw_read(dev);
456 memcpy(reg_buf, ®, buffer_length);
459 hcsr = mei_hcsr_read(hw) | H_IG;
460 mei_hcsr_set(hw, hcsr);
465 * mei_me_pg_enter - write pg enter register to mei device.
467 * @dev: the device structure
469 static void mei_me_pg_enter(struct mei_device *dev)
471 struct mei_me_hw *hw = to_me_hw(dev);
472 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
473 reg |= H_HPG_CSR_PGI;
474 mei_me_reg_write(hw, H_HPG_CSR, reg);
478 * mei_me_pg_enter - write pg enter register to mei device.
480 * @dev: the device structure
482 static void mei_me_pg_exit(struct mei_device *dev)
484 struct mei_me_hw *hw = to_me_hw(dev);
485 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
487 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
489 reg |= H_HPG_CSR_PGIHEXR;
490 mei_me_reg_write(hw, H_HPG_CSR, reg);
494 * mei_me_pg_set_sync - perform pg entry procedure
496 * @dev: the device structure
498 * returns 0 on success an error code otherwise
500 int mei_me_pg_set_sync(struct mei_device *dev)
502 struct mei_me_hw *hw = to_me_hw(dev);
503 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
506 dev->pg_event = MEI_PG_EVENT_WAIT;
508 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
512 mutex_unlock(&dev->device_lock);
513 wait_event_timeout(dev->wait_pg,
514 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
515 mutex_lock(&dev->device_lock);
517 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
518 mei_me_pg_enter(dev);
524 dev->pg_event = MEI_PG_EVENT_IDLE;
525 hw->pg_state = MEI_PG_ON;
531 * mei_me_pg_unset_sync - perform pg exit procedure
533 * @dev: the device structure
535 * returns 0 on success an error code otherwise
537 int mei_me_pg_unset_sync(struct mei_device *dev)
539 struct mei_me_hw *hw = to_me_hw(dev);
540 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
543 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
546 dev->pg_event = MEI_PG_EVENT_WAIT;
550 mutex_unlock(&dev->device_lock);
551 wait_event_timeout(dev->wait_pg,
552 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
553 mutex_lock(&dev->device_lock);
556 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
557 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
561 dev->pg_event = MEI_PG_EVENT_IDLE;
562 hw->pg_state = MEI_PG_OFF;
568 * mei_me_pg_is_enabled - detect if PG is supported by HW
570 * @dev: the device structure
572 * returns: true is pg supported, false otherwise
574 static bool mei_me_pg_is_enabled(struct mei_device *dev)
576 struct mei_me_hw *hw = to_me_hw(dev);
577 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
579 if ((reg & ME_PGIC_HRA) == 0)
582 if (dev->version.major_version < HBM_MAJOR_VERSION_PGI)
585 if (dev->version.major_version == HBM_MAJOR_VERSION_PGI &&
586 dev->version.minor_version < HBM_MINOR_VERSION_PGI)
592 dev_dbg(&dev->pdev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
593 !!(reg & ME_PGIC_HRA),
594 dev->version.major_version,
595 dev->version.minor_version,
596 HBM_MAJOR_VERSION_PGI,
597 HBM_MINOR_VERSION_PGI);
603 * mei_me_irq_quick_handler - The ISR of the MEI device
605 * @irq: The irq number
606 * @dev_id: pointer to the device structure
608 * returns irqreturn_t
611 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
613 struct mei_device *dev = (struct mei_device *) dev_id;
614 struct mei_me_hw *hw = to_me_hw(dev);
615 u32 csr_reg = mei_hcsr_read(hw);
617 if ((csr_reg & H_IS) != H_IS)
620 /* clear H_IS bit in H_CSR */
621 mei_me_reg_write(hw, H_CSR, csr_reg);
623 return IRQ_WAKE_THREAD;
627 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
630 * @irq: The irq number
631 * @dev_id: pointer to the device structure
633 * returns irqreturn_t
636 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
638 struct mei_device *dev = (struct mei_device *) dev_id;
639 struct mei_cl_cb complete_list;
643 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
644 /* initialize our complete list */
645 mutex_lock(&dev->device_lock);
646 mei_io_list_init(&complete_list);
648 /* Ack the interrupt here
649 * In case of MSI we don't go through the quick handler */
650 if (pci_dev_msi_enabled(dev->pdev))
651 mei_clear_interrupts(dev);
653 /* check if ME wants a reset */
654 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
655 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
656 schedule_work(&dev->reset_work);
660 /* check if we need to start the dev */
661 if (!mei_host_is_ready(dev)) {
662 if (mei_hw_is_ready(dev)) {
663 mei_me_hw_reset_release(dev);
664 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
666 dev->recvd_hw_ready = true;
667 wake_up_interruptible(&dev->wait_hw_ready);
669 dev_dbg(&dev->pdev->dev, "Spurious Interrupt\n");
673 /* check slots available for reading */
674 slots = mei_count_full_read_slots(dev);
676 dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
677 rets = mei_irq_read_handler(dev, &complete_list, &slots);
678 /* There is a race between ME write and interrupt delivery:
679 * Not all data is always available immediately after the
680 * interrupt, so try to read again on the next interrupt.
682 if (rets == -ENODATA)
685 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
686 dev_err(&dev->pdev->dev, "mei_irq_read_handler ret = %d.\n",
688 schedule_work(&dev->reset_work);
693 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
696 * During PG handshake only allowed write is the replay to the
697 * PG exit message, so block calling write function
698 * if the pg state is not idle
700 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
701 rets = mei_irq_write_handler(dev, &complete_list);
702 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
705 mei_irq_compl_handler(dev, &complete_list);
708 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
709 mutex_unlock(&dev->device_lock);
713 static const struct mei_hw_ops mei_me_hw_ops = {
715 .pg_state = mei_me_pg_state,
717 .host_is_ready = mei_me_host_is_ready,
719 .hw_is_ready = mei_me_hw_is_ready,
720 .hw_reset = mei_me_hw_reset,
721 .hw_config = mei_me_hw_config,
722 .hw_start = mei_me_hw_start,
724 .pg_is_enabled = mei_me_pg_is_enabled,
726 .intr_clear = mei_me_intr_clear,
727 .intr_enable = mei_me_intr_enable,
728 .intr_disable = mei_me_intr_disable,
730 .hbuf_free_slots = mei_me_hbuf_empty_slots,
731 .hbuf_is_ready = mei_me_hbuf_is_empty,
732 .hbuf_max_len = mei_me_hbuf_max_len,
734 .write = mei_me_write_message,
736 .rdbuf_full_slots = mei_me_count_full_read_slots,
737 .read_hdr = mei_me_mecbrw_read,
738 .read = mei_me_read_slots
741 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
744 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
745 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
746 return (reg & 0x600) == 0x200;
749 #define MEI_CFG_FW_NM \
750 .quirk_probe = mei_me_fw_type_nm
752 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
755 /* Read ME FW Status check for SPS Firmware */
756 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
757 /* if bits [19:16] = 15, running SPS Firmware */
758 return (reg & 0xf0000) == 0xf0000;
761 #define MEI_CFG_FW_SPS \
762 .quirk_probe = mei_me_fw_type_sps
765 #define MEI_CFG_LEGACY_HFS \
768 #define MEI_CFG_ICH_HFS \
769 .fw_status.count = 1, \
770 .fw_status.status[0] = PCI_CFG_HFS_1
772 #define MEI_CFG_PCH_HFS \
773 .fw_status.count = 2, \
774 .fw_status.status[0] = PCI_CFG_HFS_1, \
775 .fw_status.status[1] = PCI_CFG_HFS_2
778 /* ICH Legacy devices */
779 const struct mei_cfg mei_me_legacy_cfg = {
784 const struct mei_cfg mei_me_ich_cfg = {
789 const struct mei_cfg mei_me_pch_cfg = {
794 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
795 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
800 /* PCH Lynx Point with quirk for SPS Firmware exclusion */
801 const struct mei_cfg mei_me_lpt_cfg = {
807 * mei_me_dev_init - allocates and initializes the mei device structure
809 * @pdev: The pci device structure
810 * @cfg: per device generation config
812 * returns The mei_device_device pointer on success, NULL on failure.
814 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
815 const struct mei_cfg *cfg)
817 struct mei_device *dev;
819 dev = kzalloc(sizeof(struct mei_device) +
820 sizeof(struct mei_me_hw), GFP_KERNEL);
824 mei_device_init(dev, cfg);
826 dev->ops = &mei_me_hw_ops;