3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @dev: the device structure
32 * @offset: offset from which to read the data
34 * returns register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @dev: the device structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * returns ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @dev: the device structure
73 * returns ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @dev: the device structure
85 * returns H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @dev: the device structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_hw_config - configure hw dependent settings
110 static void mei_me_hw_config(struct mei_device *dev)
112 struct mei_me_hw *hw = to_me_hw(dev);
113 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
114 /* Doesn't change in runtime */
115 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
117 hw->pg_state = MEI_PG_OFF;
121 * mei_me_pg_state - translate internal pg state
122 * to the mei power gating state
125 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
127 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
129 struct mei_me_hw *hw = to_me_hw(dev);
134 * mei_clear_interrupts - clear and stop interrupts
136 * @dev: the device structure
138 static void mei_me_intr_clear(struct mei_device *dev)
140 struct mei_me_hw *hw = to_me_hw(dev);
141 u32 hcsr = mei_hcsr_read(hw);
142 if ((hcsr & H_IS) == H_IS)
143 mei_me_reg_write(hw, H_CSR, hcsr);
146 * mei_me_intr_enable - enables mei device interrupts
148 * @dev: the device structure
150 static void mei_me_intr_enable(struct mei_device *dev)
152 struct mei_me_hw *hw = to_me_hw(dev);
153 u32 hcsr = mei_hcsr_read(hw);
155 mei_hcsr_set(hw, hcsr);
159 * mei_disable_interrupts - disables mei device interrupts
161 * @dev: the device structure
163 static void mei_me_intr_disable(struct mei_device *dev)
165 struct mei_me_hw *hw = to_me_hw(dev);
166 u32 hcsr = mei_hcsr_read(hw);
168 mei_hcsr_set(hw, hcsr);
172 * mei_me_hw_reset_release - release device from the reset
174 * @dev: the device structure
176 static void mei_me_hw_reset_release(struct mei_device *dev)
178 struct mei_me_hw *hw = to_me_hw(dev);
179 u32 hcsr = mei_hcsr_read(hw);
183 mei_hcsr_set(hw, hcsr);
185 /* complete this write before we set host ready on another CPU */
189 * mei_me_hw_reset - resets fw via mei csr register.
191 * @dev: the device structure
192 * @intr_enable: if interrupt should be enabled after reset.
194 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
196 struct mei_me_hw *hw = to_me_hw(dev);
197 u32 hcsr = mei_hcsr_read(hw);
199 hcsr |= H_RST | H_IG | H_IS;
206 dev->recvd_hw_ready = false;
207 mei_me_reg_write(hw, H_CSR, hcsr);
210 * Host reads the H_CSR once to ensure that the
211 * posted write to H_CSR completes.
213 hcsr = mei_hcsr_read(hw);
215 if ((hcsr & H_RST) == 0)
216 dev_warn(&dev->pdev->dev, "H_RST is not set = 0x%08X", hcsr);
218 if ((hcsr & H_RDY) == H_RDY)
219 dev_warn(&dev->pdev->dev, "H_RDY is not cleared 0x%08X", hcsr);
221 if (intr_enable == false)
222 mei_me_hw_reset_release(dev);
228 * mei_me_host_set_ready - enable device
234 static void mei_me_host_set_ready(struct mei_device *dev)
236 struct mei_me_hw *hw = to_me_hw(dev);
237 hw->host_hw_state = mei_hcsr_read(hw);
238 hw->host_hw_state |= H_IE | H_IG | H_RDY;
239 mei_hcsr_set(hw, hw->host_hw_state);
242 * mei_me_host_is_ready - check whether the host has turned ready
247 static bool mei_me_host_is_ready(struct mei_device *dev)
249 struct mei_me_hw *hw = to_me_hw(dev);
250 hw->host_hw_state = mei_hcsr_read(hw);
251 return (hw->host_hw_state & H_RDY) == H_RDY;
255 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
260 static bool mei_me_hw_is_ready(struct mei_device *dev)
262 struct mei_me_hw *hw = to_me_hw(dev);
263 hw->me_hw_state = mei_me_mecsr_read(hw);
264 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
267 static int mei_me_hw_ready_wait(struct mei_device *dev)
269 mutex_unlock(&dev->device_lock);
270 wait_event_timeout(dev->wait_hw_ready,
272 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
273 mutex_lock(&dev->device_lock);
274 if (!dev->recvd_hw_ready) {
275 dev_err(&dev->pdev->dev, "wait hw ready failed\n");
279 dev->recvd_hw_ready = false;
283 static int mei_me_hw_start(struct mei_device *dev)
285 int ret = mei_me_hw_ready_wait(dev);
288 dev_dbg(&dev->pdev->dev, "hw is ready\n");
290 mei_me_host_set_ready(dev);
296 * mei_hbuf_filled_slots - gets number of device filled buffer slots
298 * @dev: the device structure
300 * returns number of filled slots
302 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
304 struct mei_me_hw *hw = to_me_hw(dev);
305 char read_ptr, write_ptr;
307 hw->host_hw_state = mei_hcsr_read(hw);
309 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
310 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
312 return (unsigned char) (write_ptr - read_ptr);
316 * mei_me_hbuf_is_empty - checks if host buffer is empty.
318 * @dev: the device structure
320 * returns true if empty, false - otherwise.
322 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
324 return mei_hbuf_filled_slots(dev) == 0;
328 * mei_me_hbuf_empty_slots - counts write empty slots.
330 * @dev: the device structure
332 * returns -EOVERFLOW if overflow, otherwise empty slots count
334 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
336 unsigned char filled_slots, empty_slots;
338 filled_slots = mei_hbuf_filled_slots(dev);
339 empty_slots = dev->hbuf_depth - filled_slots;
341 /* check for overflow */
342 if (filled_slots > dev->hbuf_depth)
348 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
350 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
355 * mei_me_write_message - writes a message to mei device.
357 * @dev: the device structure
358 * @header: mei HECI header of message
359 * @buf: message payload will be written
361 * This function returns -EIO if write has failed
363 static int mei_me_write_message(struct mei_device *dev,
364 struct mei_msg_hdr *header,
367 struct mei_me_hw *hw = to_me_hw(dev);
369 unsigned long length = header->length;
370 u32 *reg_buf = (u32 *)buf;
376 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
378 empty_slots = mei_hbuf_empty_slots(dev);
379 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
381 dw_cnt = mei_data2slots(length);
382 if (empty_slots < 0 || dw_cnt > empty_slots)
385 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
387 for (i = 0; i < length / 4; i++)
388 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
393 memcpy(®, &buf[length - rem], rem);
394 mei_me_reg_write(hw, H_CB_WW, reg);
397 hcsr = mei_hcsr_read(hw) | H_IG;
398 mei_hcsr_set(hw, hcsr);
399 if (!mei_me_hw_is_ready(dev))
406 * mei_me_count_full_read_slots - counts read full slots.
408 * @dev: the device structure
410 * returns -EOVERFLOW if overflow, otherwise filled slots count
412 static int mei_me_count_full_read_slots(struct mei_device *dev)
414 struct mei_me_hw *hw = to_me_hw(dev);
415 char read_ptr, write_ptr;
416 unsigned char buffer_depth, filled_slots;
418 hw->me_hw_state = mei_me_mecsr_read(hw);
419 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
420 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
421 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
422 filled_slots = (unsigned char) (write_ptr - read_ptr);
424 /* check for overflow */
425 if (filled_slots > buffer_depth)
428 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
429 return (int)filled_slots;
433 * mei_me_read_slots - reads a message from mei device.
435 * @dev: the device structure
436 * @buffer: message buffer will be written
437 * @buffer_length: message size will be read
439 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
440 unsigned long buffer_length)
442 struct mei_me_hw *hw = to_me_hw(dev);
443 u32 *reg_buf = (u32 *)buffer;
446 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
447 *reg_buf++ = mei_me_mecbrw_read(dev);
449 if (buffer_length > 0) {
450 u32 reg = mei_me_mecbrw_read(dev);
451 memcpy(reg_buf, ®, buffer_length);
454 hcsr = mei_hcsr_read(hw) | H_IG;
455 mei_hcsr_set(hw, hcsr);
460 * mei_me_pg_enter - write pg enter register to mei device.
462 * @dev: the device structure
464 static void mei_me_pg_enter(struct mei_device *dev)
466 struct mei_me_hw *hw = to_me_hw(dev);
467 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
468 reg |= H_HPG_CSR_PGI;
469 mei_me_reg_write(hw, H_HPG_CSR, reg);
473 * mei_me_pg_enter - write pg enter register to mei device.
475 * @dev: the device structure
477 static void mei_me_pg_exit(struct mei_device *dev)
479 struct mei_me_hw *hw = to_me_hw(dev);
480 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
482 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
484 reg |= H_HPG_CSR_PGIHEXR;
485 mei_me_reg_write(hw, H_HPG_CSR, reg);
489 * mei_me_pg_set_sync - perform pg entry procedure
491 * @dev: the device structure
493 * returns 0 on success an error code otherwise
495 int mei_me_pg_set_sync(struct mei_device *dev)
497 struct mei_me_hw *hw = to_me_hw(dev);
498 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
501 dev->pg_event = MEI_PG_EVENT_WAIT;
503 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
507 mutex_unlock(&dev->device_lock);
508 wait_event_timeout(dev->wait_pg,
509 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
510 mutex_lock(&dev->device_lock);
512 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
513 mei_me_pg_enter(dev);
519 dev->pg_event = MEI_PG_EVENT_IDLE;
520 hw->pg_state = MEI_PG_ON;
526 * mei_me_pg_unset_sync - perform pg exit procedure
528 * @dev: the device structure
530 * returns 0 on success an error code otherwise
532 int mei_me_pg_unset_sync(struct mei_device *dev)
534 struct mei_me_hw *hw = to_me_hw(dev);
535 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
538 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
541 dev->pg_event = MEI_PG_EVENT_WAIT;
545 mutex_unlock(&dev->device_lock);
546 wait_event_timeout(dev->wait_pg,
547 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
548 mutex_lock(&dev->device_lock);
551 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
552 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
556 dev->pg_event = MEI_PG_EVENT_IDLE;
557 hw->pg_state = MEI_PG_OFF;
563 * mei_me_pg_is_enabled - detect if PG is supported by HW
565 * @dev: the device structure
567 * returns: true is pg supported, false otherwise
569 static bool mei_me_pg_is_enabled(struct mei_device *dev)
571 struct mei_me_hw *hw = to_me_hw(dev);
572 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
574 if ((reg & ME_PGIC_HRA) == 0)
577 if (!dev->hbm_f_pg_supported)
583 dev_dbg(&dev->pdev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
584 !!(reg & ME_PGIC_HRA),
585 dev->version.major_version,
586 dev->version.minor_version,
587 HBM_MAJOR_VERSION_PGI,
588 HBM_MINOR_VERSION_PGI);
594 * mei_me_irq_quick_handler - The ISR of the MEI device
596 * @irq: The irq number
597 * @dev_id: pointer to the device structure
599 * returns irqreturn_t
602 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
604 struct mei_device *dev = (struct mei_device *) dev_id;
605 struct mei_me_hw *hw = to_me_hw(dev);
606 u32 csr_reg = mei_hcsr_read(hw);
608 if ((csr_reg & H_IS) != H_IS)
611 /* clear H_IS bit in H_CSR */
612 mei_me_reg_write(hw, H_CSR, csr_reg);
614 return IRQ_WAKE_THREAD;
618 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
621 * @irq: The irq number
622 * @dev_id: pointer to the device structure
624 * returns irqreturn_t
627 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
629 struct mei_device *dev = (struct mei_device *) dev_id;
630 struct mei_cl_cb complete_list;
634 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
635 /* initialize our complete list */
636 mutex_lock(&dev->device_lock);
637 mei_io_list_init(&complete_list);
639 /* Ack the interrupt here
640 * In case of MSI we don't go through the quick handler */
641 if (pci_dev_msi_enabled(dev->pdev))
642 mei_clear_interrupts(dev);
644 /* check if ME wants a reset */
645 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
646 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
647 schedule_work(&dev->reset_work);
651 /* check if we need to start the dev */
652 if (!mei_host_is_ready(dev)) {
653 if (mei_hw_is_ready(dev)) {
654 mei_me_hw_reset_release(dev);
655 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
657 dev->recvd_hw_ready = true;
658 wake_up(&dev->wait_hw_ready);
660 dev_dbg(&dev->pdev->dev, "Spurious Interrupt\n");
664 /* check slots available for reading */
665 slots = mei_count_full_read_slots(dev);
667 dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
668 rets = mei_irq_read_handler(dev, &complete_list, &slots);
669 /* There is a race between ME write and interrupt delivery:
670 * Not all data is always available immediately after the
671 * interrupt, so try to read again on the next interrupt.
673 if (rets == -ENODATA)
676 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
677 dev_err(&dev->pdev->dev, "mei_irq_read_handler ret = %d.\n",
679 schedule_work(&dev->reset_work);
684 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
687 * During PG handshake only allowed write is the replay to the
688 * PG exit message, so block calling write function
689 * if the pg state is not idle
691 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
692 rets = mei_irq_write_handler(dev, &complete_list);
693 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
696 mei_irq_compl_handler(dev, &complete_list);
699 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
700 mutex_unlock(&dev->device_lock);
704 static const struct mei_hw_ops mei_me_hw_ops = {
706 .pg_state = mei_me_pg_state,
708 .host_is_ready = mei_me_host_is_ready,
710 .hw_is_ready = mei_me_hw_is_ready,
711 .hw_reset = mei_me_hw_reset,
712 .hw_config = mei_me_hw_config,
713 .hw_start = mei_me_hw_start,
715 .pg_is_enabled = mei_me_pg_is_enabled,
717 .intr_clear = mei_me_intr_clear,
718 .intr_enable = mei_me_intr_enable,
719 .intr_disable = mei_me_intr_disable,
721 .hbuf_free_slots = mei_me_hbuf_empty_slots,
722 .hbuf_is_ready = mei_me_hbuf_is_empty,
723 .hbuf_max_len = mei_me_hbuf_max_len,
725 .write = mei_me_write_message,
727 .rdbuf_full_slots = mei_me_count_full_read_slots,
728 .read_hdr = mei_me_mecbrw_read,
729 .read = mei_me_read_slots
732 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
735 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
736 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
737 return (reg & 0x600) == 0x200;
740 #define MEI_CFG_FW_NM \
741 .quirk_probe = mei_me_fw_type_nm
743 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
746 /* Read ME FW Status check for SPS Firmware */
747 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
748 /* if bits [19:16] = 15, running SPS Firmware */
749 return (reg & 0xf0000) == 0xf0000;
752 #define MEI_CFG_FW_SPS \
753 .quirk_probe = mei_me_fw_type_sps
756 #define MEI_CFG_LEGACY_HFS \
759 #define MEI_CFG_ICH_HFS \
760 .fw_status.count = 1, \
761 .fw_status.status[0] = PCI_CFG_HFS_1
763 #define MEI_CFG_PCH_HFS \
764 .fw_status.count = 2, \
765 .fw_status.status[0] = PCI_CFG_HFS_1, \
766 .fw_status.status[1] = PCI_CFG_HFS_2
769 /* ICH Legacy devices */
770 const struct mei_cfg mei_me_legacy_cfg = {
775 const struct mei_cfg mei_me_ich_cfg = {
780 const struct mei_cfg mei_me_pch_cfg = {
785 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
786 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
791 /* PCH Lynx Point with quirk for SPS Firmware exclusion */
792 const struct mei_cfg mei_me_lpt_cfg = {
798 * mei_me_dev_init - allocates and initializes the mei device structure
800 * @pdev: The pci device structure
801 * @cfg: per device generation config
803 * returns The mei_device_device pointer on success, NULL on failure.
805 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
806 const struct mei_cfg *cfg)
808 struct mei_device *dev;
810 dev = kzalloc(sizeof(struct mei_device) +
811 sizeof(struct mei_me_hw), GFP_KERNEL);
815 mei_device_init(dev, cfg);
817 dev->ops = &mei_me_hw_ops;