3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
18 #include <linux/jiffies.h>
19 #include <linux/delay.h>
20 #include <linux/kthread.h>
21 #include <linux/irqreturn.h>
23 #include <linux/mei.h>
31 * mei_txe_reg_read - Reads 32bit data from the txe device
33 * @base_addr: registers base address
34 * @offset: register offset
36 * Return: register value
38 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
41 return ioread32(base_addr + offset);
45 * mei_txe_reg_write - Writes 32bit data to the txe device
47 * @base_addr: registers base address
48 * @offset: register offset
49 * @value: the value to write
51 static inline void mei_txe_reg_write(void __iomem *base_addr,
52 unsigned long offset, u32 value)
54 iowrite32(value, base_addr + offset);
58 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
60 * @hw: the txe hardware structure
61 * @offset: register offset
63 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
65 * Return: register value
67 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
70 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
74 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
76 * @hw: the txe hardware structure
77 * @offset: register offset
79 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
81 * Return: register value
83 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
86 WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
87 return mei_txe_sec_reg_read_silent(hw, offset);
90 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
91 * doesn't check for aliveness
93 * @hw: the txe hardware structure
94 * @offset: register offset
95 * @value: value to write
97 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
99 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
100 unsigned long offset, u32 value)
102 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
106 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
108 * @hw: the txe hardware structure
109 * @offset: register offset
110 * @value: value to write
112 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
114 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
115 unsigned long offset, u32 value)
117 WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
118 mei_txe_sec_reg_write_silent(hw, offset, value);
121 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
123 * @hw: the txe hardware structure
124 * @offset: offset from which to read the data
126 * Return: the byte read.
128 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
129 unsigned long offset)
131 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
135 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
137 * @hw: the txe hardware structure
138 * @offset: offset from which to write the data
139 * @value: the byte to write
141 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
142 unsigned long offset, u32 value)
144 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
148 * mei_txe_aliveness_set - request for aliveness change
150 * @dev: the device structure
151 * @req: requested aliveness value
153 * Request for aliveness change and returns true if the change is
154 * really needed and false if aliveness is already
155 * in the requested state
157 * Locking: called under "dev->device_lock" lock
159 * Return: true if request was send
161 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
164 struct mei_txe_hw *hw = to_txe_hw(dev);
165 bool do_req = hw->aliveness != req;
167 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
170 dev->pg_event = MEI_PG_EVENT_WAIT;
171 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
178 * mei_txe_aliveness_req_get - get aliveness requested register value
180 * @dev: the device structure
182 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
183 * from HICR_HOST_ALIVENESS_REQ register value
185 * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
187 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
189 struct mei_txe_hw *hw = to_txe_hw(dev);
192 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
193 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
197 * mei_txe_aliveness_get - get aliveness response register value
199 * @dev: the device structure
201 * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
204 static u32 mei_txe_aliveness_get(struct mei_device *dev)
206 struct mei_txe_hw *hw = to_txe_hw(dev);
209 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
210 return reg & HICR_HOST_ALIVENESS_RESP_ACK;
214 * mei_txe_aliveness_poll - waits for aliveness to settle
216 * @dev: the device structure
217 * @expected: expected aliveness value
219 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
221 * Return: > 0 if the expected value was received, -ETIME otherwise
223 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
225 struct mei_txe_hw *hw = to_txe_hw(dev);
229 hw->aliveness = mei_txe_aliveness_get(dev);
230 if (hw->aliveness == expected) {
231 dev->pg_event = MEI_PG_EVENT_IDLE;
233 "aliveness settled after %d msecs\n", t);
236 mutex_unlock(&dev->device_lock);
237 msleep(MSEC_PER_SEC / 5);
238 mutex_lock(&dev->device_lock);
239 t += MSEC_PER_SEC / 5;
240 } while (t < SEC_ALIVENESS_WAIT_TIMEOUT);
242 dev->pg_event = MEI_PG_EVENT_IDLE;
243 dev_err(dev->dev, "aliveness timed out\n");
248 * mei_txe_aliveness_wait - waits for aliveness to settle
250 * @dev: the device structure
251 * @expected: expected aliveness value
253 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
255 * Return: 0 on success and < 0 otherwise
257 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
259 struct mei_txe_hw *hw = to_txe_hw(dev);
260 const unsigned long timeout =
261 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
265 hw->aliveness = mei_txe_aliveness_get(dev);
266 if (hw->aliveness == expected)
269 mutex_unlock(&dev->device_lock);
270 err = wait_event_timeout(hw->wait_aliveness_resp,
271 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
272 mutex_lock(&dev->device_lock);
274 hw->aliveness = mei_txe_aliveness_get(dev);
275 ret = hw->aliveness == expected ? 0 : -ETIME;
278 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
279 err, hw->aliveness, dev->pg_event);
281 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
282 jiffies_to_msecs(timeout - err),
283 hw->aliveness, dev->pg_event);
285 dev->pg_event = MEI_PG_EVENT_IDLE;
290 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
292 * @dev: the device structure
293 * @req: requested aliveness value
295 * Return: 0 on success and < 0 otherwise
297 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
299 if (mei_txe_aliveness_set(dev, req))
300 return mei_txe_aliveness_wait(dev, req);
305 * mei_txe_pg_is_enabled - detect if PG is supported by HW
307 * @dev: the device structure
309 * Return: true is pg supported, false otherwise
311 static bool mei_txe_pg_is_enabled(struct mei_device *dev)
317 * mei_txe_pg_state - translate aliveness register value
318 * to the mei power gating state
320 * @dev: the device structure
322 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
324 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
326 struct mei_txe_hw *hw = to_txe_hw(dev);
328 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
332 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
334 * @dev: the device structure
336 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
338 struct mei_txe_hw *hw = to_txe_hw(dev);
340 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
341 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
342 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
343 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
347 * mei_txe_input_doorbell_set - sets bit 0 in
348 * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
350 * @hw: the txe hardware structure
352 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
354 /* Clear the interrupt cause */
355 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
356 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
360 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
362 * @hw: the txe hardware structure
364 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
366 mei_txe_br_reg_write(hw,
367 SICR_SEC_IPC_OUTPUT_STATUS_REG,
368 SEC_IPC_OUTPUT_STATUS_RDY);
372 * mei_txe_is_input_ready - check if TXE is ready for receiving data
374 * @dev: the device structure
376 * Return: true if INPUT STATUS READY bit is set
378 static bool mei_txe_is_input_ready(struct mei_device *dev)
380 struct mei_txe_hw *hw = to_txe_hw(dev);
383 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
384 return !!(SEC_IPC_INPUT_STATUS_RDY & status);
388 * mei_txe_intr_clear - clear all interrupts
390 * @dev: the device structure
392 static inline void mei_txe_intr_clear(struct mei_device *dev)
394 struct mei_txe_hw *hw = to_txe_hw(dev);
396 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
397 SEC_IPC_HOST_INT_STATUS_PENDING);
398 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
399 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
403 * mei_txe_intr_disable - disable all interrupts
405 * @dev: the device structure
407 static void mei_txe_intr_disable(struct mei_device *dev)
409 struct mei_txe_hw *hw = to_txe_hw(dev);
411 mei_txe_br_reg_write(hw, HHIER_REG, 0);
412 mei_txe_br_reg_write(hw, HIER_REG, 0);
415 * mei_txe_intr_disable - enable all interrupts
417 * @dev: the device structure
419 static void mei_txe_intr_enable(struct mei_device *dev)
421 struct mei_txe_hw *hw = to_txe_hw(dev);
423 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
424 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
428 * mei_txe_pending_interrupts - check if there are pending interrupts
429 * only Aliveness, Input ready, and output doorbell are of relevance
431 * @dev: the device structure
433 * Checks if there are pending interrupts
434 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
436 * Return: true if there are pending interrupts
438 static bool mei_txe_pending_interrupts(struct mei_device *dev)
441 struct mei_txe_hw *hw = to_txe_hw(dev);
442 bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
449 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
450 !!(hw->intr_cause & TXE_INTR_IN_READY),
451 !!(hw->intr_cause & TXE_INTR_READINESS),
452 !!(hw->intr_cause & TXE_INTR_ALIVENESS),
453 !!(hw->intr_cause & TXE_INTR_OUT_DB));
459 * mei_txe_input_payload_write - write a dword to the host buffer
462 * @dev: the device structure
463 * @idx: index in the host buffer
466 static void mei_txe_input_payload_write(struct mei_device *dev,
467 unsigned long idx, u32 value)
469 struct mei_txe_hw *hw = to_txe_hw(dev);
471 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
472 (idx * sizeof(u32)), value);
476 * mei_txe_out_data_read - read dword from the device buffer
479 * @dev: the device structure
480 * @idx: index in the device buffer
482 * Return: register value at index
484 static u32 mei_txe_out_data_read(const struct mei_device *dev,
487 struct mei_txe_hw *hw = to_txe_hw(dev);
489 return mei_txe_br_reg_read(hw,
490 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
496 * mei_txe_readiness_set_host_rdy - set host readiness bit
498 * @dev: the device structure
500 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
502 struct mei_txe_hw *hw = to_txe_hw(dev);
504 mei_txe_br_reg_write(hw,
505 SICR_HOST_IPC_READINESS_REQ_REG,
506 SICR_HOST_IPC_READINESS_HOST_RDY);
510 * mei_txe_readiness_clear - clear host readiness bit
512 * @dev: the device structure
514 static void mei_txe_readiness_clear(struct mei_device *dev)
516 struct mei_txe_hw *hw = to_txe_hw(dev);
518 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
519 SICR_HOST_IPC_READINESS_RDY_CLR);
522 * mei_txe_readiness_get - Reads and returns
523 * the HICR_SEC_IPC_READINESS register value
525 * @dev: the device structure
527 * Return: the HICR_SEC_IPC_READINESS register value
529 static u32 mei_txe_readiness_get(struct mei_device *dev)
531 struct mei_txe_hw *hw = to_txe_hw(dev);
533 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
538 * mei_txe_readiness_is_sec_rdy - check readiness
539 * for HICR_SEC_IPC_READINESS_SEC_RDY
541 * @readiness: cached readiness state
543 * Return: true if readiness bit is set
545 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
547 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
551 * mei_txe_hw_is_ready - check if the hw is ready
553 * @dev: the device structure
555 * Return: true if sec is ready
557 static bool mei_txe_hw_is_ready(struct mei_device *dev)
559 u32 readiness = mei_txe_readiness_get(dev);
561 return mei_txe_readiness_is_sec_rdy(readiness);
565 * mei_txe_host_is_ready - check if the host is ready
567 * @dev: the device structure
569 * Return: true if host is ready
571 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
573 struct mei_txe_hw *hw = to_txe_hw(dev);
574 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
576 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
580 * mei_txe_readiness_wait - wait till readiness settles
582 * @dev: the device structure
584 * Return: 0 on success and -ETIME on timeout
586 static int mei_txe_readiness_wait(struct mei_device *dev)
588 if (mei_txe_hw_is_ready(dev))
591 mutex_unlock(&dev->device_lock);
592 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
593 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
594 mutex_lock(&dev->device_lock);
595 if (!dev->recvd_hw_ready) {
596 dev_err(dev->dev, "wait for readiness failed\n");
600 dev->recvd_hw_ready = false;
604 static const struct mei_fw_status mei_txe_fw_sts = {
606 .status[0] = PCI_CFG_TXE_FW_STS0,
607 .status[1] = PCI_CFG_TXE_FW_STS1
611 * mei_txe_fw_status - read fw status register from pci config space
614 * @fw_status: fw status register values
616 * Return: 0 on success, error otherwise
618 static int mei_txe_fw_status(struct mei_device *dev,
619 struct mei_fw_status *fw_status)
621 const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
622 struct pci_dev *pdev = to_pci_dev(dev->dev);
629 fw_status->count = fw_src->count;
630 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
631 ret = pci_read_config_dword(pdev,
632 fw_src->status[i], &fw_status->status[i]);
641 * mei_txe_hw_config - configure hardware at the start of the devices
643 * @dev: the device structure
645 * Configure hardware at the start of the device should be done only
646 * once at the device probe time
648 static void mei_txe_hw_config(struct mei_device *dev)
651 struct mei_txe_hw *hw = to_txe_hw(dev);
653 /* Doesn't change in runtime */
654 dev->hbuf_depth = PAYLOAD_SIZE / 4;
656 hw->aliveness = mei_txe_aliveness_get(dev);
657 hw->readiness = mei_txe_readiness_get(dev);
659 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
660 hw->aliveness, hw->readiness);
665 * mei_txe_write - writes a message to device.
667 * @dev: the device structure
668 * @header: header of message
669 * @buf: message buffer will be written
671 * Return: 0 if success, <0 - otherwise.
674 static int mei_txe_write(struct mei_device *dev,
675 struct mei_msg_hdr *header, unsigned char *buf)
677 struct mei_txe_hw *hw = to_txe_hw(dev);
679 unsigned long length;
680 int slots = dev->hbuf_depth;
681 u32 *reg_buf = (u32 *)buf;
685 if (WARN_ON(!header || !buf))
688 length = header->length;
690 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
692 dw_cnt = mei_data2slots(length);
696 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
699 /* Enable Input Ready Interrupt. */
700 mei_txe_input_ready_interrupt_enable(dev);
702 if (!mei_txe_is_input_ready(dev)) {
703 struct mei_fw_status fw_status;
705 mei_fw_status(dev, &fw_status);
706 dev_err(dev->dev, "Input is not ready " FW_STS_FMT "\n",
707 FW_STS_PRM(fw_status));
711 mei_txe_input_payload_write(dev, 0, *((u32 *)header));
713 for (i = 0; i < length / 4; i++)
714 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
720 memcpy(®, &buf[length - rem], rem);
721 mei_txe_input_payload_write(dev, i + 1, reg);
724 /* after each write the whole buffer is consumed */
727 /* Set Input-Doorbell */
728 mei_txe_input_doorbell_set(hw);
734 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
736 * @dev: the device structure
738 * Return: the PAYLOAD_SIZE - 4
740 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
742 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
746 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
748 * @dev: the device structure
750 * Return: always hbuf_depth
752 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
754 struct mei_txe_hw *hw = to_txe_hw(dev);
760 * mei_txe_count_full_read_slots - mimics the me device circular buffer
762 * @dev: the device structure
764 * Return: always buffer size in dwords count
766 static int mei_txe_count_full_read_slots(struct mei_device *dev)
768 /* read buffers has static size */
769 return PAYLOAD_SIZE / 4;
773 * mei_txe_read_hdr - read message header which is always in 4 first bytes
775 * @dev: the device structure
777 * Return: mei message header
780 static u32 mei_txe_read_hdr(const struct mei_device *dev)
782 return mei_txe_out_data_read(dev, 0);
785 * mei_txe_read - reads a message from the txe device.
787 * @dev: the device structure
788 * @buf: message buffer will be written
789 * @len: message size will be read
791 * Return: -EINVAL on error wrong argument and 0 on success
793 static int mei_txe_read(struct mei_device *dev,
794 unsigned char *buf, unsigned long len)
797 struct mei_txe_hw *hw = to_txe_hw(dev);
802 if (WARN_ON(!buf || !len))
805 reg_buf = (u32 *)buf;
808 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
809 len, mei_txe_out_data_read(dev, 0));
811 for (i = 0; i < len / 4; i++) {
812 /* skip header: index starts from 1 */
813 reg = mei_txe_out_data_read(dev, i + 1);
814 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
819 reg = mei_txe_out_data_read(dev, i + 1);
820 memcpy(reg_buf, ®, rem);
823 mei_txe_output_ready_set(hw);
828 * mei_txe_hw_reset - resets host and fw.
830 * @dev: the device structure
831 * @intr_enable: if interrupt should be enabled after reset.
833 * Return: 0 on success and < 0 in case of error
835 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
837 struct mei_txe_hw *hw = to_txe_hw(dev);
841 * read input doorbell to ensure consistency between Bridge and SeC
842 * return value might be garbage return
844 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
846 aliveness_req = mei_txe_aliveness_req_get(dev);
847 hw->aliveness = mei_txe_aliveness_get(dev);
849 /* Disable interrupts in this stage we will poll */
850 mei_txe_intr_disable(dev);
853 * If Aliveness Request and Aliveness Response are not equal then
854 * wait for them to be equal
855 * Since we might have interrupts disabled - poll for it
857 if (aliveness_req != hw->aliveness)
858 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
859 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
864 * If Aliveness Request and Aliveness Response are set then clear them
867 mei_txe_aliveness_set(dev, 0);
868 if (mei_txe_aliveness_poll(dev, 0) < 0) {
869 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
875 * Set readiness RDY_CLR bit
877 mei_txe_readiness_clear(dev);
883 * mei_txe_hw_start - start the hardware after reset
885 * @dev: the device structure
887 * Return: 0 on success an error code otherwise
889 static int mei_txe_hw_start(struct mei_device *dev)
891 struct mei_txe_hw *hw = to_txe_hw(dev);
896 /* bring back interrupts */
897 mei_txe_intr_enable(dev);
899 ret = mei_txe_readiness_wait(dev);
901 dev_err(dev->dev, "waiting for readiness failed\n");
906 * If HISR.INT2_STS interrupt status bit is set then clear it.
908 hisr = mei_txe_br_reg_read(hw, HISR_REG);
909 if (hisr & HISR_INT_2_STS)
910 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
912 /* Clear the interrupt cause of OutputDoorbell */
913 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
915 ret = mei_txe_aliveness_set_sync(dev, 1);
917 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
921 /* enable input ready interrupts:
922 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
924 mei_txe_input_ready_interrupt_enable(dev);
927 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
928 mei_txe_output_ready_set(hw);
930 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
932 mei_txe_readiness_set_host_rdy(dev);
938 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
939 * single bit mask and acknowledge the interrupts
941 * @dev: the device structure
942 * @do_ack: acknowledge interrupts
944 * Return: true if found interrupts to process.
946 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
948 struct mei_txe_hw *hw = to_txe_hw(dev);
955 /* read interrupt registers */
956 hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
957 generated = (hhisr & IPC_HHIER_MSK);
961 hisr = mei_txe_br_reg_read(hw, HISR_REG);
963 aliveness = mei_txe_aliveness_get(dev);
964 if (hhisr & IPC_HHIER_SEC && aliveness)
965 ipc_isr = mei_txe_sec_reg_read_silent(hw,
966 SEC_IPC_HOST_INT_STATUS_REG);
970 generated = generated ||
971 (hisr & HISR_INT_STS_MSK) ||
972 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
974 if (generated && do_ack) {
975 /* Save the interrupt causes */
976 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
977 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
978 hw->intr_cause |= TXE_INTR_IN_READY;
981 mei_txe_intr_disable(dev);
982 /* Clear the interrupts in hierarchy:
983 * IPC and Bridge, than the High Level */
984 mei_txe_sec_reg_write_silent(hw,
985 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
986 mei_txe_br_reg_write(hw, HISR_REG, hisr);
987 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
995 * mei_txe_irq_quick_handler - The ISR of the MEI device
997 * @irq: The irq number
998 * @dev_id: pointer to the device structure
1000 * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1001 * IRQ_NONE otherwise
1003 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1005 struct mei_device *dev = dev_id;
1007 if (mei_txe_check_and_ack_intrs(dev, true))
1008 return IRQ_WAKE_THREAD;
1014 * mei_txe_irq_thread_handler - txe interrupt thread
1016 * @irq: The irq number
1017 * @dev_id: pointer to the device structure
1019 * Return: IRQ_HANDLED
1021 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1023 struct mei_device *dev = (struct mei_device *) dev_id;
1024 struct mei_txe_hw *hw = to_txe_hw(dev);
1025 struct mei_cl_cb complete_list;
1029 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1030 mei_txe_br_reg_read(hw, HHISR_REG),
1031 mei_txe_br_reg_read(hw, HISR_REG),
1032 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1035 /* initialize our complete list */
1036 mutex_lock(&dev->device_lock);
1037 mei_io_list_init(&complete_list);
1039 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1040 mei_txe_check_and_ack_intrs(dev, true);
1042 /* show irq events */
1043 mei_txe_pending_interrupts(dev);
1045 hw->aliveness = mei_txe_aliveness_get(dev);
1046 hw->readiness = mei_txe_readiness_get(dev);
1049 * Detection of TXE driver going through reset
1050 * or TXE driver resetting the HECI interface.
1052 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1053 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1055 /* Check if SeC is going through reset */
1056 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1057 dev_dbg(dev->dev, "we need to start the dev.\n");
1058 dev->recvd_hw_ready = true;
1060 dev->recvd_hw_ready = false;
1061 if (dev->dev_state != MEI_DEV_RESETTING) {
1063 dev_warn(dev->dev, "FW not ready: resetting.\n");
1064 schedule_work(&dev->reset_work);
1069 wake_up(&dev->wait_hw_ready);
1072 /************************************************************/
1073 /* Check interrupt cause:
1074 * Aliveness: Detection of SeC acknowledge of host request that
1075 * it remain alive or host cancellation of that request.
1078 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1079 /* Clear the interrupt cause */
1081 "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1082 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1083 if (waitqueue_active(&hw->wait_aliveness_resp))
1084 wake_up(&hw->wait_aliveness_resp);
1089 * Detection of SeC having sent output to host
1091 slots = mei_count_full_read_slots(dev);
1092 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1094 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1095 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1097 "mei_irq_read_handler ret = %d.\n", rets);
1099 schedule_work(&dev->reset_work);
1103 /* Input Ready: Detection if host can write to SeC */
1104 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1105 dev->hbuf_is_ready = true;
1106 hw->slots = dev->hbuf_depth;
1109 if (hw->aliveness && dev->hbuf_is_ready) {
1110 /* get the real register value */
1111 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1112 rets = mei_irq_write_handler(dev, &complete_list);
1113 if (rets && rets != -EMSGSIZE)
1114 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1116 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1119 mei_irq_compl_handler(dev, &complete_list);
1122 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1124 mutex_unlock(&dev->device_lock);
1126 mei_enable_interrupts(dev);
1130 static const struct mei_hw_ops mei_txe_hw_ops = {
1132 .host_is_ready = mei_txe_host_is_ready,
1134 .fw_status = mei_txe_fw_status,
1135 .pg_state = mei_txe_pg_state,
1137 .hw_is_ready = mei_txe_hw_is_ready,
1138 .hw_reset = mei_txe_hw_reset,
1139 .hw_config = mei_txe_hw_config,
1140 .hw_start = mei_txe_hw_start,
1142 .pg_is_enabled = mei_txe_pg_is_enabled,
1144 .intr_clear = mei_txe_intr_clear,
1145 .intr_enable = mei_txe_intr_enable,
1146 .intr_disable = mei_txe_intr_disable,
1148 .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1149 .hbuf_is_ready = mei_txe_is_input_ready,
1150 .hbuf_max_len = mei_txe_hbuf_max_len,
1152 .write = mei_txe_write,
1154 .rdbuf_full_slots = mei_txe_count_full_read_slots,
1155 .read_hdr = mei_txe_read_hdr,
1157 .read = mei_txe_read,
1162 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1166 * Return: struct mei_device * on success or NULL
1168 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1170 struct mei_device *dev;
1171 struct mei_txe_hw *hw;
1173 dev = kzalloc(sizeof(struct mei_device) +
1174 sizeof(struct mei_txe_hw), GFP_KERNEL);
1178 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1180 hw = to_txe_hw(dev);
1182 init_waitqueue_head(&hw->wait_aliveness_resp);
1188 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1190 * @dev: the device structure
1191 * @addr: physical address start of the range
1192 * @range: physical range size
1194 * Return: 0 on success an error code otherwise
1196 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1198 struct mei_txe_hw *hw = to_txe_hw(dev);
1200 u32 lo32 = lower_32_bits(addr);
1201 u32 hi32 = upper_32_bits(addr);
1204 /* SATT is limited to 36 Bits */
1208 /* SATT has to be 16Byte aligned */
1212 /* SATT range has to be 4Bytes aligned */
1216 /* SATT is limited to 32 MB range*/
1217 if (range > SATT_RANGE_MAX)
1220 ctrl = SATT2_CTRL_VALID_MSK;
1221 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1223 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1224 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1225 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1226 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",