2 * Atmel MultiMedia Card Interface driver
4 * Copyright (C) 2004-2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27 #include <linux/types.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/sdio.h>
32 #include <mach/atmel-mci.h>
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
37 #include <asm/unaligned.h>
40 #include <mach/board.h>
42 #include "atmel-mci-regs.h"
44 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
45 #define ATMCI_DMA_THRESHOLD 16
54 enum atmel_mci_state {
58 STATE_WAITING_NOTBUSY,
73 struct atmel_mci_caps {
83 struct atmel_mci_dma {
84 struct dma_chan *chan;
85 struct dma_async_tx_descriptor *data_desc;
89 * struct atmel_mci - MMC controller state shared between all slots
90 * @lock: Spinlock protecting the queue and associated data.
91 * @regs: Pointer to MMIO registers.
92 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
93 * @pio_offset: Offset into the current scatterlist entry.
94 * @buffer: Buffer used if we don't have the r/w proof capability. We
95 * don't have the time to switch pdc buffers so we have to use only
96 * one buffer for the full transaction.
97 * @buf_size: size of the buffer.
98 * @phys_buf_addr: buffer address needed for pdc.
99 * @cur_slot: The slot which is currently using the controller.
100 * @mrq: The request currently being processed on @cur_slot,
101 * or NULL if the controller is idle.
102 * @cmd: The command currently being sent to the card, or NULL.
103 * @data: The data currently being transferred, or NULL if no data
104 * transfer is in progress.
105 * @data_size: just data->blocks * data->blksz.
106 * @dma: DMA client state.
107 * @data_chan: DMA channel being used for the current data transfer.
108 * @cmd_status: Snapshot of SR taken upon completion of the current
109 * command. Only valid when EVENT_CMD_COMPLETE is pending.
110 * @data_status: Snapshot of SR taken upon completion of the current
111 * data transfer. Only valid when EVENT_DATA_COMPLETE or
112 * EVENT_DATA_ERROR is pending.
113 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
115 * @tasklet: Tasklet running the request state machine.
116 * @pending_events: Bitmask of events flagged by the interrupt handler
117 * to be processed by the tasklet.
118 * @completed_events: Bitmask of events which the state machine has
120 * @state: Tasklet state.
121 * @queue: List of slots waiting for access to the controller.
122 * @need_clock_update: Update the clock rate before the next request.
123 * @need_reset: Reset controller before next request.
124 * @mode_reg: Value of the MR register.
125 * @cfg_reg: Value of the CFG register.
126 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
127 * rate and timeout calculations.
128 * @mapbase: Physical address of the MMIO registers.
129 * @mck: The peripheral bus clock hooked up to the MMC controller.
130 * @pdev: Platform device associated with the MMC controller.
131 * @slot: Slots sharing this MMC controller.
132 * @caps: MCI capabilities depending on MCI version.
133 * @prepare_data: function to setup MCI before data transfer which
134 * depends on MCI capabilities.
135 * @submit_data: function to start data transfer which depends on MCI
137 * @stop_transfer: function to stop data transfer which depends on MCI
143 * @lock is a softirq-safe spinlock protecting @queue as well as
144 * @cur_slot, @mrq and @state. These must always be updated
145 * at the same time while holding @lock.
147 * @lock also protects mode_reg and need_clock_update since these are
148 * used to synchronize mode register updates with the queue
151 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
152 * and must always be written at the same time as the slot is added to
155 * @pending_events and @completed_events are accessed using atomic bit
156 * operations, so they don't need any locking.
158 * None of the fields touched by the interrupt handler need any
159 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
160 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
161 * interrupts must be disabled and @data_status updated with a
162 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
163 * CMDRDY interrupt must be disabled and @cmd_status updated with a
164 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
165 * bytes_xfered field of @data must be written. This is ensured by
172 struct scatterlist *sg;
173 unsigned int pio_offset;
174 unsigned int *buffer;
175 unsigned int buf_size;
176 dma_addr_t buf_phys_addr;
178 struct atmel_mci_slot *cur_slot;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
182 unsigned int data_size;
184 struct atmel_mci_dma dma;
185 struct dma_chan *data_chan;
186 struct dma_slave_config dma_conf;
192 struct tasklet_struct tasklet;
193 unsigned long pending_events;
194 unsigned long completed_events;
195 enum atmel_mci_state state;
196 struct list_head queue;
198 bool need_clock_update;
202 unsigned long bus_hz;
203 unsigned long mapbase;
205 struct platform_device *pdev;
207 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
209 struct atmel_mci_caps caps;
211 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
212 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
213 void (*stop_transfer)(struct atmel_mci *host);
217 * struct atmel_mci_slot - MMC slot state
218 * @mmc: The mmc_host representing this slot.
219 * @host: The MMC controller this slot is using.
220 * @sdc_reg: Value of SDCR to be written before using this slot.
221 * @sdio_irq: SDIO irq mask for this slot.
222 * @mrq: mmc_request currently being processed or waiting to be
223 * processed, or NULL when the slot is idle.
224 * @queue_node: List node for placing this node in the @queue list of
226 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
227 * @flags: Random state bits associated with the slot.
228 * @detect_pin: GPIO pin used for card detection, or negative if not
230 * @wp_pin: GPIO pin used for card write protect sending, or negative
232 * @detect_is_active_high: The state of the detect pin when it is active.
233 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
235 struct atmel_mci_slot {
236 struct mmc_host *mmc;
237 struct atmel_mci *host;
242 struct mmc_request *mrq;
243 struct list_head queue_node;
247 #define ATMCI_CARD_PRESENT 0
248 #define ATMCI_CARD_NEED_INIT 1
249 #define ATMCI_SHUTDOWN 2
250 #define ATMCI_SUSPENDED 3
254 bool detect_is_active_high;
256 struct timer_list detect_timer;
259 #define atmci_test_and_clear_pending(host, event) \
260 test_and_clear_bit(event, &host->pending_events)
261 #define atmci_set_completed(host, event) \
262 set_bit(event, &host->completed_events)
263 #define atmci_set_pending(host, event) \
264 set_bit(event, &host->pending_events)
267 * The debugfs stuff below is mostly optimized away when
268 * CONFIG_DEBUG_FS is not set.
270 static int atmci_req_show(struct seq_file *s, void *v)
272 struct atmel_mci_slot *slot = s->private;
273 struct mmc_request *mrq;
274 struct mmc_command *cmd;
275 struct mmc_command *stop;
276 struct mmc_data *data;
278 /* Make sure we get a consistent snapshot */
279 spin_lock_bh(&slot->host->lock);
289 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
290 cmd->opcode, cmd->arg, cmd->flags,
291 cmd->resp[0], cmd->resp[1], cmd->resp[2],
292 cmd->resp[3], cmd->error);
294 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
295 data->bytes_xfered, data->blocks,
296 data->blksz, data->flags, data->error);
299 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
300 stop->opcode, stop->arg, stop->flags,
301 stop->resp[0], stop->resp[1], stop->resp[2],
302 stop->resp[3], stop->error);
305 spin_unlock_bh(&slot->host->lock);
310 static int atmci_req_open(struct inode *inode, struct file *file)
312 return single_open(file, atmci_req_show, inode->i_private);
315 static const struct file_operations atmci_req_fops = {
316 .owner = THIS_MODULE,
317 .open = atmci_req_open,
320 .release = single_release,
323 static void atmci_show_status_reg(struct seq_file *s,
324 const char *regname, u32 value)
326 static const char *sr_bit[] = {
357 seq_printf(s, "%s:\t0x%08x", regname, value);
358 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
359 if (value & (1 << i)) {
361 seq_printf(s, " %s", sr_bit[i]);
363 seq_puts(s, " UNKNOWN");
369 static int atmci_regs_show(struct seq_file *s, void *v)
371 struct atmel_mci *host = s->private;
374 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
379 * Grab a more or less consistent snapshot. Note that we're
380 * not disabling interrupts, so IMR and SR may not be
383 spin_lock_bh(&host->lock);
384 clk_enable(host->mck);
385 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
386 clk_disable(host->mck);
387 spin_unlock_bh(&host->lock);
389 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
391 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
392 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
393 buf[ATMCI_MR / 4] & 0xff);
394 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
395 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
396 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
397 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
399 buf[ATMCI_BLKR / 4] & 0xffff,
400 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
401 if (host->caps.has_cstor_reg)
402 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
404 /* Don't read RSPR and RDR; it will consume the data there */
406 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
407 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
409 if (host->caps.has_dma) {
412 val = buf[ATMCI_DMA / 4];
413 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
416 1 << (((val >> 4) & 3) + 1) : 1,
417 val & ATMCI_DMAEN ? " DMAEN" : "");
419 if (host->caps.has_cfg_reg) {
422 val = buf[ATMCI_CFG / 4];
423 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
425 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
426 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
427 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
428 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
436 static int atmci_regs_open(struct inode *inode, struct file *file)
438 return single_open(file, atmci_regs_show, inode->i_private);
441 static const struct file_operations atmci_regs_fops = {
442 .owner = THIS_MODULE,
443 .open = atmci_regs_open,
446 .release = single_release,
449 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
451 struct mmc_host *mmc = slot->mmc;
452 struct atmel_mci *host = slot->host;
456 root = mmc->debugfs_root;
460 node = debugfs_create_file("regs", S_IRUSR, root, host,
467 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
471 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
475 node = debugfs_create_x32("pending_events", S_IRUSR, root,
476 (u32 *)&host->pending_events);
480 node = debugfs_create_x32("completed_events", S_IRUSR, root,
481 (u32 *)&host->completed_events);
488 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
491 static inline unsigned int atmci_get_version(struct atmel_mci *host)
493 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
496 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
500 * It is easier here to use us instead of ns for the timeout,
501 * it prevents from overflows during calculation.
503 unsigned int us = DIV_ROUND_UP(ns, 1000);
505 /* Maximum clock frequency is host->bus_hz/2 */
506 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
509 static void atmci_set_timeout(struct atmel_mci *host,
510 struct atmel_mci_slot *slot, struct mmc_data *data)
512 static unsigned dtomul_to_shift[] = {
513 0, 4, 7, 8, 10, 12, 16, 20
519 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
520 + data->timeout_clks;
522 for (dtomul = 0; dtomul < 8; dtomul++) {
523 unsigned shift = dtomul_to_shift[dtomul];
524 dtocyc = (timeout + (1 << shift) - 1) >> shift;
534 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
535 dtocyc << dtomul_to_shift[dtomul]);
536 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
540 * Return mask with command flags to be enabled for this command.
542 static u32 atmci_prepare_command(struct mmc_host *mmc,
543 struct mmc_command *cmd)
545 struct mmc_data *data;
548 cmd->error = -EINPROGRESS;
550 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
552 if (cmd->flags & MMC_RSP_PRESENT) {
553 if (cmd->flags & MMC_RSP_136)
554 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
556 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
560 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
561 * it's too difficult to determine whether this is an ACMD or
562 * not. Better make it 64.
564 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
566 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
567 cmdr |= ATMCI_CMDR_OPDCMD;
571 cmdr |= ATMCI_CMDR_START_XFER;
573 if (cmd->opcode == SD_IO_RW_EXTENDED) {
574 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
576 if (data->flags & MMC_DATA_STREAM)
577 cmdr |= ATMCI_CMDR_STREAM;
578 else if (data->blocks > 1)
579 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
581 cmdr |= ATMCI_CMDR_BLOCK;
584 if (data->flags & MMC_DATA_READ)
585 cmdr |= ATMCI_CMDR_TRDIR_READ;
591 static void atmci_send_command(struct atmel_mci *host,
592 struct mmc_command *cmd, u32 cmd_flags)
597 dev_vdbg(&host->pdev->dev,
598 "start command: ARGR=0x%08x CMDR=0x%08x\n",
599 cmd->arg, cmd_flags);
601 atmci_writel(host, ATMCI_ARGR, cmd->arg);
602 atmci_writel(host, ATMCI_CMDR, cmd_flags);
605 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
607 atmci_send_command(host, data->stop, host->stop_cmdr);
608 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
612 * Configure given PDC buffer taking care of alignement issues.
613 * Update host->data_size and host->sg.
615 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
616 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
618 u32 pointer_reg, counter_reg;
619 unsigned int buf_size;
621 if (dir == XFER_RECEIVE) {
622 pointer_reg = ATMEL_PDC_RPR;
623 counter_reg = ATMEL_PDC_RCR;
625 pointer_reg = ATMEL_PDC_TPR;
626 counter_reg = ATMEL_PDC_TCR;
629 if (buf_nb == PDC_SECOND_BUF) {
630 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
631 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
634 if (!host->caps.has_rwproof) {
635 buf_size = host->buf_size;
636 atmci_writel(host, pointer_reg, host->buf_phys_addr);
638 buf_size = sg_dma_len(host->sg);
639 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
642 if (host->data_size <= buf_size) {
643 if (host->data_size & 0x3) {
644 /* If size is different from modulo 4, transfer bytes */
645 atmci_writel(host, counter_reg, host->data_size);
646 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
648 /* Else transfer 32-bits words */
649 atmci_writel(host, counter_reg, host->data_size / 4);
653 /* We assume the size of a page is 32-bits aligned */
654 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
655 host->data_size -= sg_dma_len(host->sg);
657 host->sg = sg_next(host->sg);
662 * Configure PDC buffer according to the data size ie configuring one or two
663 * buffers. Don't use this function if you want to configure only the second
664 * buffer. In this case, use atmci_pdc_set_single_buf.
666 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
668 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
670 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
674 * Unmap sg lists, called when transfer is finished.
676 static void atmci_pdc_cleanup(struct atmel_mci *host)
678 struct mmc_data *data = host->data;
681 dma_unmap_sg(&host->pdev->dev,
682 data->sg, data->sg_len,
683 ((data->flags & MMC_DATA_WRITE)
684 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
688 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
689 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
690 * interrupt needed for both transfer directions.
692 static void atmci_pdc_complete(struct atmel_mci *host)
694 int transfer_size = host->data->blocks * host->data->blksz;
696 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
698 if ((!host->caps.has_rwproof)
699 && (host->data->flags & MMC_DATA_READ))
700 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
701 host->buffer, transfer_size);
703 atmci_pdc_cleanup(host);
706 * If the card was removed, data will be NULL. No point trying
707 * to send the stop command or waiting for NBUSY in this case.
710 atmci_set_pending(host, EVENT_XFER_COMPLETE);
711 tasklet_schedule(&host->tasklet);
715 static void atmci_dma_cleanup(struct atmel_mci *host)
717 struct mmc_data *data = host->data;
720 dma_unmap_sg(host->dma.chan->device->dev,
721 data->sg, data->sg_len,
722 ((data->flags & MMC_DATA_WRITE)
723 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
727 * This function is called by the DMA driver from tasklet context.
729 static void atmci_dma_complete(void *arg)
731 struct atmel_mci *host = arg;
732 struct mmc_data *data = host->data;
734 dev_vdbg(&host->pdev->dev, "DMA complete\n");
736 if (host->caps.has_dma)
737 /* Disable DMA hardware handshaking on MCI */
738 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
740 atmci_dma_cleanup(host);
743 * If the card was removed, data will be NULL. No point trying
744 * to send the stop command or waiting for NBUSY in this case.
747 atmci_set_pending(host, EVENT_XFER_COMPLETE);
748 tasklet_schedule(&host->tasklet);
751 * Regardless of what the documentation says, we have
752 * to wait for NOTBUSY even after block read
755 * When the DMA transfer is complete, the controller
756 * may still be reading the CRC from the card, i.e.
757 * the data transfer is still in progress and we
758 * haven't seen all the potential error bits yet.
760 * The interrupt handler will schedule a different
761 * tasklet to finish things up when the data transfer
762 * is completely done.
764 * We may not complete the mmc request here anyway
765 * because the mmc layer may call back and cause us to
766 * violate the "don't submit new operations from the
767 * completion callback" rule of the dma engine
770 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
775 * Returns a mask of interrupt flags to be enabled after the whole
776 * request has been prepared.
778 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
782 data->error = -EINPROGRESS;
786 host->data_chan = NULL;
788 iflags = ATMCI_DATA_ERROR_FLAGS;
791 * Errata: MMC data write operation with less than 12
792 * bytes is impossible.
794 * Errata: MCI Transmit Data Register (TDR) FIFO
795 * corruption when length is not multiple of 4.
797 if (data->blocks * data->blksz < 12
798 || (data->blocks * data->blksz) & 3)
799 host->need_reset = true;
801 host->pio_offset = 0;
802 if (data->flags & MMC_DATA_READ)
803 iflags |= ATMCI_RXRDY;
805 iflags |= ATMCI_TXRDY;
811 * Set interrupt flags and set block length into the MCI mode register even
812 * if this value is also accessible in the MCI block register. It seems to be
813 * necessary before the High Speed MCI version. It also map sg and configure
817 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
821 enum dma_data_direction dir;
823 data->error = -EINPROGRESS;
827 iflags = ATMCI_DATA_ERROR_FLAGS;
829 /* Enable pdc mode */
830 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
832 if (data->flags & MMC_DATA_READ) {
833 dir = DMA_FROM_DEVICE;
834 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
837 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
841 tmp = atmci_readl(host, ATMCI_MR);
843 tmp |= ATMCI_BLKLEN(data->blksz);
844 atmci_writel(host, ATMCI_MR, tmp);
847 host->data_size = data->blocks * data->blksz;
848 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
850 if ((!host->caps.has_rwproof)
851 && (host->data->flags & MMC_DATA_WRITE))
852 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
853 host->buffer, host->data_size);
856 atmci_pdc_set_both_buf(host,
857 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
863 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
865 struct dma_chan *chan;
866 struct dma_async_tx_descriptor *desc;
867 struct scatterlist *sg;
869 enum dma_data_direction direction;
870 enum dma_transfer_direction slave_dirn;
874 data->error = -EINPROGRESS;
880 iflags = ATMCI_DATA_ERROR_FLAGS;
883 * We don't do DMA on "complex" transfers, i.e. with
884 * non-word-aligned buffers or lengths. Also, we don't bother
885 * with all the DMA setup overhead for short transfers.
887 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
888 return atmci_prepare_data(host, data);
890 return atmci_prepare_data(host, data);
892 for_each_sg(data->sg, sg, data->sg_len, i) {
893 if (sg->offset & 3 || sg->length & 3)
894 return atmci_prepare_data(host, data);
897 /* If we don't have a channel, we can't do DMA */
898 chan = host->dma.chan;
900 host->data_chan = chan;
905 if (host->caps.has_dma)
906 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
908 if (data->flags & MMC_DATA_READ) {
909 direction = DMA_FROM_DEVICE;
910 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
912 direction = DMA_TO_DEVICE;
913 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
916 sglen = dma_map_sg(chan->device->dev, data->sg,
917 data->sg_len, direction);
919 dmaengine_slave_config(chan, &host->dma_conf);
920 desc = dmaengine_prep_slave_sg(chan,
921 data->sg, sglen, slave_dirn,
922 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
926 host->dma.data_desc = desc;
927 desc->callback = atmci_dma_complete;
928 desc->callback_param = host;
932 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
937 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
943 * Start PDC according to transfer direction.
946 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
948 if (data->flags & MMC_DATA_READ)
949 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
951 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
955 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
957 struct dma_chan *chan = host->data_chan;
958 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
961 dmaengine_submit(desc);
962 dma_async_issue_pending(chan);
966 static void atmci_stop_transfer(struct atmel_mci *host)
968 atmci_set_pending(host, EVENT_XFER_COMPLETE);
969 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
973 * Stop data transfer because error(s) occured.
975 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
977 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
980 static void atmci_stop_transfer_dma(struct atmel_mci *host)
982 struct dma_chan *chan = host->data_chan;
985 dmaengine_terminate_all(chan);
986 atmci_dma_cleanup(host);
988 /* Data transfer was stopped by the interrupt handler */
989 atmci_set_pending(host, EVENT_XFER_COMPLETE);
990 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
995 * Start a request: prepare data if needed, prepare the command and activate
998 static void atmci_start_request(struct atmel_mci *host,
999 struct atmel_mci_slot *slot)
1001 struct mmc_request *mrq;
1002 struct mmc_command *cmd;
1003 struct mmc_data *data;
1008 host->cur_slot = slot;
1011 host->pending_events = 0;
1012 host->completed_events = 0;
1013 host->cmd_status = 0;
1014 host->data_status = 0;
1016 if (host->need_reset) {
1017 iflags = atmci_readl(host, ATMCI_IMR);
1018 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1019 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1020 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1021 atmci_writel(host, ATMCI_MR, host->mode_reg);
1022 if (host->caps.has_cfg_reg)
1023 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1024 atmci_writel(host, ATMCI_IER, iflags);
1025 host->need_reset = false;
1027 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1029 iflags = atmci_readl(host, ATMCI_IMR);
1030 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1031 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1034 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1035 /* Send init sequence (74 clock cycles) */
1036 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1037 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1043 atmci_set_timeout(host, slot, data);
1045 /* Must set block count/size before sending command */
1046 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1047 | ATMCI_BLKLEN(data->blksz));
1048 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1049 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1051 iflags |= host->prepare_data(host, data);
1054 iflags |= ATMCI_CMDRDY;
1056 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1057 atmci_send_command(host, cmd, cmdflags);
1060 host->submit_data(host, data);
1063 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1064 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1065 if (!(data->flags & MMC_DATA_WRITE))
1066 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1067 if (data->flags & MMC_DATA_STREAM)
1068 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1070 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1074 * We could have enabled interrupts earlier, but I suspect
1075 * that would open up a nice can of interesting race
1076 * conditions (e.g. command and data complete, but stop not
1079 atmci_writel(host, ATMCI_IER, iflags);
1082 static void atmci_queue_request(struct atmel_mci *host,
1083 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1085 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1088 spin_lock_bh(&host->lock);
1090 if (host->state == STATE_IDLE) {
1091 host->state = STATE_SENDING_CMD;
1092 atmci_start_request(host, slot);
1094 list_add_tail(&slot->queue_node, &host->queue);
1096 spin_unlock_bh(&host->lock);
1099 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1101 struct atmel_mci_slot *slot = mmc_priv(mmc);
1102 struct atmel_mci *host = slot->host;
1103 struct mmc_data *data;
1108 * We may "know" the card is gone even though there's still an
1109 * electrical connection. If so, we really need to communicate
1110 * this to the MMC core since there won't be any more
1111 * interrupts as the card is completely removed. Otherwise,
1112 * the MMC core might believe the card is still there even
1113 * though the card was just removed very slowly.
1115 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1116 mrq->cmd->error = -ENOMEDIUM;
1117 mmc_request_done(mmc, mrq);
1121 /* We don't support multiple blocks of weird lengths. */
1123 if (data && data->blocks > 1 && data->blksz & 3) {
1124 mrq->cmd->error = -EINVAL;
1125 mmc_request_done(mmc, mrq);
1128 atmci_queue_request(host, slot, mrq);
1131 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1133 struct atmel_mci_slot *slot = mmc_priv(mmc);
1134 struct atmel_mci *host = slot->host;
1137 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1138 switch (ios->bus_width) {
1139 case MMC_BUS_WIDTH_1:
1140 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1142 case MMC_BUS_WIDTH_4:
1143 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1148 unsigned int clock_min = ~0U;
1151 spin_lock_bh(&host->lock);
1152 if (!host->mode_reg) {
1153 clk_enable(host->mck);
1154 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1155 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1156 if (host->caps.has_cfg_reg)
1157 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1161 * Use mirror of ios->clock to prevent race with mmc
1162 * core ios update when finding the minimum.
1164 slot->clock = ios->clock;
1165 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1166 if (host->slot[i] && host->slot[i]->clock
1167 && host->slot[i]->clock < clock_min)
1168 clock_min = host->slot[i]->clock;
1171 /* Calculate clock divider */
1172 if (host->caps.has_odd_clk_div) {
1173 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1175 dev_warn(&mmc->class_dev,
1176 "clock %u too slow; using %lu\n",
1177 clock_min, host->bus_hz / (511 + 2));
1180 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1181 | ATMCI_MR_CLKODD(clkdiv & 1);
1183 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1185 dev_warn(&mmc->class_dev,
1186 "clock %u too slow; using %lu\n",
1187 clock_min, host->bus_hz / (2 * 256));
1190 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1194 * WRPROOF and RDPROOF prevent overruns/underruns by
1195 * stopping the clock when the FIFO is full/empty.
1196 * This state is not expected to last for long.
1198 if (host->caps.has_rwproof)
1199 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1201 if (host->caps.has_cfg_reg) {
1202 /* setup High Speed mode in relation with card capacity */
1203 if (ios->timing == MMC_TIMING_SD_HS)
1204 host->cfg_reg |= ATMCI_CFG_HSMODE;
1206 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1209 if (list_empty(&host->queue)) {
1210 atmci_writel(host, ATMCI_MR, host->mode_reg);
1211 if (host->caps.has_cfg_reg)
1212 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1214 host->need_clock_update = true;
1217 spin_unlock_bh(&host->lock);
1219 bool any_slot_active = false;
1221 spin_lock_bh(&host->lock);
1223 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1224 if (host->slot[i] && host->slot[i]->clock) {
1225 any_slot_active = true;
1229 if (!any_slot_active) {
1230 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1231 if (host->mode_reg) {
1232 atmci_readl(host, ATMCI_MR);
1233 clk_disable(host->mck);
1237 spin_unlock_bh(&host->lock);
1240 switch (ios->power_mode) {
1242 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1246 * TODO: None of the currently available AVR32-based
1247 * boards allow MMC power to be turned off. Implement
1248 * power control when this can be tested properly.
1250 * We also need to hook this into the clock management
1251 * somehow so that newly inserted cards aren't
1252 * subjected to a fast clock before we have a chance
1253 * to figure out what the maximum rate is. Currently,
1254 * there's no way to avoid this, and there never will
1255 * be for boards that don't support power control.
1261 static int atmci_get_ro(struct mmc_host *mmc)
1263 int read_only = -ENOSYS;
1264 struct atmel_mci_slot *slot = mmc_priv(mmc);
1266 if (gpio_is_valid(slot->wp_pin)) {
1267 read_only = gpio_get_value(slot->wp_pin);
1268 dev_dbg(&mmc->class_dev, "card is %s\n",
1269 read_only ? "read-only" : "read-write");
1275 static int atmci_get_cd(struct mmc_host *mmc)
1277 int present = -ENOSYS;
1278 struct atmel_mci_slot *slot = mmc_priv(mmc);
1280 if (gpio_is_valid(slot->detect_pin)) {
1281 present = !(gpio_get_value(slot->detect_pin) ^
1282 slot->detect_is_active_high);
1283 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1284 present ? "" : "not ");
1290 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1292 struct atmel_mci_slot *slot = mmc_priv(mmc);
1293 struct atmel_mci *host = slot->host;
1296 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1298 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1301 static const struct mmc_host_ops atmci_ops = {
1302 .request = atmci_request,
1303 .set_ios = atmci_set_ios,
1304 .get_ro = atmci_get_ro,
1305 .get_cd = atmci_get_cd,
1306 .enable_sdio_irq = atmci_enable_sdio_irq,
1309 /* Called with host->lock held */
1310 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1311 __releases(&host->lock)
1312 __acquires(&host->lock)
1314 struct atmel_mci_slot *slot = NULL;
1315 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1317 WARN_ON(host->cmd || host->data);
1320 * Update the MMC clock rate if necessary. This may be
1321 * necessary if set_ios() is called when a different slot is
1322 * busy transferring data.
1324 if (host->need_clock_update) {
1325 atmci_writel(host, ATMCI_MR, host->mode_reg);
1326 if (host->caps.has_cfg_reg)
1327 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1330 host->cur_slot->mrq = NULL;
1332 if (!list_empty(&host->queue)) {
1333 slot = list_entry(host->queue.next,
1334 struct atmel_mci_slot, queue_node);
1335 list_del(&slot->queue_node);
1336 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1337 mmc_hostname(slot->mmc));
1338 host->state = STATE_SENDING_CMD;
1339 atmci_start_request(host, slot);
1341 dev_vdbg(&host->pdev->dev, "list empty\n");
1342 host->state = STATE_IDLE;
1345 spin_unlock(&host->lock);
1346 mmc_request_done(prev_mmc, mrq);
1347 spin_lock(&host->lock);
1350 static void atmci_command_complete(struct atmel_mci *host,
1351 struct mmc_command *cmd)
1353 u32 status = host->cmd_status;
1355 /* Read the response from the card (up to 16 bytes) */
1356 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1357 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1358 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1359 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1361 if (status & ATMCI_RTOE)
1362 cmd->error = -ETIMEDOUT;
1363 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1364 cmd->error = -EILSEQ;
1365 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1371 static void atmci_detect_change(unsigned long data)
1373 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1378 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1379 * freeing the interrupt. We must not re-enable the interrupt
1380 * if it has been freed, and if we're shutting down, it
1381 * doesn't really matter whether the card is present or not.
1384 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1387 enable_irq(gpio_to_irq(slot->detect_pin));
1388 present = !(gpio_get_value(slot->detect_pin) ^
1389 slot->detect_is_active_high);
1390 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1392 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1393 present, present_old);
1395 if (present != present_old) {
1396 struct atmel_mci *host = slot->host;
1397 struct mmc_request *mrq;
1399 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1400 present ? "inserted" : "removed");
1402 spin_lock(&host->lock);
1405 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1407 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1409 /* Clean up queue if present */
1412 if (mrq == host->mrq) {
1414 * Reset controller to terminate any ongoing
1415 * commands or data transfers.
1417 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1418 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1419 atmci_writel(host, ATMCI_MR, host->mode_reg);
1420 if (host->caps.has_cfg_reg)
1421 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1426 switch (host->state) {
1429 case STATE_SENDING_CMD:
1430 mrq->cmd->error = -ENOMEDIUM;
1432 host->stop_transfer(host);
1434 case STATE_DATA_XFER:
1435 mrq->data->error = -ENOMEDIUM;
1436 host->stop_transfer(host);
1438 case STATE_WAITING_NOTBUSY:
1439 mrq->data->error = -ENOMEDIUM;
1441 case STATE_SENDING_STOP:
1442 mrq->stop->error = -ENOMEDIUM;
1444 case STATE_END_REQUEST:
1448 atmci_request_end(host, mrq);
1450 list_del(&slot->queue_node);
1451 mrq->cmd->error = -ENOMEDIUM;
1453 mrq->data->error = -ENOMEDIUM;
1455 mrq->stop->error = -ENOMEDIUM;
1457 spin_unlock(&host->lock);
1458 mmc_request_done(slot->mmc, mrq);
1459 spin_lock(&host->lock);
1462 spin_unlock(&host->lock);
1464 mmc_detect_change(slot->mmc, 0);
1468 static void atmci_tasklet_func(unsigned long priv)
1470 struct atmel_mci *host = (struct atmel_mci *)priv;
1471 struct mmc_request *mrq = host->mrq;
1472 struct mmc_data *data = host->data;
1473 enum atmel_mci_state state = host->state;
1474 enum atmel_mci_state prev_state;
1477 spin_lock(&host->lock);
1479 state = host->state;
1481 dev_vdbg(&host->pdev->dev,
1482 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1483 state, host->pending_events, host->completed_events,
1484 atmci_readl(host, ATMCI_IMR));
1493 case STATE_SENDING_CMD:
1495 * Command has been sent, we are waiting for command
1496 * ready. Then we have three next states possible:
1497 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1498 * command needing it or DATA_XFER if there is data.
1500 if (!atmci_test_and_clear_pending(host,
1505 atmci_set_completed(host, EVENT_CMD_RDY);
1506 atmci_command_complete(host, mrq->cmd);
1509 * If there is a command error don't start
1512 if (mrq->cmd->error) {
1513 host->stop_transfer(host);
1515 atmci_writel(host, ATMCI_IDR,
1516 ATMCI_TXRDY | ATMCI_RXRDY
1517 | ATMCI_DATA_ERROR_FLAGS);
1518 state = STATE_END_REQUEST;
1520 state = STATE_DATA_XFER;
1521 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1522 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1523 state = STATE_WAITING_NOTBUSY;
1525 state = STATE_END_REQUEST;
1529 case STATE_DATA_XFER:
1530 if (atmci_test_and_clear_pending(host,
1531 EVENT_DATA_ERROR)) {
1532 atmci_set_completed(host, EVENT_DATA_ERROR);
1533 state = STATE_END_REQUEST;
1538 * A data transfer is in progress. The event expected
1539 * to move to the next state depends of data transfer
1540 * type (PDC or DMA). Once transfer done we can move
1541 * to the next step which is WAITING_NOTBUSY in write
1542 * case and directly SENDING_STOP in read case.
1544 if (!atmci_test_and_clear_pending(host,
1545 EVENT_XFER_COMPLETE))
1548 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1550 if (host->data->flags & MMC_DATA_WRITE) {
1551 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1552 state = STATE_WAITING_NOTBUSY;
1553 } else if (host->mrq->stop) {
1554 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1555 atmci_send_stop_cmd(host, data);
1556 state = STATE_SENDING_STOP;
1559 data->bytes_xfered = data->blocks * data->blksz;
1561 state = STATE_END_REQUEST;
1565 case STATE_WAITING_NOTBUSY:
1567 * We can be in the state for two reasons: a command
1568 * requiring waiting not busy signal (stop command
1569 * included) or a write operation. In the latest case,
1570 * we need to send a stop command.
1572 if (!atmci_test_and_clear_pending(host,
1576 atmci_set_completed(host, EVENT_NOTBUSY);
1580 * For some commands such as CMD53, even if
1581 * there is data transfer, there is no stop
1584 if (host->mrq->stop) {
1585 atmci_writel(host, ATMCI_IER,
1587 atmci_send_stop_cmd(host, data);
1588 state = STATE_SENDING_STOP;
1591 data->bytes_xfered = data->blocks
1594 state = STATE_END_REQUEST;
1597 state = STATE_END_REQUEST;
1600 case STATE_SENDING_STOP:
1602 * In this state, it is important to set host->data to
1603 * NULL (which is tested in the waiting notbusy state)
1604 * in order to go to the end request state instead of
1605 * sending stop again.
1607 if (!atmci_test_and_clear_pending(host,
1613 data->bytes_xfered = data->blocks * data->blksz;
1615 atmci_command_complete(host, mrq->stop);
1616 if (mrq->stop->error) {
1617 host->stop_transfer(host);
1618 atmci_writel(host, ATMCI_IDR,
1619 ATMCI_TXRDY | ATMCI_RXRDY
1620 | ATMCI_DATA_ERROR_FLAGS);
1621 state = STATE_END_REQUEST;
1623 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1624 state = STATE_WAITING_NOTBUSY;
1628 case STATE_END_REQUEST:
1629 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1630 | ATMCI_DATA_ERROR_FLAGS);
1631 status = host->data_status;
1632 if (unlikely(status)) {
1633 host->stop_transfer(host);
1635 if (status & ATMCI_DTOE) {
1636 data->error = -ETIMEDOUT;
1637 } else if (status & ATMCI_DCRCE) {
1638 data->error = -EILSEQ;
1644 atmci_request_end(host, host->mrq);
1648 } while (state != prev_state);
1650 host->state = state;
1652 spin_unlock(&host->lock);
1655 static void atmci_read_data_pio(struct atmel_mci *host)
1657 struct scatterlist *sg = host->sg;
1658 void *buf = sg_virt(sg);
1659 unsigned int offset = host->pio_offset;
1660 struct mmc_data *data = host->data;
1663 unsigned int nbytes = 0;
1666 value = atmci_readl(host, ATMCI_RDR);
1667 if (likely(offset + 4 <= sg->length)) {
1668 put_unaligned(value, (u32 *)(buf + offset));
1673 if (offset == sg->length) {
1674 flush_dcache_page(sg_page(sg));
1675 host->sg = sg = sg_next(sg);
1683 unsigned int remaining = sg->length - offset;
1684 memcpy(buf + offset, &value, remaining);
1685 nbytes += remaining;
1687 flush_dcache_page(sg_page(sg));
1688 host->sg = sg = sg_next(sg);
1692 offset = 4 - remaining;
1694 memcpy(buf, (u8 *)&value + remaining, offset);
1698 status = atmci_readl(host, ATMCI_SR);
1699 if (status & ATMCI_DATA_ERROR_FLAGS) {
1700 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1701 | ATMCI_DATA_ERROR_FLAGS));
1702 host->data_status = status;
1703 data->bytes_xfered += nbytes;
1706 } while (status & ATMCI_RXRDY);
1708 host->pio_offset = offset;
1709 data->bytes_xfered += nbytes;
1714 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1715 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1716 data->bytes_xfered += nbytes;
1718 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1721 static void atmci_write_data_pio(struct atmel_mci *host)
1723 struct scatterlist *sg = host->sg;
1724 void *buf = sg_virt(sg);
1725 unsigned int offset = host->pio_offset;
1726 struct mmc_data *data = host->data;
1729 unsigned int nbytes = 0;
1732 if (likely(offset + 4 <= sg->length)) {
1733 value = get_unaligned((u32 *)(buf + offset));
1734 atmci_writel(host, ATMCI_TDR, value);
1738 if (offset == sg->length) {
1739 host->sg = sg = sg_next(sg);
1747 unsigned int remaining = sg->length - offset;
1750 memcpy(&value, buf + offset, remaining);
1751 nbytes += remaining;
1753 host->sg = sg = sg_next(sg);
1755 atmci_writel(host, ATMCI_TDR, value);
1759 offset = 4 - remaining;
1761 memcpy((u8 *)&value + remaining, buf, offset);
1762 atmci_writel(host, ATMCI_TDR, value);
1766 status = atmci_readl(host, ATMCI_SR);
1767 if (status & ATMCI_DATA_ERROR_FLAGS) {
1768 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1769 | ATMCI_DATA_ERROR_FLAGS));
1770 host->data_status = status;
1771 data->bytes_xfered += nbytes;
1774 } while (status & ATMCI_TXRDY);
1776 host->pio_offset = offset;
1777 data->bytes_xfered += nbytes;
1782 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1783 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1784 data->bytes_xfered += nbytes;
1786 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1789 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1793 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1794 struct atmel_mci_slot *slot = host->slot[i];
1795 if (slot && (status & slot->sdio_irq)) {
1796 mmc_signal_sdio_irq(slot->mmc);
1802 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1804 struct atmel_mci *host = dev_id;
1805 u32 status, mask, pending;
1806 unsigned int pass_count = 0;
1809 status = atmci_readl(host, ATMCI_SR);
1810 mask = atmci_readl(host, ATMCI_IMR);
1811 pending = status & mask;
1815 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1816 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1817 | ATMCI_RXRDY | ATMCI_TXRDY
1818 | ATMCI_ENDRX | ATMCI_ENDTX
1819 | ATMCI_RXBUFF | ATMCI_TXBUFE);
1821 host->data_status = status;
1823 atmci_set_pending(host, EVENT_DATA_ERROR);
1824 tasklet_schedule(&host->tasklet);
1827 if (pending & ATMCI_TXBUFE) {
1828 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1829 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1831 * We can receive this interruption before having configured
1832 * the second pdc buffer, so we need to reconfigure first and
1833 * second buffers again
1835 if (host->data_size) {
1836 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1837 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1838 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1840 atmci_pdc_complete(host);
1842 } else if (pending & ATMCI_ENDTX) {
1843 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1845 if (host->data_size) {
1846 atmci_pdc_set_single_buf(host,
1847 XFER_TRANSMIT, PDC_SECOND_BUF);
1848 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1852 if (pending & ATMCI_RXBUFF) {
1853 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1854 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1856 * We can receive this interruption before having configured
1857 * the second pdc buffer, so we need to reconfigure first and
1858 * second buffers again
1860 if (host->data_size) {
1861 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1862 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1863 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1865 atmci_pdc_complete(host);
1867 } else if (pending & ATMCI_ENDRX) {
1868 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1870 if (host->data_size) {
1871 atmci_pdc_set_single_buf(host,
1872 XFER_RECEIVE, PDC_SECOND_BUF);
1873 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1878 * First mci IPs, so mainly the ones having pdc, have some
1879 * issues with the notbusy signal. You can't get it after
1880 * data transmission if you have not sent a stop command.
1881 * The appropriate workaround is to use the BLKE signal.
1883 if (pending & ATMCI_BLKE) {
1884 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
1886 atmci_set_pending(host, EVENT_NOTBUSY);
1887 tasklet_schedule(&host->tasklet);
1890 if (pending & ATMCI_NOTBUSY) {
1891 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
1893 atmci_set_pending(host, EVENT_NOTBUSY);
1894 tasklet_schedule(&host->tasklet);
1897 if (pending & ATMCI_RXRDY)
1898 atmci_read_data_pio(host);
1899 if (pending & ATMCI_TXRDY)
1900 atmci_write_data_pio(host);
1902 if (pending & ATMCI_CMDRDY) {
1903 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1904 host->cmd_status = status;
1906 atmci_set_pending(host, EVENT_CMD_RDY);
1907 tasklet_schedule(&host->tasklet);
1910 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1911 atmci_sdio_interrupt(host, status);
1913 } while (pass_count++ < 5);
1915 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1918 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1920 struct atmel_mci_slot *slot = dev_id;
1923 * Disable interrupts until the pin has stabilized and check
1924 * the state then. Use mod_timer() since we may be in the
1925 * middle of the timer routine when this interrupt triggers.
1927 disable_irq_nosync(irq);
1928 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1933 static int __init atmci_init_slot(struct atmel_mci *host,
1934 struct mci_slot_pdata *slot_data, unsigned int id,
1935 u32 sdc_reg, u32 sdio_irq)
1937 struct mmc_host *mmc;
1938 struct atmel_mci_slot *slot;
1940 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1944 slot = mmc_priv(mmc);
1947 slot->detect_pin = slot_data->detect_pin;
1948 slot->wp_pin = slot_data->wp_pin;
1949 slot->detect_is_active_high = slot_data->detect_is_active_high;
1950 slot->sdc_reg = sdc_reg;
1951 slot->sdio_irq = sdio_irq;
1953 mmc->ops = &atmci_ops;
1954 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1955 mmc->f_max = host->bus_hz / 2;
1956 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1958 mmc->caps |= MMC_CAP_SDIO_IRQ;
1959 if (host->caps.has_highspeed)
1960 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1962 * Without the read/write proof capability, it is strongly suggested to
1963 * use only one bit for data to prevent fifo underruns and overruns
1964 * which will corrupt data.
1966 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
1967 mmc->caps |= MMC_CAP_4_BIT_DATA;
1969 if (atmci_get_version(host) < 0x200) {
1970 mmc->max_segs = 256;
1971 mmc->max_blk_size = 4095;
1972 mmc->max_blk_count = 256;
1973 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1974 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
1977 mmc->max_req_size = 32768 * 512;
1978 mmc->max_blk_size = 32768;
1979 mmc->max_blk_count = 512;
1982 /* Assume card is present initially */
1983 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1984 if (gpio_is_valid(slot->detect_pin)) {
1985 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1986 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1987 slot->detect_pin = -EBUSY;
1988 } else if (gpio_get_value(slot->detect_pin) ^
1989 slot->detect_is_active_high) {
1990 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1994 if (!gpio_is_valid(slot->detect_pin))
1995 mmc->caps |= MMC_CAP_NEEDS_POLL;
1997 if (gpio_is_valid(slot->wp_pin)) {
1998 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1999 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2000 slot->wp_pin = -EBUSY;
2004 host->slot[id] = slot;
2007 if (gpio_is_valid(slot->detect_pin)) {
2010 setup_timer(&slot->detect_timer, atmci_detect_change,
2011 (unsigned long)slot);
2013 ret = request_irq(gpio_to_irq(slot->detect_pin),
2014 atmci_detect_interrupt,
2015 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2016 "mmc-detect", slot);
2018 dev_dbg(&mmc->class_dev,
2019 "could not request IRQ %d for detect pin\n",
2020 gpio_to_irq(slot->detect_pin));
2021 gpio_free(slot->detect_pin);
2022 slot->detect_pin = -EBUSY;
2026 atmci_init_debugfs(slot);
2031 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2034 /* Debugfs stuff is cleaned up by mmc core */
2036 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2039 mmc_remove_host(slot->mmc);
2041 if (gpio_is_valid(slot->detect_pin)) {
2042 int pin = slot->detect_pin;
2044 free_irq(gpio_to_irq(pin), slot);
2045 del_timer_sync(&slot->detect_timer);
2048 if (gpio_is_valid(slot->wp_pin))
2049 gpio_free(slot->wp_pin);
2051 slot->host->slot[id] = NULL;
2052 mmc_free_host(slot->mmc);
2055 static bool atmci_filter(struct dma_chan *chan, void *slave)
2057 struct mci_dma_data *sl = slave;
2059 if (sl && find_slave_dev(sl) == chan->device->dev) {
2060 chan->private = slave_data_ptr(sl);
2067 static bool atmci_configure_dma(struct atmel_mci *host)
2069 struct mci_platform_data *pdata;
2074 pdata = host->pdev->dev.platform_data;
2076 if (pdata && find_slave_dev(pdata->dma_slave)) {
2077 dma_cap_mask_t mask;
2079 /* Try to grab a DMA channel */
2081 dma_cap_set(DMA_SLAVE, mask);
2083 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2085 if (!host->dma.chan) {
2086 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2089 dev_info(&host->pdev->dev,
2090 "using %s for DMA transfers\n",
2091 dma_chan_name(host->dma.chan));
2093 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2094 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2095 host->dma_conf.src_maxburst = 1;
2096 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2097 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2098 host->dma_conf.dst_maxburst = 1;
2099 host->dma_conf.device_fc = false;
2105 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2106 * HSMCI provides DMA support and a new config register but no more supports
2109 static void __init atmci_get_cap(struct atmel_mci *host)
2111 unsigned int version;
2113 version = atmci_get_version(host);
2114 dev_info(&host->pdev->dev,
2115 "version: 0x%x\n", version);
2117 host->caps.has_dma = 0;
2118 host->caps.has_pdc = 1;
2119 host->caps.has_cfg_reg = 0;
2120 host->caps.has_cstor_reg = 0;
2121 host->caps.has_highspeed = 0;
2122 host->caps.has_rwproof = 0;
2123 host->caps.has_odd_clk_div = 0;
2125 /* keep only major version number */
2126 switch (version & 0xf00) {
2128 host->caps.has_odd_clk_div = 1;
2131 #ifdef CONFIG_AT_HDMAC
2132 host->caps.has_dma = 1;
2134 dev_info(&host->pdev->dev,
2135 "has dma capability but dma engine is not selected, then use pio\n");
2137 host->caps.has_pdc = 0;
2138 host->caps.has_cfg_reg = 1;
2139 host->caps.has_cstor_reg = 1;
2140 host->caps.has_highspeed = 1;
2142 host->caps.has_rwproof = 1;
2146 host->caps.has_pdc = 0;
2147 dev_warn(&host->pdev->dev,
2148 "Unmanaged mci version, set minimum capabilities\n");
2153 static int __init atmci_probe(struct platform_device *pdev)
2155 struct mci_platform_data *pdata;
2156 struct atmel_mci *host;
2157 struct resource *regs;
2158 unsigned int nr_slots;
2162 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2165 pdata = pdev->dev.platform_data;
2168 irq = platform_get_irq(pdev, 0);
2172 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2177 spin_lock_init(&host->lock);
2178 INIT_LIST_HEAD(&host->queue);
2180 host->mck = clk_get(&pdev->dev, "mci_clk");
2181 if (IS_ERR(host->mck)) {
2182 ret = PTR_ERR(host->mck);
2187 host->regs = ioremap(regs->start, resource_size(regs));
2191 clk_enable(host->mck);
2192 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2193 host->bus_hz = clk_get_rate(host->mck);
2194 clk_disable(host->mck);
2196 host->mapbase = regs->start;
2198 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2200 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2202 goto err_request_irq;
2204 /* Get MCI capabilities and set operations according to it */
2205 atmci_get_cap(host);
2206 if (host->caps.has_dma && atmci_configure_dma(host)) {
2207 host->prepare_data = &atmci_prepare_data_dma;
2208 host->submit_data = &atmci_submit_data_dma;
2209 host->stop_transfer = &atmci_stop_transfer_dma;
2210 } else if (host->caps.has_pdc) {
2211 dev_info(&pdev->dev, "using PDC\n");
2212 host->prepare_data = &atmci_prepare_data_pdc;
2213 host->submit_data = &atmci_submit_data_pdc;
2214 host->stop_transfer = &atmci_stop_transfer_pdc;
2216 dev_info(&pdev->dev, "using PIO\n");
2217 host->prepare_data = &atmci_prepare_data;
2218 host->submit_data = &atmci_submit_data;
2219 host->stop_transfer = &atmci_stop_transfer;
2222 platform_set_drvdata(pdev, host);
2224 /* We need at least one slot to succeed */
2227 if (pdata->slot[0].bus_width) {
2228 ret = atmci_init_slot(host, &pdata->slot[0],
2229 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2232 host->buf_size = host->slot[0]->mmc->max_req_size;
2235 if (pdata->slot[1].bus_width) {
2236 ret = atmci_init_slot(host, &pdata->slot[1],
2237 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2240 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2242 host->slot[1]->mmc->max_req_size;
2247 dev_err(&pdev->dev, "init failed: no slot defined\n");
2251 if (!host->caps.has_rwproof) {
2252 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2253 &host->buf_phys_addr,
2255 if (!host->buffer) {
2257 dev_err(&pdev->dev, "buffer allocation failed\n");
2262 dev_info(&pdev->dev,
2263 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2264 host->mapbase, irq, nr_slots);
2270 dma_release_channel(host->dma.chan);
2271 free_irq(irq, host);
2273 iounmap(host->regs);
2281 static int __exit atmci_remove(struct platform_device *pdev)
2283 struct atmel_mci *host = platform_get_drvdata(pdev);
2286 platform_set_drvdata(pdev, NULL);
2289 dma_free_coherent(&pdev->dev, host->buf_size,
2290 host->buffer, host->buf_phys_addr);
2292 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2294 atmci_cleanup_slot(host->slot[i], i);
2297 clk_enable(host->mck);
2298 atmci_writel(host, ATMCI_IDR, ~0UL);
2299 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2300 atmci_readl(host, ATMCI_SR);
2301 clk_disable(host->mck);
2303 #ifdef CONFIG_MMC_ATMELMCI_DMA
2305 dma_release_channel(host->dma.chan);
2308 free_irq(platform_get_irq(pdev, 0), host);
2309 iounmap(host->regs);
2318 static int atmci_suspend(struct device *dev)
2320 struct atmel_mci *host = dev_get_drvdata(dev);
2323 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2324 struct atmel_mci_slot *slot = host->slot[i];
2329 ret = mmc_suspend_host(slot->mmc);
2332 slot = host->slot[i];
2334 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2335 mmc_resume_host(host->slot[i]->mmc);
2336 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2341 set_bit(ATMCI_SUSPENDED, &slot->flags);
2348 static int atmci_resume(struct device *dev)
2350 struct atmel_mci *host = dev_get_drvdata(dev);
2354 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2355 struct atmel_mci_slot *slot = host->slot[i];
2358 slot = host->slot[i];
2361 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2363 err = mmc_resume_host(slot->mmc);
2367 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2372 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2373 #define ATMCI_PM_OPS (&atmci_pm)
2375 #define ATMCI_PM_OPS NULL
2378 static struct platform_driver atmci_driver = {
2379 .remove = __exit_p(atmci_remove),
2381 .name = "atmel_mci",
2386 static int __init atmci_init(void)
2388 return platform_driver_probe(&atmci_driver, atmci_probe);
2391 static void __exit atmci_exit(void)
2393 platform_driver_unregister(&atmci_driver);
2396 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2397 module_exit(atmci_exit);
2399 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2400 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2401 MODULE_LICENSE("GPL v2");