drivers/mmc/host/atmel-mci.c

   1 /*
   2  * Atmel MultiMedia Card Interface driver
   3  *
   4  * Copyright (C) 2004-2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_gpio.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/types.h>
  31 #include <linux/platform_data/atmel.h>
  32
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/sdio.h>
  35
  36 #include <mach/atmel-mci.h>
  37 #include <linux/atmel-mci.h>
  38 #include <linux/atmel_pdc.h>
  39
  40 #include <asm/cacheflush.h>
  41 #include <asm/io.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "atmel-mci-regs.h"
  45
  46 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
  47 #define ATMCI_DMA_THRESHOLD     16
  48
  49 enum {
  50         EVENT_CMD_RDY = 0,
  51         EVENT_XFER_COMPLETE,
  52         EVENT_NOTBUSY,
  53         EVENT_DATA_ERROR,
  54 };
  55
  56 enum atmel_mci_state {
  57         STATE_IDLE = 0,
  58         STATE_SENDING_CMD,
  59         STATE_DATA_XFER,
  60         STATE_WAITING_NOTBUSY,
  61         STATE_SENDING_STOP,
  62         STATE_END_REQUEST,
  63 };
  64
  65 enum atmci_xfer_dir {
  66         XFER_RECEIVE = 0,
  67         XFER_TRANSMIT,
  68 };
  69
  70 enum atmci_pdc_buf {
  71         PDC_FIRST_BUF = 0,
  72         PDC_SECOND_BUF,
  73 };
  74
  75 struct atmel_mci_caps {
  76         bool    has_dma_conf_reg;
  77         bool    has_pdc;
  78         bool    has_cfg_reg;
  79         bool    has_cstor_reg;
  80         bool    has_highspeed;
  81         bool    has_rwproof;
  82         bool    has_odd_clk_div;
  83         bool    has_bad_data_ordering;
  84         bool    need_reset_after_xfer;
  85         bool    need_blksz_mul_4;
  86         bool    need_notbusy_for_read_ops;
  87 };
  88
  89 struct atmel_mci_dma {
  90         struct dma_chan                 *chan;
  91         struct dma_async_tx_descriptor  *data_desc;
  92 };
  93
  94 /**
  95  * struct atmel_mci - MMC controller state shared between all slots
  96  * @lock: Spinlock protecting the queue and associated data.
  97  * @regs: Pointer to MMIO registers.
  98  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
  99  * @pio_offset: Offset into the current scatterlist entry.
 100  * @buffer: Buffer used if we don't have the r/w proof capability. We
 101  *      don't have the time to switch pdc buffers so we have to use only
 102  *      one buffer for the full transaction.
 103  * @buf_size: size of the buffer.
 104  * @phys_buf_addr: buffer address needed for pdc.
 105  * @cur_slot: The slot which is currently using the controller.
 106  * @mrq: The request currently being processed on @cur_slot,
 107  *      or NULL if the controller is idle.
 108  * @cmd: The command currently being sent to the card, or NULL.
 109  * @data: The data currently being transferred, or NULL if no data
 110  *      transfer is in progress.
 111  * @data_size: just data->blocks * data->blksz.
 112  * @dma: DMA client state.
 113  * @data_chan: DMA channel being used for the current data transfer.
 114  * @cmd_status: Snapshot of SR taken upon completion of the current
 115  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
 116  * @data_status: Snapshot of SR taken upon completion of the current
 117  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
 118  *      EVENT_DATA_ERROR is pending.
 119  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 120  *      to be sent.
 121  * @tasklet: Tasklet running the request state machine.
 122  * @pending_events: Bitmask of events flagged by the interrupt handler
 123  *      to be processed by the tasklet.
 124  * @completed_events: Bitmask of events which the state machine has
 125  *      processed.
 126  * @state: Tasklet state.
 127  * @queue: List of slots waiting for access to the controller.
 128  * @need_clock_update: Update the clock rate before the next request.
 129  * @need_reset: Reset controller before next request.
 130  * @timer: Timer to balance the data timeout error flag which cannot rise.
 131  * @mode_reg: Value of the MR register.
 132  * @cfg_reg: Value of the CFG register.
 133  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 134  *      rate and timeout calculations.
 135  * @mapbase: Physical address of the MMIO registers.
 136  * @mck: The peripheral bus clock hooked up to the MMC controller.
 137  * @pdev: Platform device associated with the MMC controller.
 138  * @slot: Slots sharing this MMC controller.
 139  * @caps: MCI capabilities depending on MCI version.
 140  * @prepare_data: function to setup MCI before data transfer which
 141  * depends on MCI capabilities.
 142  * @submit_data: function to start data transfer which depends on MCI
 143  * capabilities.
 144  * @stop_transfer: function to stop data transfer which depends on MCI
 145  * capabilities.
 146  *
 147  * Locking
 148  * =======
 149  *
 150  * @lock is a softirq-safe spinlock protecting @queue as well as
 151  * @cur_slot, @mrq and @state. These must always be updated
 152  * at the same time while holding @lock.
 153  *
 154  * @lock also protects mode_reg and need_clock_update since these are
 155  * used to synchronize mode register updates with the queue
 156  * processing.
 157  *
 158  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 159  * and must always be written at the same time as the slot is added to
 160  * @queue.
 161  *
 162  * @pending_events and @completed_events are accessed using atomic bit
 163  * operations, so they don't need any locking.
 164  *
 165  * None of the fields touched by the interrupt handler need any
 166  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 167  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 168  * interrupts must be disabled and @data_status updated with a
 169  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 170  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 171  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 172  * bytes_xfered field of @data must be written. This is ensured by
 173  * using barriers.
 174  */
 175 struct atmel_mci {
 176         spinlock_t              lock;
 177         void __iomem            *regs;
 178
 179         struct scatterlist      *sg;
 180         unsigned int            sg_len;
 181         unsigned int            pio_offset;
 182         unsigned int            *buffer;
 183         unsigned int            buf_size;
 184         dma_addr_t              buf_phys_addr;
 185
 186         struct atmel_mci_slot   *cur_slot;
 187         struct mmc_request      *mrq;
 188         struct mmc_command      *cmd;
 189         struct mmc_data         *data;
 190         unsigned int            data_size;
 191
 192         struct atmel_mci_dma    dma;
 193         struct dma_chan         *data_chan;
 194         struct dma_slave_config dma_conf;
 195
 196         u32                     cmd_status;
 197         u32                     data_status;
 198         u32                     stop_cmdr;
 199
 200         struct tasklet_struct   tasklet;
 201         unsigned long           pending_events;
 202         unsigned long           completed_events;
 203         enum atmel_mci_state    state;
 204         struct list_head        queue;
 205
 206         bool                    need_clock_update;
 207         bool                    need_reset;
 208         struct timer_list       timer;
 209         u32                     mode_reg;
 210         u32                     cfg_reg;
 211         unsigned long           bus_hz;
 212         unsigned long           mapbase;
 213         struct clk              *mck;
 214         struct platform_device  *pdev;
 215
 216         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
 217
 218         struct atmel_mci_caps   caps;
 219
 220         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 221         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 222         void (*stop_transfer)(struct atmel_mci *host);
 223 };
 224
 225 /**
 226  * struct atmel_mci_slot - MMC slot state
 227  * @mmc: The mmc_host representing this slot.
 228  * @host: The MMC controller this slot is using.
 229  * @sdc_reg: Value of SDCR to be written before using this slot.
 230  * @sdio_irq: SDIO irq mask for this slot.
 231  * @mrq: mmc_request currently being processed or waiting to be
 232  *      processed, or NULL when the slot is idle.
 233  * @queue_node: List node for placing this node in the @queue list of
 234  *      &struct atmel_mci.
 235  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 236  * @flags: Random state bits associated with the slot.
 237  * @detect_pin: GPIO pin used for card detection, or negative if not
 238  *      available.
 239  * @wp_pin: GPIO pin used for card write protect sending, or negative
 240  *      if not available.
 241  * @detect_is_active_high: The state of the detect pin when it is active.
 242  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 243  */
 244 struct atmel_mci_slot {
 245         struct mmc_host         *mmc;
 246         struct atmel_mci        *host;
 247
 248         u32                     sdc_reg;
 249         u32                     sdio_irq;
 250
 251         struct mmc_request      *mrq;
 252         struct list_head        queue_node;
 253
 254         unsigned int            clock;
 255         unsigned long           flags;
 256 #define ATMCI_CARD_PRESENT      0
 257 #define ATMCI_CARD_NEED_INIT    1
 258 #define ATMCI_SHUTDOWN          2
 259
 260         int                     detect_pin;
 261         int                     wp_pin;
 262         bool                    detect_is_active_high;
 263
 264         struct timer_list       detect_timer;
 265 };
 266
 267 #define atmci_test_and_clear_pending(host, event)               \
 268         test_and_clear_bit(event, &host->pending_events)
 269 #define atmci_set_completed(host, event)                        \
 270         set_bit(event, &host->completed_events)
 271 #define atmci_set_pending(host, event)                          \
 272         set_bit(event, &host->pending_events)
 273
 274 /*
 275  * The debugfs stuff below is mostly optimized away when
 276  * CONFIG_DEBUG_FS is not set.
 277  */
 278 static int atmci_req_show(struct seq_file *s, void *v)
 279 {
 280         struct atmel_mci_slot   *slot = s->private;
 281         struct mmc_request      *mrq;
 282         struct mmc_command      *cmd;
 283         struct mmc_command      *stop;
 284         struct mmc_data         *data;
 285
 286         /* Make sure we get a consistent snapshot */
 287         spin_lock_bh(&slot->host->lock);
 288         mrq = slot->mrq;
 289
 290         if (mrq) {
 291                 cmd = mrq->cmd;
 292                 data = mrq->data;
 293                 stop = mrq->stop;
 294
 295                 if (cmd)
 296                         seq_printf(s,
 297                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 298                                 cmd->opcode, cmd->arg, cmd->flags,
 299                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
 300                                 cmd->resp[3], cmd->error);
 301                 if (data)
 302                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 303                                 data->bytes_xfered, data->blocks,
 304                                 data->blksz, data->flags, data->error);
 305                 if (stop)
 306                         seq_printf(s,
 307                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 308                                 stop->opcode, stop->arg, stop->flags,
 309                                 stop->resp[0], stop->resp[1], stop->resp[2],
 310                                 stop->resp[3], stop->error);
 311         }
 312
 313         spin_unlock_bh(&slot->host->lock);
 314
 315         return 0;
 316 }
 317
 318 static int atmci_req_open(struct inode *inode, struct file *file)
 319 {
 320         return single_open(file, atmci_req_show, inode->i_private);
 321 }
 322
 323 static const struct file_operations atmci_req_fops = {
 324         .owner          = THIS_MODULE,
 325         .open           = atmci_req_open,
 326         .read           = seq_read,
 327         .llseek         = seq_lseek,
 328         .release        = single_release,
 329 };
 330
 331 static void atmci_show_status_reg(struct seq_file *s,
 332                 const char *regname, u32 value)
 333 {
 334         static const char       *sr_bit[] = {
 335                 [0]     = "CMDRDY",
 336                 [1]     = "RXRDY",
 337                 [2]     = "TXRDY",
 338                 [3]     = "BLKE",
 339                 [4]     = "DTIP",
 340                 [5]     = "NOTBUSY",
 341                 [6]     = "ENDRX",
 342                 [7]     = "ENDTX",
 343                 [8]     = "SDIOIRQA",
 344                 [9]     = "SDIOIRQB",
 345                 [12]    = "SDIOWAIT",
 346                 [14]    = "RXBUFF",
 347                 [15]    = "TXBUFE",
 348                 [16]    = "RINDE",
 349                 [17]    = "RDIRE",
 350                 [18]    = "RCRCE",
 351                 [19]    = "RENDE",
 352                 [20]    = "RTOE",
 353                 [21]    = "DCRCE",
 354                 [22]    = "DTOE",
 355                 [23]    = "CSTOE",
 356                 [24]    = "BLKOVRE",
 357                 [25]    = "DMADONE",
 358                 [26]    = "FIFOEMPTY",
 359                 [27]    = "XFRDONE",
 360                 [30]    = "OVRE",
 361                 [31]    = "UNRE",
 362         };
 363         unsigned int            i;
 364
 365         seq_printf(s, "%s:\t0x%08x", regname, value);
 366         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 367                 if (value & (1 << i)) {
 368                         if (sr_bit[i])
 369                                 seq_printf(s, " %s", sr_bit[i]);
 370                         else
 371                                 seq_puts(s, " UNKNOWN");
 372                 }
 373         }
 374         seq_putc(s, '\n');
 375 }
 376
 377 static int atmci_regs_show(struct seq_file *s, void *v)
 378 {
 379         struct atmel_mci        *host = s->private;
 380         u32                     *buf;
 381         int                     ret = 0;
 382
 383
 384         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 385         if (!buf)
 386                 return -ENOMEM;
 387
 388         /*
 389          * Grab a more or less consistent snapshot. Note that we're
 390          * not disabling interrupts, so IMR and SR may not be
 391          * consistent.
 392          */
 393         ret = clk_prepare_enable(host->mck);
 394         if (ret)
 395                 goto out;
 396
 397         spin_lock_bh(&host->lock);
 398         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 399         spin_unlock_bh(&host->lock);
 400
 401         clk_disable_unprepare(host->mck);
 402
 403         seq_printf(s, "MR:\t0x%08x%s%s ",
 404                         buf[ATMCI_MR / 4],
 405                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 406                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 407         if (host->caps.has_odd_clk_div)
 408                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 409                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
 410                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
 411         else
 412                 seq_printf(s, "CLKDIV=%u\n",
 413                                 (buf[ATMCI_MR / 4] & 0xff));
 414         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 415         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 416         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 417         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 418                         buf[ATMCI_BLKR / 4],
 419                         buf[ATMCI_BLKR / 4] & 0xffff,
 420                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 421         if (host->caps.has_cstor_reg)
 422                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 423
 424         /* Don't read RSPR and RDR; it will consume the data there */
 425
 426         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 427         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 428
 429         if (host->caps.has_dma_conf_reg) {
 430                 u32 val;
 431
 432                 val = buf[ATMCI_DMA / 4];
 433                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 434                                 val, val & 3,
 435                                 ((val >> 4) & 3) ?
 436                                         1 << (((val >> 4) & 3) + 1) : 1,
 437                                 val & ATMCI_DMAEN ? " DMAEN" : "");
 438         }
 439         if (host->caps.has_cfg_reg) {
 440                 u32 val;
 441
 442                 val = buf[ATMCI_CFG / 4];
 443                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 444                                 val,
 445                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 446                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 447                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 448                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 449         }
 450
 451 out:
 452         kfree(buf);
 453
 454         return ret;
 455 }
 456
 457 static int atmci_regs_open(struct inode *inode, struct file *file)
 458 {
 459         return single_open(file, atmci_regs_show, inode->i_private);
 460 }
 461
 462 static const struct file_operations atmci_regs_fops = {
 463         .owner          = THIS_MODULE,
 464         .open           = atmci_regs_open,
 465         .read           = seq_read,
 466         .llseek         = seq_lseek,
 467         .release        = single_release,
 468 };
 469
 470 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 471 {
 472         struct mmc_host         *mmc = slot->mmc;
 473         struct atmel_mci        *host = slot->host;
 474         struct dentry           *root;
 475         struct dentry           *node;
 476
 477         root = mmc->debugfs_root;
 478         if (!root)
 479                 return;
 480
 481         node = debugfs_create_file("regs", S_IRUSR, root, host,
 482                         &atmci_regs_fops);
 483         if (IS_ERR(node))
 484                 return;
 485         if (!node)
 486                 goto err;
 487
 488         node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
 489         if (!node)
 490                 goto err;
 491
 492         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 493         if (!node)
 494                 goto err;
 495
 496         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 497                                      (u32 *)&host->pending_events);
 498         if (!node)
 499                 goto err;
 500
 501         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 502                                      (u32 *)&host->completed_events);
 503         if (!node)
 504                 goto err;
 505
 506         return;
 507
 508 err:
 509         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 510 }
 511
 512 #if defined(CONFIG_OF)
 513 static const struct of_device_id atmci_dt_ids[] = {
 514         { .compatible = "atmel,hsmci" },
 515         { /* sentinel */ }
 516 };
 517
 518 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
 519
 520 static struct mci_platform_data*
 521 atmci_of_init(struct platform_device *pdev)
 522 {
 523         struct device_node *np = pdev->dev.of_node;
 524         struct device_node *cnp;
 525         struct mci_platform_data *pdata;
 526         u32 slot_id;
 527
 528         if (!np) {
 529                 dev_err(&pdev->dev, "device node not found\n");
 530                 return ERR_PTR(-EINVAL);
 531         }
 532
 533         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 534         if (!pdata) {
 535                 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
 536                 return ERR_PTR(-ENOMEM);
 537         }
 538
 539         for_each_child_of_node(np, cnp) {
 540                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
 541                         dev_warn(&pdev->dev, "reg property is missing for %s\n",
 542                                  cnp->full_name);
 543                         continue;
 544                 }
 545
 546                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
 547                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
 548                                  ATMCI_MAX_NR_SLOTS);
 549                         break;
 550                 }
 551
 552                 if (of_property_read_u32(cnp, "bus-width",
 553                                          &pdata->slot[slot_id].bus_width))
 554                         pdata->slot[slot_id].bus_width = 1;
 555
 556                 pdata->slot[slot_id].detect_pin =
 557                         of_get_named_gpio(cnp, "cd-gpios", 0);
 558
 559                 pdata->slot[slot_id].detect_is_active_high =
 560                         of_property_read_bool(cnp, "cd-inverted");
 561
 562                 pdata->slot[slot_id].wp_pin =
 563                         of_get_named_gpio(cnp, "wp-gpios", 0);
 564         }
 565
 566         return pdata;
 567 }
 568 #else /* CONFIG_OF */
 569 static inline struct mci_platform_data*
 570 atmci_of_init(struct platform_device *dev)
 571 {
 572         return ERR_PTR(-EINVAL);
 573 }
 574 #endif
 575
 576 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 577 {
 578         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 579 }
 580
 581 static void atmci_timeout_timer(unsigned long data)
 582 {
 583         struct atmel_mci *host;
 584
 585         host = (struct atmel_mci *)data;
 586
 587         dev_dbg(&host->pdev->dev, "software timeout\n");
 588
 589         if (host->mrq->cmd->data) {
 590                 host->mrq->cmd->data->error = -ETIMEDOUT;
 591                 host->data = NULL;
 592                 /*
 593                  * With some SDIO modules, sometimes DMA transfer hangs. If
 594                  * stop_transfer() is not called then the DMA request is not
 595                  * removed, following ones are queued and never computed.
 596                  */
 597                 if (host->state == STATE_DATA_XFER)
 598                         host->stop_transfer(host);
 599         } else {
 600                 host->mrq->cmd->error = -ETIMEDOUT;
 601                 host->cmd = NULL;
 602         }
 603         host->need_reset = 1;
 604         host->state = STATE_END_REQUEST;
 605         smp_wmb();
 606         tasklet_schedule(&host->tasklet);
 607 }
 608
 609 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 610                                         unsigned int ns)
 611 {
 612         /*
 613          * It is easier here to use us instead of ns for the timeout,
 614          * it prevents from overflows during calculation.
 615          */
 616         unsigned int us = DIV_ROUND_UP(ns, 1000);
 617
 618         /* Maximum clock frequency is host->bus_hz/2 */
 619         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 620 }
 621
 622 static void atmci_set_timeout(struct atmel_mci *host,
 623                 struct atmel_mci_slot *slot, struct mmc_data *data)
 624 {
 625         static unsigned dtomul_to_shift[] = {
 626                 0, 4, 7, 8, 10, 12, 16, 20
 627         };
 628         unsigned        timeout;
 629         unsigned        dtocyc;
 630         unsigned        dtomul;
 631
 632         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 633                 + data->timeout_clks;
 634
 635         for (dtomul = 0; dtomul < 8; dtomul++) {
 636                 unsigned shift = dtomul_to_shift[dtomul];
 637                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
 638                 if (dtocyc < 15)
 639                         break;
 640         }
 641
 642         if (dtomul >= 8) {
 643                 dtomul = 7;
 644                 dtocyc = 15;
 645         }
 646
 647         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 648                         dtocyc << dtomul_to_shift[dtomul]);
 649         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 650 }
 651
 652 /*
 653  * Return mask with command flags to be enabled for this command.
 654  */
 655 static u32 atmci_prepare_command(struct mmc_host *mmc,
 656                                  struct mmc_command *cmd)
 657 {
 658         struct mmc_data *data;
 659         u32             cmdr;
 660
 661         cmd->error = -EINPROGRESS;
 662
 663         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 664
 665         if (cmd->flags & MMC_RSP_PRESENT) {
 666                 if (cmd->flags & MMC_RSP_136)
 667                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 668                 else
 669                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 670         }
 671
 672         /*
 673          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 674          * it's too difficult to determine whether this is an ACMD or
 675          * not. Better make it 64.
 676          */
 677         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 678
 679         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 680                 cmdr |= ATMCI_CMDR_OPDCMD;
 681
 682         data = cmd->data;
 683         if (data) {
 684                 cmdr |= ATMCI_CMDR_START_XFER;
 685
 686                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
 687                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 688                 } else {
 689                         if (data->flags & MMC_DATA_STREAM)
 690                                 cmdr |= ATMCI_CMDR_STREAM;
 691                         else if (data->blocks > 1)
 692                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 693                         else
 694                                 cmdr |= ATMCI_CMDR_BLOCK;
 695                 }
 696
 697                 if (data->flags & MMC_DATA_READ)
 698                         cmdr |= ATMCI_CMDR_TRDIR_READ;
 699         }
 700
 701         return cmdr;
 702 }
 703
 704 static void atmci_send_command(struct atmel_mci *host,
 705                 struct mmc_command *cmd, u32 cmd_flags)
 706 {
 707         WARN_ON(host->cmd);
 708         host->cmd = cmd;
 709
 710         dev_vdbg(&host->pdev->dev,
 711                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
 712                         cmd->arg, cmd_flags);
 713
 714         atmci_writel(host, ATMCI_ARGR, cmd->arg);
 715         atmci_writel(host, ATMCI_CMDR, cmd_flags);
 716 }
 717
 718 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 719 {
 720         dev_dbg(&host->pdev->dev, "send stop command\n");
 721         atmci_send_command(host, data->stop, host->stop_cmdr);
 722         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 723 }
 724
 725 /*
 726  * Configure given PDC buffer taking care of alignement issues.
 727  * Update host->data_size and host->sg.
 728  */
 729 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 730         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 731 {
 732         u32 pointer_reg, counter_reg;
 733         unsigned int buf_size;
 734
 735         if (dir == XFER_RECEIVE) {
 736                 pointer_reg = ATMEL_PDC_RPR;
 737                 counter_reg = ATMEL_PDC_RCR;
 738         } else {
 739                 pointer_reg = ATMEL_PDC_TPR;
 740                 counter_reg = ATMEL_PDC_TCR;
 741         }
 742
 743         if (buf_nb == PDC_SECOND_BUF) {
 744                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 745                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 746         }
 747
 748         if (!host->caps.has_rwproof) {
 749                 buf_size = host->buf_size;
 750                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
 751         } else {
 752                 buf_size = sg_dma_len(host->sg);
 753                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 754         }
 755
 756         if (host->data_size <= buf_size) {
 757                 if (host->data_size & 0x3) {
 758                         /* If size is different from modulo 4, transfer bytes */
 759                         atmci_writel(host, counter_reg, host->data_size);
 760                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 761                 } else {
 762                         /* Else transfer 32-bits words */
 763                         atmci_writel(host, counter_reg, host->data_size / 4);
 764                 }
 765                 host->data_size = 0;
 766         } else {
 767                 /* We assume the size of a page is 32-bits aligned */
 768                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 769                 host->data_size -= sg_dma_len(host->sg);
 770                 if (host->data_size)
 771                         host->sg = sg_next(host->sg);
 772         }
 773 }
 774
 775 /*
 776  * Configure PDC buffer according to the data size ie configuring one or two
 777  * buffers. Don't use this function if you want to configure only the second
 778  * buffer. In this case, use atmci_pdc_set_single_buf.
 779  */
 780 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 781 {
 782         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 783         if (host->data_size)
 784                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 785 }
 786
 787 /*
 788  * Unmap sg lists, called when transfer is finished.
 789  */
 790 static void atmci_pdc_cleanup(struct atmel_mci *host)
 791 {
 792         struct mmc_data         *data = host->data;
 793
 794         if (data)
 795                 dma_unmap_sg(&host->pdev->dev,
 796                                 data->sg, data->sg_len,
 797                                 ((data->flags & MMC_DATA_WRITE)
 798                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 799 }
 800
 801 /*
 802  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 803  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 804  * interrupt needed for both transfer directions.
 805  */
 806 static void atmci_pdc_complete(struct atmel_mci *host)
 807 {
 808         int transfer_size = host->data->blocks * host->data->blksz;
 809         int i;
 810
 811         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 812
 813         if ((!host->caps.has_rwproof)
 814             && (host->data->flags & MMC_DATA_READ)) {
 815                 if (host->caps.has_bad_data_ordering)
 816                         for (i = 0; i < transfer_size; i++)
 817                                 host->buffer[i] = swab32(host->buffer[i]);
 818                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 819                                     host->buffer, transfer_size);
 820         }
 821
 822         atmci_pdc_cleanup(host);
 823
 824         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
 825         atmci_set_pending(host, EVENT_XFER_COMPLETE);
 826         tasklet_schedule(&host->tasklet);
 827 }
 828
 829 static void atmci_dma_cleanup(struct atmel_mci *host)
 830 {
 831         struct mmc_data                 *data = host->data;
 832
 833         if (data)
 834                 dma_unmap_sg(host->dma.chan->device->dev,
 835                                 data->sg, data->sg_len,
 836                                 ((data->flags & MMC_DATA_WRITE)
 837                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 838 }
 839
 840 /*
 841  * This function is called by the DMA driver from tasklet context.
 842  */
 843 static void atmci_dma_complete(void *arg)
 844 {
 845         struct atmel_mci        *host = arg;
 846         struct mmc_data         *data = host->data;
 847
 848         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 849
 850         if (host->caps.has_dma_conf_reg)
 851                 /* Disable DMA hardware handshaking on MCI */
 852                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
 853
 854         atmci_dma_cleanup(host);
 855
 856         /*
 857          * If the card was removed, data will be NULL. No point trying
 858          * to send the stop command or waiting for NBUSY in this case.
 859          */
 860         if (data) {
 861                 dev_dbg(&host->pdev->dev,
 862                         "(%s) set pending xfer complete\n", __func__);
 863                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
 864                 tasklet_schedule(&host->tasklet);
 865
 866                 /*
 867                  * Regardless of what the documentation says, we have
 868                  * to wait for NOTBUSY even after block read
 869                  * operations.
 870                  *
 871                  * When the DMA transfer is complete, the controller
 872                  * may still be reading the CRC from the card, i.e.
 873                  * the data transfer is still in progress and we
 874                  * haven't seen all the potential error bits yet.
 875                  *
 876                  * The interrupt handler will schedule a different
 877                  * tasklet to finish things up when the data transfer
 878                  * is completely done.
 879                  *
 880                  * We may not complete the mmc request here anyway
 881                  * because the mmc layer may call back and cause us to
 882                  * violate the "don't submit new operations from the
 883                  * completion callback" rule of the dma engine
 884                  * framework.
 885                  */
 886                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
 887         }
 888 }
 889
 890 /*
 891  * Returns a mask of interrupt flags to be enabled after the whole
 892  * request has been prepared.
 893  */
 894 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
 895 {
 896         u32 iflags;
 897
 898         data->error = -EINPROGRESS;
 899
 900         host->sg = data->sg;
 901         host->sg_len = data->sg_len;
 902         host->data = data;
 903         host->data_chan = NULL;
 904
 905         iflags = ATMCI_DATA_ERROR_FLAGS;
 906
 907         /*
 908          * Errata: MMC data write operation with less than 12
 909          * bytes is impossible.
 910          *
 911          * Errata: MCI Transmit Data Register (TDR) FIFO
 912          * corruption when length is not multiple of 4.
 913          */
 914         if (data->blocks * data->blksz < 12
 915                         || (data->blocks * data->blksz) & 3)
 916                 host->need_reset = true;
 917
 918         host->pio_offset = 0;
 919         if (data->flags & MMC_DATA_READ)
 920                 iflags |= ATMCI_RXRDY;
 921         else
 922                 iflags |= ATMCI_TXRDY;
 923
 924         return iflags;
 925 }
 926
 927 /*
 928  * Set interrupt flags and set block length into the MCI mode register even
 929  * if this value is also accessible in the MCI block register. It seems to be
 930  * necessary before the High Speed MCI version. It also map sg and configure
 931  * PDC registers.
 932  */
 933 static u32
 934 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
 935 {
 936         u32 iflags, tmp;
 937         unsigned int sg_len;
 938         enum dma_data_direction dir;
 939         int i;
 940
 941         data->error = -EINPROGRESS;
 942
 943         host->data = data;
 944         host->sg = data->sg;
 945         iflags = ATMCI_DATA_ERROR_FLAGS;
 946
 947         /* Enable pdc mode */
 948         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
 949
 950         if (data->flags & MMC_DATA_READ) {
 951                 dir = DMA_FROM_DEVICE;
 952                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
 953         } else {
 954                 dir = DMA_TO_DEVICE;
 955                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
 956         }
 957
 958         /* Set BLKLEN */
 959         tmp = atmci_readl(host, ATMCI_MR);
 960         tmp &= 0x0000ffff;
 961         tmp |= ATMCI_BLKLEN(data->blksz);
 962         atmci_writel(host, ATMCI_MR, tmp);
 963
 964         /* Configure PDC */
 965         host->data_size = data->blocks * data->blksz;
 966         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
 967
 968         if ((!host->caps.has_rwproof)
 969             && (host->data->flags & MMC_DATA_WRITE)) {
 970                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
 971                                   host->buffer, host->data_size);
 972                 if (host->caps.has_bad_data_ordering)
 973                         for (i = 0; i < host->data_size; i++)
 974                                 host->buffer[i] = swab32(host->buffer[i]);
 975         }
 976
 977         if (host->data_size)
 978                 atmci_pdc_set_both_buf(host,
 979                         ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
 980
 981         return iflags;
 982 }
 983
 984 static u32
 985 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
 986 {
 987         struct dma_chan                 *chan;
 988         struct dma_async_tx_descriptor  *desc;
 989         struct scatterlist              *sg;
 990         unsigned int                    i;
 991         enum dma_data_direction         direction;
 992         enum dma_transfer_direction     slave_dirn;
 993         unsigned int                    sglen;
 994         u32                             maxburst;
 995         u32 iflags;
 996
 997         data->error = -EINPROGRESS;
 998
 999         WARN_ON(host->data);
1000         host->sg = NULL;
1001         host->data = data;
1002
1003         iflags = ATMCI_DATA_ERROR_FLAGS;
1004
1005         /*
1006          * We don't do DMA on "complex" transfers, i.e. with
1007          * non-word-aligned buffers or lengths. Also, we don't bother
1008          * with all the DMA setup overhead for short transfers.
1009          */
1010         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1011                 return atmci_prepare_data(host, data);
1012         if (data->blksz & 3)
1013                 return atmci_prepare_data(host, data);
1014
1015         for_each_sg(data->sg, sg, data->sg_len, i) {
1016                 if (sg->offset & 3 || sg->length & 3)
1017                         return atmci_prepare_data(host, data);
1018         }
1019
1020         /* If we don't have a channel, we can't do DMA */
1021         chan = host->dma.chan;
1022         if (chan)
1023                 host->data_chan = chan;
1024
1025         if (!chan)
1026                 return -ENODEV;
1027
1028         if (data->flags & MMC_DATA_READ) {
1029                 direction = DMA_FROM_DEVICE;
1030                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1031                 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1032         } else {
1033                 direction = DMA_TO_DEVICE;
1034                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1035                 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1036         }
1037
1038         if (host->caps.has_dma_conf_reg)
1039                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1040                         ATMCI_DMAEN);
1041
1042         sglen = dma_map_sg(chan->device->dev, data->sg,
1043                         data->sg_len, direction);
1044
1045         dmaengine_slave_config(chan, &host->dma_conf);
1046         desc = dmaengine_prep_slave_sg(chan,
1047                         data->sg, sglen, slave_dirn,
1048                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049         if (!desc)
1050                 goto unmap_exit;
1051
1052         host->dma.data_desc = desc;
1053         desc->callback = atmci_dma_complete;
1054         desc->callback_param = host;
1055
1056         return iflags;
1057 unmap_exit:
1058         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1059         return -ENOMEM;
1060 }
1061
1062 static void
1063 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1064 {
1065         return;
1066 }
1067
1068 /*
1069  * Start PDC according to transfer direction.
1070  */
1071 static void
1072 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1073 {
1074         if (data->flags & MMC_DATA_READ)
1075                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1076         else
1077                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1078 }
1079
1080 static void
1081 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1082 {
1083         struct dma_chan                 *chan = host->data_chan;
1084         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1085
1086         if (chan) {
1087                 dmaengine_submit(desc);
1088                 dma_async_issue_pending(chan);
1089         }
1090 }
1091
1092 static void atmci_stop_transfer(struct atmel_mci *host)
1093 {
1094         dev_dbg(&host->pdev->dev,
1095                 "(%s) set pending xfer complete\n", __func__);
1096         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1097         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1098 }
1099
1100 /*
1101  * Stop data transfer because error(s) occurred.
1102  */
1103 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1104 {
1105         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1106 }
1107
1108 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1109 {
1110         struct dma_chan *chan = host->data_chan;
1111
1112         if (chan) {
1113                 dmaengine_terminate_all(chan);
1114                 atmci_dma_cleanup(host);
1115         } else {
1116                 /* Data transfer was stopped by the interrupt handler */
1117                 dev_dbg(&host->pdev->dev,
1118                         "(%s) set pending xfer complete\n", __func__);
1119                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1120                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1121         }
1122 }
1123
1124 /*
1125  * Start a request: prepare data if needed, prepare the command and activate
1126  * interrupts.
1127  */
1128 static void atmci_start_request(struct atmel_mci *host,
1129                 struct atmel_mci_slot *slot)
1130 {
1131         struct mmc_request      *mrq;
1132         struct mmc_command      *cmd;
1133         struct mmc_data         *data;
1134         u32                     iflags;
1135         u32                     cmdflags;
1136
1137         mrq = slot->mrq;
1138         host->cur_slot = slot;
1139         host->mrq = mrq;
1140
1141         host->pending_events = 0;
1142         host->completed_events = 0;
1143         host->cmd_status = 0;
1144         host->data_status = 0;
1145
1146         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1147
1148         if (host->need_reset || host->caps.need_reset_after_xfer) {
1149                 iflags = atmci_readl(host, ATMCI_IMR);
1150                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1151                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1152                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1153                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1154                 if (host->caps.has_cfg_reg)
1155                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1156                 atmci_writel(host, ATMCI_IER, iflags);
1157                 host->need_reset = false;
1158         }
1159         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1160
1161         iflags = atmci_readl(host, ATMCI_IMR);
1162         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1163                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1164                                 iflags);
1165
1166         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1167                 /* Send init sequence (74 clock cycles) */
1168                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1169                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1170                         cpu_relax();
1171         }
1172         iflags = 0;
1173         data = mrq->data;
1174         if (data) {
1175                 atmci_set_timeout(host, slot, data);
1176
1177                 /* Must set block count/size before sending command */
1178                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1179                                 | ATMCI_BLKLEN(data->blksz));
1180                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1181                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1182
1183                 iflags |= host->prepare_data(host, data);
1184         }
1185
1186         iflags |= ATMCI_CMDRDY;
1187         cmd = mrq->cmd;
1188         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1189
1190         /*
1191          * DMA transfer should be started before sending the command to avoid
1192          * unexpected errors especially for read operations in SDIO mode.
1193          * Unfortunately, in PDC mode, command has to be sent before starting
1194          * the transfer.
1195          */
1196         if (host->submit_data != &atmci_submit_data_dma)
1197                 atmci_send_command(host, cmd, cmdflags);
1198
1199         if (data)
1200                 host->submit_data(host, data);
1201
1202         if (host->submit_data == &atmci_submit_data_dma)
1203                 atmci_send_command(host, cmd, cmdflags);
1204
1205         if (mrq->stop) {
1206                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1207                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1208                 if (!(data->flags & MMC_DATA_WRITE))
1209                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1210                 if (data->flags & MMC_DATA_STREAM)
1211                         host->stop_cmdr |= ATMCI_CMDR_STREAM;
1212                 else
1213                         host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1214         }
1215
1216         /*
1217          * We could have enabled interrupts earlier, but I suspect
1218          * that would open up a nice can of interesting race
1219          * conditions (e.g. command and data complete, but stop not
1220          * prepared yet.)
1221          */
1222         atmci_writel(host, ATMCI_IER, iflags);
1223
1224         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1225 }
1226
1227 static void atmci_queue_request(struct atmel_mci *host,
1228                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1229 {
1230         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1231                         host->state);
1232
1233         spin_lock_bh(&host->lock);
1234         slot->mrq = mrq;
1235         if (host->state == STATE_IDLE) {
1236                 host->state = STATE_SENDING_CMD;
1237                 atmci_start_request(host, slot);
1238         } else {
1239                 dev_dbg(&host->pdev->dev, "queue request\n");
1240                 list_add_tail(&slot->queue_node, &host->queue);
1241         }
1242         spin_unlock_bh(&host->lock);
1243 }
1244
1245 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1246 {
1247         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1248         struct atmel_mci        *host = slot->host;
1249         struct mmc_data         *data;
1250
1251         WARN_ON(slot->mrq);
1252         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1253
1254         /*
1255          * We may "know" the card is gone even though there's still an
1256          * electrical connection. If so, we really need to communicate
1257          * this to the MMC core since there won't be any more
1258          * interrupts as the card is completely removed. Otherwise,
1259          * the MMC core might believe the card is still there even
1260          * though the card was just removed very slowly.
1261          */
1262         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1263                 mrq->cmd->error = -ENOMEDIUM;
1264                 mmc_request_done(mmc, mrq);
1265                 return;
1266         }
1267
1268         /* We don't support multiple blocks of weird lengths. */
1269         data = mrq->data;
1270         if (data && data->blocks > 1 && data->blksz & 3) {
1271                 mrq->cmd->error = -EINVAL;
1272                 mmc_request_done(mmc, mrq);
1273         }
1274
1275         atmci_queue_request(host, slot, mrq);
1276 }
1277
1278 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1279 {
1280         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1281         struct atmel_mci        *host = slot->host;
1282         unsigned int            i;
1283         bool                    unprepare_clk;
1284
1285         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1286         switch (ios->bus_width) {
1287         case MMC_BUS_WIDTH_1:
1288                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1289                 break;
1290         case MMC_BUS_WIDTH_4:
1291                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1292                 break;
1293         }
1294
1295         if (ios->clock) {
1296                 unsigned int clock_min = ~0U;
1297                 u32 clkdiv;
1298
1299                 clk_prepare(host->mck);
1300                 unprepare_clk = true;
1301
1302                 spin_lock_bh(&host->lock);
1303                 if (!host->mode_reg) {
1304                         clk_enable(host->mck);
1305                         unprepare_clk = false;
1306                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1307                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1308                         if (host->caps.has_cfg_reg)
1309                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1310                 }
1311
1312                 /*
1313                  * Use mirror of ios->clock to prevent race with mmc
1314                  * core ios update when finding the minimum.
1315                  */
1316                 slot->clock = ios->clock;
1317                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1318                         if (host->slot[i] && host->slot[i]->clock
1319                                         && host->slot[i]->clock < clock_min)
1320                                 clock_min = host->slot[i]->clock;
1321                 }
1322
1323                 /* Calculate clock divider */
1324                 if (host->caps.has_odd_clk_div) {
1325                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1326                         if (clkdiv > 511) {
1327                                 dev_warn(&mmc->class_dev,
1328                                          "clock %u too slow; using %lu\n",
1329                                          clock_min, host->bus_hz / (511 + 2));
1330                                 clkdiv = 511;
1331                         }
1332                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1333                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1334                 } else {
1335                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1336                         if (clkdiv > 255) {
1337                                 dev_warn(&mmc->class_dev,
1338                                          "clock %u too slow; using %lu\n",
1339                                          clock_min, host->bus_hz / (2 * 256));
1340                                 clkdiv = 255;
1341                         }
1342                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1343                 }
1344
1345                 /*
1346                  * WRPROOF and RDPROOF prevent overruns/underruns by
1347                  * stopping the clock when the FIFO is full/empty.
1348                  * This state is not expected to last for long.
1349                  */
1350                 if (host->caps.has_rwproof)
1351                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1352
1353                 if (host->caps.has_cfg_reg) {
1354                         /* setup High Speed mode in relation with card capacity */
1355                         if (ios->timing == MMC_TIMING_SD_HS)
1356                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1357                         else
1358                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1359                 }
1360
1361                 if (list_empty(&host->queue)) {
1362                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1363                         if (host->caps.has_cfg_reg)
1364                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1365                 } else {
1366                         host->need_clock_update = true;
1367                 }
1368
1369                 spin_unlock_bh(&host->lock);
1370         } else {
1371                 bool any_slot_active = false;
1372
1373                 unprepare_clk = false;
1374
1375                 spin_lock_bh(&host->lock);
1376                 slot->clock = 0;
1377                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1378                         if (host->slot[i] && host->slot[i]->clock) {
1379                                 any_slot_active = true;
1380                                 break;
1381                         }
1382                 }
1383                 if (!any_slot_active) {
1384                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1385                         if (host->mode_reg) {
1386                                 atmci_readl(host, ATMCI_MR);
1387                                 clk_disable(host->mck);
1388                                 unprepare_clk = true;
1389                         }
1390                         host->mode_reg = 0;
1391                 }
1392                 spin_unlock_bh(&host->lock);
1393         }
1394
1395         if (unprepare_clk)
1396                 clk_unprepare(host->mck);
1397
1398         switch (ios->power_mode) {
1399         case MMC_POWER_OFF:
1400                 if (!IS_ERR(mmc->supply.vmmc))
1401                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1402                 break;
1403         case MMC_POWER_UP:
1404                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1405                 if (!IS_ERR(mmc->supply.vmmc))
1406                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1407                 break;
1408         default:
1409                 /*
1410                  * TODO: None of the currently available AVR32-based
1411                  * boards allow MMC power to be turned off. Implement
1412                  * power control when this can be tested properly.
1413                  *
1414                  * We also need to hook this into the clock management
1415                  * somehow so that newly inserted cards aren't
1416                  * subjected to a fast clock before we have a chance
1417                  * to figure out what the maximum rate is. Currently,
1418                  * there's no way to avoid this, and there never will
1419                  * be for boards that don't support power control.
1420                  */
1421                 break;
1422         }
1423 }
1424
1425 static int atmci_get_ro(struct mmc_host *mmc)
1426 {
1427         int                     read_only = -ENOSYS;
1428         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1429
1430         if (gpio_is_valid(slot->wp_pin)) {
1431                 read_only = gpio_get_value(slot->wp_pin);
1432                 dev_dbg(&mmc->class_dev, "card is %s\n",
1433                                 read_only ? "read-only" : "read-write");
1434         }
1435
1436         return read_only;
1437 }
1438
1439 static int atmci_get_cd(struct mmc_host *mmc)
1440 {
1441         int                     present = -ENOSYS;
1442         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1443
1444         if (gpio_is_valid(slot->detect_pin)) {
1445                 present = !(gpio_get_value(slot->detect_pin) ^
1446                             slot->detect_is_active_high);
1447                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1448                                 present ? "" : "not ");
1449         }
1450
1451         return present;
1452 }
1453
1454 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1455 {
1456         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1457         struct atmel_mci        *host = slot->host;
1458
1459         if (enable)
1460                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1461         else
1462                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1463 }
1464
1465 static const struct mmc_host_ops atmci_ops = {
1466         .request        = atmci_request,
1467         .set_ios        = atmci_set_ios,
1468         .get_ro         = atmci_get_ro,
1469         .get_cd         = atmci_get_cd,
1470         .enable_sdio_irq = atmci_enable_sdio_irq,
1471 };
1472
1473 /* Called with host->lock held */
1474 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1475         __releases(&host->lock)
1476         __acquires(&host->lock)
1477 {
1478         struct atmel_mci_slot   *slot = NULL;
1479         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1480
1481         WARN_ON(host->cmd || host->data);
1482
1483         /*
1484          * Update the MMC clock rate if necessary. This may be
1485          * necessary if set_ios() is called when a different slot is
1486          * busy transferring data.
1487          */
1488         if (host->need_clock_update) {
1489                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1490                 if (host->caps.has_cfg_reg)
1491                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1492         }
1493
1494         host->cur_slot->mrq = NULL;
1495         host->mrq = NULL;
1496         if (!list_empty(&host->queue)) {
1497                 slot = list_entry(host->queue.next,
1498                                 struct atmel_mci_slot, queue_node);
1499                 list_del(&slot->queue_node);
1500                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1501                                 mmc_hostname(slot->mmc));
1502                 host->state = STATE_SENDING_CMD;
1503                 atmci_start_request(host, slot);
1504         } else {
1505                 dev_vdbg(&host->pdev->dev, "list empty\n");
1506                 host->state = STATE_IDLE;
1507         }
1508
1509         del_timer(&host->timer);
1510
1511         spin_unlock(&host->lock);
1512         mmc_request_done(prev_mmc, mrq);
1513         spin_lock(&host->lock);
1514 }
1515
1516 static void atmci_command_complete(struct atmel_mci *host,
1517                         struct mmc_command *cmd)
1518 {
1519         u32             status = host->cmd_status;
1520
1521         /* Read the response from the card (up to 16 bytes) */
1522         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1523         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1524         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1525         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1526
1527         if (status & ATMCI_RTOE)
1528                 cmd->error = -ETIMEDOUT;
1529         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1530                 cmd->error = -EILSEQ;
1531         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1532                 cmd->error = -EIO;
1533         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1534                 if (host->caps.need_blksz_mul_4) {
1535                         cmd->error = -EINVAL;
1536                         host->need_reset = 1;
1537                 }
1538         } else
1539                 cmd->error = 0;
1540 }
1541
1542 static void atmci_detect_change(unsigned long data)
1543 {
1544         struct atmel_mci_slot   *slot = (struct atmel_mci_slot *)data;
1545         bool                    present;
1546         bool                    present_old;
1547
1548         /*
1549          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1550          * freeing the interrupt. We must not re-enable the interrupt
1551          * if it has been freed, and if we're shutting down, it
1552          * doesn't really matter whether the card is present or not.
1553          */
1554         smp_rmb();
1555         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1556                 return;
1557
1558         enable_irq(gpio_to_irq(slot->detect_pin));
1559         present = !(gpio_get_value(slot->detect_pin) ^
1560                     slot->detect_is_active_high);
1561         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1562
1563         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1564                         present, present_old);
1565
1566         if (present != present_old) {
1567                 struct atmel_mci        *host = slot->host;
1568                 struct mmc_request      *mrq;
1569
1570                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1571                         present ? "inserted" : "removed");
1572
1573                 spin_lock(&host->lock);
1574
1575                 if (!present)
1576                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1577                 else
1578                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1579
1580                 /* Clean up queue if present */
1581                 mrq = slot->mrq;
1582                 if (mrq) {
1583                         if (mrq == host->mrq) {
1584                                 /*
1585                                  * Reset controller to terminate any ongoing
1586                                  * commands or data transfers.
1587                                  */
1588                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1589                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1590                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1591                                 if (host->caps.has_cfg_reg)
1592                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1593
1594                                 host->data = NULL;
1595                                 host->cmd = NULL;
1596
1597                                 switch (host->state) {
1598                                 case STATE_IDLE:
1599                                         break;
1600                                 case STATE_SENDING_CMD:
1601                                         mrq->cmd->error = -ENOMEDIUM;
1602                                         if (mrq->data)
1603                                                 host->stop_transfer(host);
1604                                         break;
1605                                 case STATE_DATA_XFER:
1606                                         mrq->data->error = -ENOMEDIUM;
1607                                         host->stop_transfer(host);
1608                                         break;
1609                                 case STATE_WAITING_NOTBUSY:
1610                                         mrq->data->error = -ENOMEDIUM;
1611                                         break;
1612                                 case STATE_SENDING_STOP:
1613                                         mrq->stop->error = -ENOMEDIUM;
1614                                         break;
1615                                 case STATE_END_REQUEST:
1616                                         break;
1617                                 }
1618
1619                                 atmci_request_end(host, mrq);
1620                         } else {
1621                                 list_del(&slot->queue_node);
1622                                 mrq->cmd->error = -ENOMEDIUM;
1623                                 if (mrq->data)
1624                                         mrq->data->error = -ENOMEDIUM;
1625                                 if (mrq->stop)
1626                                         mrq->stop->error = -ENOMEDIUM;
1627
1628                                 spin_unlock(&host->lock);
1629                                 mmc_request_done(slot->mmc, mrq);
1630                                 spin_lock(&host->lock);
1631                         }
1632                 }
1633                 spin_unlock(&host->lock);
1634
1635                 mmc_detect_change(slot->mmc, 0);
1636         }
1637 }
1638
1639 static void atmci_tasklet_func(unsigned long priv)
1640 {
1641         struct atmel_mci        *host = (struct atmel_mci *)priv;
1642         struct mmc_request      *mrq = host->mrq;
1643         struct mmc_data         *data = host->data;
1644         enum atmel_mci_state    state = host->state;
1645         enum atmel_mci_state    prev_state;
1646         u32                     status;
1647
1648         spin_lock(&host->lock);
1649
1650         state = host->state;
1651
1652         dev_vdbg(&host->pdev->dev,
1653                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1654                 state, host->pending_events, host->completed_events,
1655                 atmci_readl(host, ATMCI_IMR));
1656
1657         do {
1658                 prev_state = state;
1659                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1660
1661                 switch (state) {
1662                 case STATE_IDLE:
1663                         break;
1664
1665                 case STATE_SENDING_CMD:
1666                         /*
1667                          * Command has been sent, we are waiting for command
1668                          * ready. Then we have three next states possible:
1669                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1670                          * command needing it or DATA_XFER if there is data.
1671                          */
1672                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1673                         if (!atmci_test_and_clear_pending(host,
1674                                                 EVENT_CMD_RDY))
1675                                 break;
1676
1677                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1678                         host->cmd = NULL;
1679                         atmci_set_completed(host, EVENT_CMD_RDY);
1680                         atmci_command_complete(host, mrq->cmd);
1681                         if (mrq->data) {
1682                                 dev_dbg(&host->pdev->dev,
1683                                         "command with data transfer");
1684                                 /*
1685                                  * If there is a command error don't start
1686                                  * data transfer.
1687                                  */
1688                                 if (mrq->cmd->error) {
1689                                         host->stop_transfer(host);
1690                                         host->data = NULL;
1691                                         atmci_writel(host, ATMCI_IDR,
1692                                                      ATMCI_TXRDY | ATMCI_RXRDY
1693                                                      | ATMCI_DATA_ERROR_FLAGS);
1694                                         state = STATE_END_REQUEST;
1695                                 } else
1696                                         state = STATE_DATA_XFER;
1697                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1698                                 dev_dbg(&host->pdev->dev,
1699                                         "command response need waiting notbusy");
1700                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1701                                 state = STATE_WAITING_NOTBUSY;
1702                         } else
1703                                 state = STATE_END_REQUEST;
1704
1705                         break;
1706
1707                 case STATE_DATA_XFER:
1708                         if (atmci_test_and_clear_pending(host,
1709                                                 EVENT_DATA_ERROR)) {
1710                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1711                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1712                                 state = STATE_END_REQUEST;
1713                                 break;
1714                         }
1715
1716                         /*
1717                          * A data transfer is in progress. The event expected
1718                          * to move to the next state depends of data transfer
1719                          * type (PDC or DMA). Once transfer done we can move
1720                          * to the next step which is WAITING_NOTBUSY in write
1721                          * case and directly SENDING_STOP in read case.
1722                          */
1723                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1724                         if (!atmci_test_and_clear_pending(host,
1725                                                 EVENT_XFER_COMPLETE))
1726                                 break;
1727
1728                         dev_dbg(&host->pdev->dev,
1729                                 "(%s) set completed xfer complete\n",
1730                                 __func__);
1731                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1732
1733                         if (host->caps.need_notbusy_for_read_ops ||
1734                            (host->data->flags & MMC_DATA_WRITE)) {
1735                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1736                                 state = STATE_WAITING_NOTBUSY;
1737                         } else if (host->mrq->stop) {
1738                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1739                                 atmci_send_stop_cmd(host, data);
1740                                 state = STATE_SENDING_STOP;
1741                         } else {
1742                                 host->data = NULL;
1743                                 data->bytes_xfered = data->blocks * data->blksz;
1744                                 data->error = 0;
1745                                 state = STATE_END_REQUEST;
1746                         }
1747                         break;
1748
1749                 case STATE_WAITING_NOTBUSY:
1750                         /*
1751                          * We can be in the state for two reasons: a command
1752                          * requiring waiting not busy signal (stop command
1753                          * included) or a write operation. In the latest case,
1754                          * we need to send a stop command.
1755                          */
1756                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1757                         if (!atmci_test_and_clear_pending(host,
1758                                                 EVENT_NOTBUSY))
1759                                 break;
1760
1761                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1762                         atmci_set_completed(host, EVENT_NOTBUSY);
1763
1764                         if (host->data) {
1765                                 /*
1766                                  * For some commands such as CMD53, even if
1767                                  * there is data transfer, there is no stop
1768                                  * command to send.
1769                                  */
1770                                 if (host->mrq->stop) {
1771                                         atmci_writel(host, ATMCI_IER,
1772                                                      ATMCI_CMDRDY);
1773                                         atmci_send_stop_cmd(host, data);
1774                                         state = STATE_SENDING_STOP;
1775                                 } else {
1776                                         host->data = NULL;
1777                                         data->bytes_xfered = data->blocks
1778                                                              * data->blksz;
1779                                         data->error = 0;
1780                                         state = STATE_END_REQUEST;
1781                                 }
1782                         } else
1783                                 state = STATE_END_REQUEST;
1784                         break;
1785
1786                 case STATE_SENDING_STOP:
1787                         /*
1788                          * In this state, it is important to set host->data to
1789                          * NULL (which is tested in the waiting notbusy state)
1790                          * in order to go to the end request state instead of
1791                          * sending stop again.
1792                          */
1793                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1794                         if (!atmci_test_and_clear_pending(host,
1795                                                 EVENT_CMD_RDY))
1796                                 break;
1797
1798                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1799                         host->cmd = NULL;
1800                         data->bytes_xfered = data->blocks * data->blksz;
1801                         data->error = 0;
1802                         atmci_command_complete(host, mrq->stop);
1803                         if (mrq->stop->error) {
1804                                 host->stop_transfer(host);
1805                                 atmci_writel(host, ATMCI_IDR,
1806                                              ATMCI_TXRDY | ATMCI_RXRDY
1807                                              | ATMCI_DATA_ERROR_FLAGS);
1808                                 state = STATE_END_REQUEST;
1809                         } else {
1810                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1811                                 state = STATE_WAITING_NOTBUSY;
1812                         }
1813                         host->data = NULL;
1814                         break;
1815
1816                 case STATE_END_REQUEST:
1817                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1818                                            | ATMCI_DATA_ERROR_FLAGS);
1819                         status = host->data_status;
1820                         if (unlikely(status)) {
1821                                 host->stop_transfer(host);
1822                                 host->data = NULL;
1823                                 if (data) {
1824                                         if (status & ATMCI_DTOE) {
1825                                                 data->error = -ETIMEDOUT;
1826                                         } else if (status & ATMCI_DCRCE) {
1827                                                 data->error = -EILSEQ;
1828                                         } else {
1829                                                 data->error = -EIO;
1830                                         }
1831                                 }
1832                         }
1833
1834                         atmci_request_end(host, host->mrq);
1835                         state = STATE_IDLE;
1836                         break;
1837                 }
1838         } while (state != prev_state);
1839
1840         host->state = state;
1841
1842         spin_unlock(&host->lock);
1843 }
1844
1845 static void atmci_read_data_pio(struct atmel_mci *host)
1846 {
1847         struct scatterlist      *sg = host->sg;
1848         void                    *buf = sg_virt(sg);
1849         unsigned int            offset = host->pio_offset;
1850         struct mmc_data         *data = host->data;
1851         u32                     value;
1852         u32                     status;
1853         unsigned int            nbytes = 0;
1854
1855         do {
1856                 value = atmci_readl(host, ATMCI_RDR);
1857                 if (likely(offset + 4 <= sg->length)) {
1858                         put_unaligned(value, (u32 *)(buf + offset));
1859
1860                         offset += 4;
1861                         nbytes += 4;
1862
1863                         if (offset == sg->length) {
1864                                 flush_dcache_page(sg_page(sg));
1865                                 host->sg = sg = sg_next(sg);
1866                                 host->sg_len--;
1867                                 if (!sg || !host->sg_len)
1868                                         goto done;
1869
1870                                 offset = 0;
1871                                 buf = sg_virt(sg);
1872                         }
1873                 } else {
1874                         unsigned int remaining = sg->length - offset;
1875                         memcpy(buf + offset, &value, remaining);
1876                         nbytes += remaining;
1877
1878                         flush_dcache_page(sg_page(sg));
1879                         host->sg = sg = sg_next(sg);
1880                         host->sg_len--;
1881                         if (!sg || !host->sg_len)
1882                                 goto done;
1883
1884                         offset = 4 - remaining;
1885                         buf = sg_virt(sg);
1886                         memcpy(buf, (u8 *)&value + remaining, offset);
1887                         nbytes += offset;
1888                 }
1889
1890                 status = atmci_readl(host, ATMCI_SR);
1891                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1892                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1893                                                 | ATMCI_DATA_ERROR_FLAGS));
1894                         host->data_status = status;
1895                         data->bytes_xfered += nbytes;
1896                         return;
1897                 }
1898         } while (status & ATMCI_RXRDY);
1899
1900         host->pio_offset = offset;
1901         data->bytes_xfered += nbytes;
1902
1903         return;
1904
1905 done:
1906         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1907         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1908         data->bytes_xfered += nbytes;
1909         smp_wmb();
1910         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1911 }
1912
1913 static void atmci_write_data_pio(struct atmel_mci *host)
1914 {
1915         struct scatterlist      *sg = host->sg;
1916         void                    *buf = sg_virt(sg);
1917         unsigned int            offset = host->pio_offset;
1918         struct mmc_data         *data = host->data;
1919         u32                     value;
1920         u32                     status;
1921         unsigned int            nbytes = 0;
1922
1923         do {
1924                 if (likely(offset + 4 <= sg->length)) {
1925                         value = get_unaligned((u32 *)(buf + offset));
1926                         atmci_writel(host, ATMCI_TDR, value);
1927
1928                         offset += 4;
1929                         nbytes += 4;
1930                         if (offset == sg->length) {
1931                                 host->sg = sg = sg_next(sg);
1932                                 host->sg_len--;
1933                                 if (!sg || !host->sg_len)
1934                                         goto done;
1935
1936                                 offset = 0;
1937                                 buf = sg_virt(sg);
1938                         }
1939                 } else {
1940                         unsigned int remaining = sg->length - offset;
1941
1942                         value = 0;
1943                         memcpy(&value, buf + offset, remaining);
1944                         nbytes += remaining;
1945
1946                         host->sg = sg = sg_next(sg);
1947                         host->sg_len--;
1948                         if (!sg || !host->sg_len) {
1949                                 atmci_writel(host, ATMCI_TDR, value);
1950                                 goto done;
1951                         }
1952
1953                         offset = 4 - remaining;
1954                         buf = sg_virt(sg);
1955                         memcpy((u8 *)&value + remaining, buf, offset);
1956                         atmci_writel(host, ATMCI_TDR, value);
1957                         nbytes += offset;
1958                 }
1959
1960                 status = atmci_readl(host, ATMCI_SR);
1961                 if (status & ATMCI_DATA_ERROR_FLAGS) {
1962                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1963                                                 | ATMCI_DATA_ERROR_FLAGS));
1964                         host->data_status = status;
1965                         data->bytes_xfered += nbytes;
1966                         return;
1967                 }
1968         } while (status & ATMCI_TXRDY);
1969
1970         host->pio_offset = offset;
1971         data->bytes_xfered += nbytes;
1972
1973         return;
1974
1975 done:
1976         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1977         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1978         data->bytes_xfered += nbytes;
1979         smp_wmb();
1980         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1981 }
1982
1983 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1984 {
1985         int     i;
1986
1987         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1988                 struct atmel_mci_slot *slot = host->slot[i];
1989                 if (slot && (status & slot->sdio_irq)) {
1990                         mmc_signal_sdio_irq(slot->mmc);
1991                 }
1992         }
1993 }
1994
1995
1996 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1997 {
1998         struct atmel_mci        *host = dev_id;
1999         u32                     status, mask, pending;
2000         unsigned int            pass_count = 0;
2001
2002         do {
2003                 status = atmci_readl(host, ATMCI_SR);
2004                 mask = atmci_readl(host, ATMCI_IMR);
2005                 pending = status & mask;
2006                 if (!pending)
2007                         break;
2008
2009                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2010                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2011                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2012                                         | ATMCI_RXRDY | ATMCI_TXRDY
2013                                         | ATMCI_ENDRX | ATMCI_ENDTX
2014                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2015
2016                         host->data_status = status;
2017                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2018                         smp_wmb();
2019                         atmci_set_pending(host, EVENT_DATA_ERROR);
2020                         tasklet_schedule(&host->tasklet);
2021                 }
2022
2023                 if (pending & ATMCI_TXBUFE) {
2024                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2025                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2026                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2027                         /*
2028                          * We can receive this interruption before having configured
2029                          * the second pdc buffer, so we need to reconfigure first and
2030                          * second buffers again
2031                          */
2032                         if (host->data_size) {
2033                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2034                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2035                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2036                         } else {
2037                                 atmci_pdc_complete(host);
2038                         }
2039                 } else if (pending & ATMCI_ENDTX) {
2040                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2041                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2042
2043                         if (host->data_size) {
2044                                 atmci_pdc_set_single_buf(host,
2045                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2046                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2047                         }
2048                 }
2049
2050                 if (pending & ATMCI_RXBUFF) {
2051                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2052                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2053                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2054                         /*
2055                          * We can receive this interruption before having configured
2056                          * the second pdc buffer, so we need to reconfigure first and
2057                          * second buffers again
2058                          */
2059                         if (host->data_size) {
2060                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2061                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2062                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2063                         } else {
2064                                 atmci_pdc_complete(host);
2065                         }
2066                 } else if (pending & ATMCI_ENDRX) {
2067                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2068                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2069
2070                         if (host->data_size) {
2071                                 atmci_pdc_set_single_buf(host,
2072                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2073                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2074                         }
2075                 }
2076
2077                 /*
2078                  * First mci IPs, so mainly the ones having pdc, have some
2079                  * issues with the notbusy signal. You can't get it after
2080                  * data transmission if you have not sent a stop command.
2081                  * The appropriate workaround is to use the BLKE signal.
2082                  */
2083                 if (pending & ATMCI_BLKE) {
2084                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2085                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2086                         smp_wmb();
2087                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2088                         atmci_set_pending(host, EVENT_NOTBUSY);
2089                         tasklet_schedule(&host->tasklet);
2090                 }
2091
2092                 if (pending & ATMCI_NOTBUSY) {
2093                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2094                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2095                         smp_wmb();
2096                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2097                         atmci_set_pending(host, EVENT_NOTBUSY);
2098                         tasklet_schedule(&host->tasklet);
2099                 }
2100
2101                 if (pending & ATMCI_RXRDY)
2102                         atmci_read_data_pio(host);
2103                 if (pending & ATMCI_TXRDY)
2104                         atmci_write_data_pio(host);
2105
2106                 if (pending & ATMCI_CMDRDY) {
2107                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2108                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2109                         host->cmd_status = status;
2110                         smp_wmb();
2111                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2112                         atmci_set_pending(host, EVENT_CMD_RDY);
2113                         tasklet_schedule(&host->tasklet);
2114                 }
2115
2116                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2117                         atmci_sdio_interrupt(host, status);
2118
2119         } while (pass_count++ < 5);
2120
2121         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2122 }
2123
2124 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2125 {
2126         struct atmel_mci_slot   *slot = dev_id;
2127
2128         /*
2129          * Disable interrupts until the pin has stabilized and check
2130          * the state then. Use mod_timer() since we may be in the
2131          * middle of the timer routine when this interrupt triggers.
2132          */
2133         disable_irq_nosync(irq);
2134         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2135
2136         return IRQ_HANDLED;
2137 }
2138
2139 static int __init atmci_init_slot(struct atmel_mci *host,
2140                 struct mci_slot_pdata *slot_data, unsigned int id,
2141                 u32 sdc_reg, u32 sdio_irq)
2142 {
2143         struct mmc_host                 *mmc;
2144         struct atmel_mci_slot           *slot;
2145
2146         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2147         if (!mmc)
2148                 return -ENOMEM;
2149
2150         slot = mmc_priv(mmc);
2151         slot->mmc = mmc;
2152         slot->host = host;
2153         slot->detect_pin = slot_data->detect_pin;
2154         slot->wp_pin = slot_data->wp_pin;
2155         slot->detect_is_active_high = slot_data->detect_is_active_high;
2156         slot->sdc_reg = sdc_reg;
2157         slot->sdio_irq = sdio_irq;
2158
2159         dev_dbg(&mmc->class_dev,
2160                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2161                 "detect_is_active_high=%s, wp_pin=%d\n",
2162                 id, slot_data->bus_width, slot_data->detect_pin,
2163                 slot_data->detect_is_active_high ? "true" : "false",
2164                 slot_data->wp_pin);
2165
2166         mmc->ops = &atmci_ops;
2167         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2168         mmc->f_max = host->bus_hz / 2;
2169         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2170         if (sdio_irq)
2171                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2172         if (host->caps.has_highspeed)
2173                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2174         /*
2175          * Without the read/write proof capability, it is strongly suggested to
2176          * use only one bit for data to prevent fifo underruns and overruns
2177          * which will corrupt data.
2178          */
2179         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2180                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2181
2182         if (atmci_get_version(host) < 0x200) {
2183                 mmc->max_segs = 256;
2184                 mmc->max_blk_size = 4095;
2185                 mmc->max_blk_count = 256;
2186                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2187                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2188         } else {
2189                 mmc->max_segs = 64;
2190                 mmc->max_req_size = 32768 * 512;
2191                 mmc->max_blk_size = 32768;
2192                 mmc->max_blk_count = 512;
2193         }
2194
2195         /* Assume card is present initially */
2196         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2197         if (gpio_is_valid(slot->detect_pin)) {
2198                 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2199                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2200                         slot->detect_pin = -EBUSY;
2201                 } else if (gpio_get_value(slot->detect_pin) ^
2202                                 slot->detect_is_active_high) {
2203                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2204                 }
2205         }
2206
2207         if (!gpio_is_valid(slot->detect_pin))
2208                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2209
2210         if (gpio_is_valid(slot->wp_pin)) {
2211                 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2212                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2213                         slot->wp_pin = -EBUSY;
2214                 }
2215         }
2216
2217         host->slot[id] = slot;
2218         mmc_regulator_get_supply(mmc);
2219         mmc_add_host(mmc);
2220
2221         if (gpio_is_valid(slot->detect_pin)) {
2222                 int ret;
2223
2224                 setup_timer(&slot->detect_timer, atmci_detect_change,
2225                                 (unsigned long)slot);
2226
2227                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2228                                 atmci_detect_interrupt,
2229                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2230                                 "mmc-detect", slot);
2231                 if (ret) {
2232                         dev_dbg(&mmc->class_dev,
2233                                 "could not request IRQ %d for detect pin\n",
2234                                 gpio_to_irq(slot->detect_pin));
2235                         gpio_free(slot->detect_pin);
2236                         slot->detect_pin = -EBUSY;
2237                 }
2238         }
2239
2240         atmci_init_debugfs(slot);
2241
2242         return 0;
2243 }
2244
2245 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2246                 unsigned int id)
2247 {
2248         /* Debugfs stuff is cleaned up by mmc core */
2249
2250         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2251         smp_wmb();
2252
2253         mmc_remove_host(slot->mmc);
2254
2255         if (gpio_is_valid(slot->detect_pin)) {
2256                 int pin = slot->detect_pin;
2257
2258                 free_irq(gpio_to_irq(pin), slot);
2259                 del_timer_sync(&slot->detect_timer);
2260                 gpio_free(pin);
2261         }
2262         if (gpio_is_valid(slot->wp_pin))
2263                 gpio_free(slot->wp_pin);
2264
2265         slot->host->slot[id] = NULL;
2266         mmc_free_host(slot->mmc);
2267 }
2268
2269 static bool atmci_filter(struct dma_chan *chan, void *pdata)
2270 {
2271         struct mci_platform_data *sl_pdata = pdata;
2272         struct mci_dma_data *sl;
2273
2274         if (!sl_pdata)
2275                 return false;
2276
2277         sl = sl_pdata->dma_slave;
2278         if (sl && find_slave_dev(sl) == chan->device->dev) {
2279                 chan->private = slave_data_ptr(sl);
2280                 return true;
2281         } else {
2282                 return false;
2283         }
2284 }
2285
2286 static bool atmci_configure_dma(struct atmel_mci *host)
2287 {
2288         struct mci_platform_data        *pdata;
2289         dma_cap_mask_t mask;
2290
2291         if (host == NULL)
2292                 return false;
2293
2294         pdata = host->pdev->dev.platform_data;
2295
2296         dma_cap_zero(mask);
2297         dma_cap_set(DMA_SLAVE, mask);
2298
2299         host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2300                                                           &host->pdev->dev, "rxtx");
2301         if (!host->dma.chan) {
2302                 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2303                 return false;
2304         } else {
2305                 dev_info(&host->pdev->dev,
2306                                         "using %s for DMA transfers\n",
2307                                         dma_chan_name(host->dma.chan));
2308
2309                 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2310                 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2311                 host->dma_conf.src_maxburst = 1;
2312                 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2313                 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2314                 host->dma_conf.dst_maxburst = 1;
2315                 host->dma_conf.device_fc = false;
2316                 return true;
2317         }
2318 }
2319
2320 /*
2321  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2322  * HSMCI provides DMA support and a new config register but no more supports
2323  * PDC.
2324  */
2325 static void __init atmci_get_cap(struct atmel_mci *host)
2326 {
2327         unsigned int version;
2328
2329         version = atmci_get_version(host);
2330         dev_info(&host->pdev->dev,
2331                         "version: 0x%x\n", version);
2332
2333         host->caps.has_dma_conf_reg = 0;
2334         host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2335         host->caps.has_cfg_reg = 0;
2336         host->caps.has_cstor_reg = 0;
2337         host->caps.has_highspeed = 0;
2338         host->caps.has_rwproof = 0;
2339         host->caps.has_odd_clk_div = 0;
2340         host->caps.has_bad_data_ordering = 1;
2341         host->caps.need_reset_after_xfer = 1;
2342         host->caps.need_blksz_mul_4 = 1;
2343         host->caps.need_notbusy_for_read_ops = 0;
2344
2345         /* keep only major version number */
2346         switch (version & 0xf00) {
2347         case 0x500:
2348                 host->caps.has_odd_clk_div = 1;
2349         case 0x400:
2350         case 0x300:
2351                 host->caps.has_dma_conf_reg = 1;
2352                 host->caps.has_pdc = 0;
2353                 host->caps.has_cfg_reg = 1;
2354                 host->caps.has_cstor_reg = 1;
2355                 host->caps.has_highspeed = 1;
2356         case 0x200:
2357                 host->caps.has_rwproof = 1;
2358                 host->caps.need_blksz_mul_4 = 0;
2359                 host->caps.need_notbusy_for_read_ops = 1;
2360         case 0x100:
2361                 host->caps.has_bad_data_ordering = 0;
2362                 host->caps.need_reset_after_xfer = 0;
2363         case 0x0:
2364                 break;
2365         default:
2366                 host->caps.has_pdc = 0;
2367                 dev_warn(&host->pdev->dev,
2368                                 "Unmanaged mci version, set minimum capabilities\n");
2369                 break;
2370         }
2371 }
2372
2373 static int __init atmci_probe(struct platform_device *pdev)
2374 {
2375         struct mci_platform_data        *pdata;
2376         struct atmel_mci                *host;
2377         struct resource                 *regs;
2378         unsigned int                    nr_slots;
2379         int                             irq;
2380         int                             ret;
2381
2382         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2383         if (!regs)
2384                 return -ENXIO;
2385         pdata = pdev->dev.platform_data;
2386         if (!pdata) {
2387                 pdata = atmci_of_init(pdev);
2388                 if (IS_ERR(pdata)) {
2389                         dev_err(&pdev->dev, "platform data not available\n");
2390                         return PTR_ERR(pdata);
2391                 }
2392         }
2393
2394         irq = platform_get_irq(pdev, 0);
2395         if (irq < 0)
2396                 return irq;
2397
2398         host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2399         if (!host)
2400                 return -ENOMEM;
2401
2402         host->pdev = pdev;
2403         spin_lock_init(&host->lock);
2404         INIT_LIST_HEAD(&host->queue);
2405
2406         host->mck = clk_get(&pdev->dev, "mci_clk");
2407         if (IS_ERR(host->mck)) {
2408                 ret = PTR_ERR(host->mck);
2409                 goto err_clk_get;
2410         }
2411
2412         ret = -ENOMEM;
2413         host->regs = ioremap(regs->start, resource_size(regs));
2414         if (!host->regs)
2415                 goto err_ioremap;
2416
2417         ret = clk_prepare_enable(host->mck);
2418         if (ret)
2419                 goto err_request_irq;
2420         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2421         host->bus_hz = clk_get_rate(host->mck);
2422         clk_disable_unprepare(host->mck);
2423
2424         host->mapbase = regs->start;
2425
2426         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2427
2428         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2429         if (ret)
2430                 goto err_request_irq;
2431
2432         /* Get MCI capabilities and set operations according to it */
2433         atmci_get_cap(host);
2434         if (atmci_configure_dma(host)) {
2435                 host->prepare_data = &atmci_prepare_data_dma;
2436                 host->submit_data = &atmci_submit_data_dma;
2437                 host->stop_transfer = &atmci_stop_transfer_dma;
2438         } else if (host->caps.has_pdc) {
2439                 dev_info(&pdev->dev, "using PDC\n");
2440                 host->prepare_data = &atmci_prepare_data_pdc;
2441                 host->submit_data = &atmci_submit_data_pdc;
2442                 host->stop_transfer = &atmci_stop_transfer_pdc;
2443         } else {
2444                 dev_info(&pdev->dev, "using PIO\n");
2445                 host->prepare_data = &atmci_prepare_data;
2446                 host->submit_data = &atmci_submit_data;
2447                 host->stop_transfer = &atmci_stop_transfer;
2448         }
2449
2450         platform_set_drvdata(pdev, host);
2451
2452         setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2453
2454         /* We need at least one slot to succeed */
2455         nr_slots = 0;
2456         ret = -ENODEV;
2457         if (pdata->slot[0].bus_width) {
2458                 ret = atmci_init_slot(host, &pdata->slot[0],
2459                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2460                 if (!ret) {
2461                         nr_slots++;
2462                         host->buf_size = host->slot[0]->mmc->max_req_size;
2463                 }
2464         }
2465         if (pdata->slot[1].bus_width) {
2466                 ret = atmci_init_slot(host, &pdata->slot[1],
2467                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2468                 if (!ret) {
2469                         nr_slots++;
2470                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2471                                 host->buf_size =
2472                                         host->slot[1]->mmc->max_req_size;
2473                 }
2474         }
2475
2476         if (!nr_slots) {
2477                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2478                 goto err_init_slot;
2479         }
2480
2481         if (!host->caps.has_rwproof) {
2482                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2483                                                   &host->buf_phys_addr,
2484                                                   GFP_KERNEL);
2485                 if (!host->buffer) {
2486                         ret = -ENOMEM;
2487                         dev_err(&pdev->dev, "buffer allocation failed\n");
2488                         goto err_init_slot;
2489                 }
2490         }
2491
2492         dev_info(&pdev->dev,
2493                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2494                         host->mapbase, irq, nr_slots);
2495
2496         return 0;
2497
2498 err_init_slot:
2499         if (host->dma.chan)
2500                 dma_release_channel(host->dma.chan);
2501         free_irq(irq, host);
2502 err_request_irq:
2503         iounmap(host->regs);
2504 err_ioremap:
2505         clk_put(host->mck);
2506 err_clk_get:
2507         kfree(host);
2508         return ret;
2509 }
2510
2511 static int __exit atmci_remove(struct platform_device *pdev)
2512 {
2513         struct atmel_mci        *host = platform_get_drvdata(pdev);
2514         unsigned int            i;
2515
2516         if (host->buffer)
2517                 dma_free_coherent(&pdev->dev, host->buf_size,
2518                                   host->buffer, host->buf_phys_addr);
2519
2520         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2521                 if (host->slot[i])
2522                         atmci_cleanup_slot(host->slot[i], i);
2523         }
2524
2525         clk_prepare_enable(host->mck);
2526         atmci_writel(host, ATMCI_IDR, ~0UL);
2527         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2528         atmci_readl(host, ATMCI_SR);
2529         clk_disable_unprepare(host->mck);
2530
2531         if (host->dma.chan)
2532                 dma_release_channel(host->dma.chan);
2533
2534         free_irq(platform_get_irq(pdev, 0), host);
2535         iounmap(host->regs);
2536
2537         clk_put(host->mck);
2538         kfree(host);
2539
2540         return 0;
2541 }
2542
2543 static struct platform_driver atmci_driver = {
2544         .remove         = __exit_p(atmci_remove),
2545         .driver         = {
2546                 .name           = "atmel_mci",
2547                 .of_match_table = of_match_ptr(atmci_dt_ids),
2548         },
2549 };
2550
2551 static int __init atmci_init(void)
2552 {
2553         return platform_driver_probe(&atmci_driver, atmci_probe);
2554 }
2555
2556 static void __exit atmci_exit(void)
2557 {
2558         platform_driver_unregister(&atmci_driver);
2559 }
2560
2561 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2562 module_exit(atmci_exit);
2563
2564 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2565 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2566 MODULE_LICENSE("GPL v2");