drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Rockchip Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2014, Rockchip Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15
  16 #include <linux/slab.h>
  17
  18 #include <linux/mmc/host.h>
  19 #include <linux/mmc/rk_mmc.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22
  23 #include "rk_sdmmc.h"
  24 #include "dw_mmc-pltfm.h"
  25
  26 #include "rk_sdmmc_of.h"
  27
  28 #define NUM_PINS(x)                     (x + 2)
  29
  30 /* SDMMC_CLKSEL is not used in Rockchip
  31 #define SDMMC_CLKSEL                    0x09C
  32 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)     (((x) & 7) << 0)
  33 #define SDMMC_CLKSEL_CCLK_DRIVE(x)      (((x) & 7) << 16)
  34 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)    (((x) & 7) << 24)
  35 #define SDMMC_CLKSEL_GET_DRV_WD3(x)     (((x) >> 16) & 0x7)
  36 #define SDMMC_CLKSEL_TIMING(x, y, z)    (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
  37                                         SDMMC_CLKSEL_CCLK_DRIVE(y) |    \
  38                                         SDMMC_CLKSEL_CCLK_DIVIDER(z))
  39 */
  40 #define SDMMC_CMD_USE_HOLD_REG          BIT(29)
  41
  42 //#define EXYNOS4210_FIXED_CIU_CLK_DIV  2
  43 //#define EXYNOS4412_FIXED_CIU_CLK_DIV  4
  44
  45 /* Variations in Rockchip specific dw-mshc controller */
  46 enum dw_mci_rockchip_type {
  47         DW_MCI_TYPE_RK3188,
  48         DW_MCI_TYPE_RK3288,
  49 };
  50
  51 /* Rockchip implementation specific driver private data */
  52 struct dw_mci_rockchip_priv_data {
  53         enum dw_mci_rockchip_type               ctrl_type;
  54         u8                              ciu_div;
  55         u32                             sdr_timing;
  56         u32                             ddr_timing;
  57 };
  58
  59 static struct dw_mci_rockchip_compatible {
  60         char                            *compatible;
  61         enum dw_mci_rockchip_type               ctrl_type;
  62 } rockchip_compat[] = {
  63         {
  64                 .compatible     = "rockchip,rk3188-sdmmc",
  65                 .ctrl_type      = DW_MCI_TYPE_RK3188,
  66         },{
  67                 .compatible     = "rockchip,rk3288-sdmmc",
  68                 .ctrl_type      = DW_MCI_TYPE_RK3288,
  69         },
  70 };
  71
  72 static int dw_mci_rockchip_priv_init(struct dw_mci *host)
  73 {
  74         struct dw_mci_rockchip_priv_data *priv;
  75         int idx;
  76
  77         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  78         if (!priv) {
  79                 dev_err(host->dev, "mem alloc failed for private data\n");
  80                 return -ENOMEM;
  81         }
  82
  83         for (idx = 0; idx < ARRAY_SIZE(rockchip_compat); idx++) {
  84                 if (of_device_is_compatible(host->dev->of_node,
  85                                         rockchip_compat[idx].compatible))
  86                         priv->ctrl_type = rockchip_compat[idx].ctrl_type;
  87         }
  88
  89         host->priv = priv;
  90         return 0;
  91 }
  92
  93 static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
  94 {
  95         struct dw_mci_rockchip_priv_data *priv = host->priv;
  96
  97         if (priv->ctrl_type == DW_MCI_TYPE_RK3288)
  98                 host->bus_hz /= (priv->ciu_div + 1);
  99         /*else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
 100                 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
 101         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 102                 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
 103     */
 104         return 0;
 105 }
 106
 107 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
 108 {
 109         /*
 110          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 111          * use of bit 29 (which is reserved on standard MSHC controllers) for
 112          * optionally bypassing the HOLD register for command and data. The
 113          * HOLD register should be bypassed in case there is no phase shift
 114          * applied on CMD/DATA that is sent to the card.
 115          */
 116 //      if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
 117 //              *cmdr |= SDMMC_CMD_USE_HOLD_REG;
 118 }
 119
 120 static void dw_mci_rockchip_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 121 {
 122         //struct dw_mci_rockchip_priv_data *priv = host->priv;
 123 /*
 124         if (ios->timing == MMC_TIMING_UHS_DDR50)
 125                 mci_writel(host, CLKSEL, priv->ddr_timing);
 126         else
 127                 mci_writel(host, CLKSEL, priv->sdr_timing);
 128 */
 129 }
 130
 131 static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
 132 {
 133 /*
 134         struct dw_mci_rockchip_priv_data *priv = host->priv;
 135         struct device_node *np = host->dev->of_node;
 136         u32 timing[2];
 137         u32 div = 0;
 138         int ret;
 139         //rk set the timing in CRU
 140         of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 141         priv->ciu_div = div;
 142
 143         ret = of_property_read_u32_array(np,
 144                         "samsung,dw-mshc-sdr-timing", timing, 2);
 145         if (ret)
 146                 return ret;
 147
 148         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 149
 150         ret = of_property_read_u32_array(np,
 151                         "samsung,dw-mshc-ddr-timing", timing, 2);
 152         if (ret)
 153                 return ret;
 154
 155         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 156         */
 157         return 0;
 158 }
 159
 160 /* Common capabilities of RK32XX SoC */
 161 static unsigned long rockchip_dwmmc_caps[4] = {
 162         /*MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | //Temporarily comment out!!!!!!, deleted by xbw, at 2014-03-12*/
 163         MMC_CAP_8_BIT_DATA|MMC_CAP_4_BIT_DATA|MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50|MMC_CAP_UHS_SDR104|MMC_CAP_ERASE,
 164         MMC_CAP_CMD23,
 165         MMC_CAP_CMD23,
 166         MMC_CAP_CMD23,
 167 };
 168
 169 unsigned int  rockchip_dwmmc_hold_reg[4] = {1,0,0,0};
 170
 171 static const struct dw_mci_drv_data rockchip_drv_data = {
 172         .caps                   = rockchip_dwmmc_caps,
 173         .hold_reg_flag  = rockchip_dwmmc_hold_reg,
 174         .init                   = dw_mci_rockchip_priv_init,
 175         .setup_clock            = dw_mci_rockchip_setup_clock,
 176         .prepare_command        = dw_mci_rockchip_prepare_command,
 177         .set_ios                = dw_mci_rockchip_set_ios,
 178         .parse_dt               = dw_mci_rockchip_parse_dt,
 179 };
 180
 181 static const struct of_device_id dw_mci_rockchip_match[] = {
 182         { .compatible = "rockchip,rk_mmc",
 183                         .data = &rockchip_drv_data, },
 184         { /* Sentinel */},
 185 };
 186 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 187
 188 extern void rockchip_mmc_of_probe(struct device_node *np,struct rk_sdmmc_of *mmc_property);
 189
 190 #define DW_MMC_OF_PROBE 0
 191 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 192 {
 193         const struct dw_mci_drv_data *drv_data;
 194         const struct of_device_id *match;
 195     struct device_node *np = pdev->dev.of_node;
 196         struct rk_sdmmc_of *rk_mmc_property = NULL;
 197
 198     #if DW_MMC_OF_PROBE
 199     rk_mmc_property = (struct rk_sdmmc_of *)kmalloc(sizeof(struct rk_sdmmc_of),GFP_KERNEL);
 200     if(NULL == rk_mmc_property)
 201     {
 202         kfree(rk_mmc_property);
 203         rk_mmc_property = NULL;
 204         printk("rk_mmc_property malloc space failed!\n");
 205         return 0;
 206     }
 207
 208     rockchip_mmc_of_probe(np,rk_mmc_property);
 209     #endif /*DW_MMC_OF_PROBE*/
 210
 211
 212         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 213         drv_data = match->data;
 214         return dw_mci_pltfm_register(pdev, drv_data);
 215 }
 216
 217 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 218         .probe          = dw_mci_rockchip_probe,
 219         .remove         = __exit_p(dw_mci_pltfm_remove),
 220         .driver         = {
 221                 .name           = "dwmmc_rockchip",
 222                 .of_match_table = dw_mci_rockchip_match,
 223                 .pm             = &dw_mci_pltfm_pmops,
 224         },
 225 };
 226
 227 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 228
 229 MODULE_DESCRIPTION("Rockchip Specific DW-SDMMC Driver Extension");
 230 MODULE_AUTHOR("Bangwang Xie < xbw@rock-chips.com>");
 231 MODULE_LICENSE("GPL v2");
 232 MODULE_ALIAS("platform:dwmmc-rockchip");