2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
67 u32 des1; /* Reserved */
69 u32 des2; /*Buffer sizes */
70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74 u32 des3; /* Reserved */
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
84 __le32 des0; /* Control Descriptor */
85 #define IDMAC_DES0_DIC BIT(1)
86 #define IDMAC_DES0_LD BIT(2)
87 #define IDMAC_DES0_FD BIT(3)
88 #define IDMAC_DES0_CH BIT(4)
89 #define IDMAC_DES0_ER BIT(5)
90 #define IDMAC_DES0_CES BIT(30)
91 #define IDMAC_DES0_OWN BIT(31)
93 __le32 des1; /* Buffer sizes */
94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
97 __le32 des2; /* buffer 1 physical address */
99 __le32 des3; /* buffer 2 physical address */
102 /* Each descriptor can transfer up to 4KB of data in chained mode */
103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
105 static bool dw_mci_reset(struct dw_mci *host);
106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
107 static int dw_mci_card_busy(struct mmc_host *mmc);
108 static int dw_mci_get_cd(struct mmc_host *mmc);
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
146 spin_unlock_bh(&slot->host->lock);
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
153 return single_open(file, dw_mci_req_show, inode->i_private);
156 static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
161 .release = single_release,
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
166 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
167 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
168 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
169 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
170 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
171 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
176 static int dw_mci_regs_open(struct inode *inode, struct file *file)
178 return single_open(file, dw_mci_regs_show, inode->i_private);
181 static const struct file_operations dw_mci_regs_fops = {
182 .owner = THIS_MODULE,
183 .open = dw_mci_regs_open,
186 .release = single_release,
189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
191 struct mmc_host *mmc = slot->mmc;
192 struct dw_mci *host = slot->host;
196 root = mmc->debugfs_root;
200 node = debugfs_create_file("regs", S_IRUSR, root, host,
205 node = debugfs_create_file("req", S_IRUSR, root, slot,
210 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
214 node = debugfs_create_x32("pending_events", S_IRUSR, root,
215 (u32 *)&host->pending_events);
219 node = debugfs_create_x32("completed_events", S_IRUSR, root,
220 (u32 *)&host->completed_events);
227 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
229 #endif /* defined(CONFIG_DEBUG_FS) */
231 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
235 struct mmc_data *data;
236 struct dw_mci_slot *slot = mmc_priv(mmc);
237 struct dw_mci *host = slot->host;
238 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
241 cmd->error = -EINPROGRESS;
244 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
245 cmd->opcode == MMC_GO_IDLE_STATE ||
246 cmd->opcode == MMC_GO_INACTIVE_STATE ||
247 (cmd->opcode == SD_IO_RW_DIRECT &&
248 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
249 cmdr |= SDMMC_CMD_STOP;
250 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
251 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
253 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
256 /* Special bit makes CMD11 not die */
257 cmdr |= SDMMC_CMD_VOLT_SWITCH;
259 /* Change state to continue to handle CMD11 weirdness */
260 WARN_ON(slot->host->state != STATE_SENDING_CMD);
261 slot->host->state = STATE_SENDING_CMD11;
264 * We need to disable low power mode (automatic clock stop)
265 * while doing voltage switch so we don't confuse the card,
266 * since stopping the clock is a specific part of the UHS
267 * voltage change dance.
269 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
270 * unconditionally turned back on in dw_mci_setup_bus() if it's
271 * ever called with a non-zero clock. That shouldn't happen
272 * until the voltage change is all done.
274 clk_en_a = mci_readl(host, CLKENA);
275 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
276 mci_writel(host, CLKENA, clk_en_a);
277 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
278 SDMMC_CMD_PRV_DAT_WAIT, 0);
281 if (cmd->flags & MMC_RSP_PRESENT) {
282 /* We expect a response, so set this bit */
283 cmdr |= SDMMC_CMD_RESP_EXP;
284 if (cmd->flags & MMC_RSP_136)
285 cmdr |= SDMMC_CMD_RESP_LONG;
288 if (cmd->flags & MMC_RSP_CRC)
289 cmdr |= SDMMC_CMD_RESP_CRC;
293 cmdr |= SDMMC_CMD_DAT_EXP;
294 if (data->flags & MMC_DATA_STREAM)
295 cmdr |= SDMMC_CMD_STRM_MODE;
296 if (data->flags & MMC_DATA_WRITE)
297 cmdr |= SDMMC_CMD_DAT_WR;
300 if (drv_data && drv_data->prepare_command)
301 drv_data->prepare_command(slot->host, &cmdr);
306 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
308 struct mmc_command *stop;
314 stop = &host->stop_abort;
316 memset(stop, 0, sizeof(struct mmc_command));
318 if (cmdr == MMC_READ_SINGLE_BLOCK ||
319 cmdr == MMC_READ_MULTIPLE_BLOCK ||
320 cmdr == MMC_WRITE_BLOCK ||
321 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK ||
323 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
324 stop->opcode = MMC_STOP_TRANSMISSION;
326 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
327 } else if (cmdr == SD_IO_RW_EXTENDED) {
328 stop->opcode = SD_IO_RW_DIRECT;
329 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
330 ((cmd->arg >> 28) & 0x7);
331 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
336 cmdr = stop->opcode | SDMMC_CMD_STOP |
337 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
342 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
344 unsigned long timeout = jiffies + msecs_to_jiffies(500);
347 * Databook says that before issuing a new data transfer command
348 * we need to check to see if the card is busy. Data transfer commands
349 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
351 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
354 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
355 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
356 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
357 if (time_after(jiffies, timeout)) {
358 /* Command will fail; we'll pass error then */
359 dev_err(host->dev, "Busy; trying anyway\n");
367 static void dw_mci_start_command(struct dw_mci *host,
368 struct mmc_command *cmd, u32 cmd_flags)
372 "start command: ARGR=0x%08x CMDR=0x%08x\n",
373 cmd->arg, cmd_flags);
375 mci_writel(host, CMDARG, cmd->arg);
376 wmb(); /* drain writebuffer */
377 dw_mci_wait_while_busy(host, cmd_flags);
379 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
382 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
384 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
386 dw_mci_start_command(host, stop, host->stop_cmdr);
389 /* DMA interface functions */
390 static void dw_mci_stop_dma(struct dw_mci *host)
392 if (host->using_dma) {
393 host->dma_ops->stop(host);
394 host->dma_ops->cleanup(host);
397 /* Data transfer was stopped by the interrupt handler */
398 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
401 static int dw_mci_get_dma_dir(struct mmc_data *data)
403 if (data->flags & MMC_DATA_WRITE)
404 return DMA_TO_DEVICE;
406 return DMA_FROM_DEVICE;
409 static void dw_mci_dma_cleanup(struct dw_mci *host)
411 struct mmc_data *data = host->data;
414 if (!data->host_cookie)
415 dma_unmap_sg(host->dev,
418 dw_mci_get_dma_dir(data));
421 static void dw_mci_idmac_reset(struct dw_mci *host)
423 u32 bmod = mci_readl(host, BMOD);
424 /* Software reset of DMA */
425 bmod |= SDMMC_IDMAC_SWRESET;
426 mci_writel(host, BMOD, bmod);
429 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
433 /* Disable and reset the IDMAC interface */
434 temp = mci_readl(host, CTRL);
435 temp &= ~SDMMC_CTRL_USE_IDMAC;
436 temp |= SDMMC_CTRL_DMA_RESET;
437 mci_writel(host, CTRL, temp);
439 /* Stop the IDMAC running */
440 temp = mci_readl(host, BMOD);
441 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
442 temp |= SDMMC_IDMAC_SWRESET;
443 mci_writel(host, BMOD, temp);
446 static void dw_mci_dmac_complete_dma(void *arg)
448 struct dw_mci *host = arg;
449 struct mmc_data *data = host->data;
451 dev_vdbg(host->dev, "DMA complete\n");
453 if ((host->use_dma == TRANS_MODE_EDMAC) &&
454 data && (data->flags & MMC_DATA_READ))
455 /* Invalidate cache after read */
456 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
461 host->dma_ops->cleanup(host);
464 * If the card was removed, data will be NULL. No point in trying to
465 * send the stop command or waiting for NBUSY in this case.
468 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
469 tasklet_schedule(&host->tasklet);
473 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
476 unsigned int desc_len;
479 if (host->dma_64bit_address == 1) {
480 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
482 desc_first = desc_last = desc = host->sg_cpu;
484 for (i = 0; i < sg_len; i++) {
485 unsigned int length = sg_dma_len(&data->sg[i]);
487 u64 mem_addr = sg_dma_address(&data->sg[i]);
489 for ( ; length ; desc++) {
490 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
491 length : DW_MCI_DESC_DATA_LENGTH;
496 * Set the OWN bit and disable interrupts
497 * for this descriptor
499 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
503 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
505 /* Physical address to DMA to/from */
506 desc->des4 = mem_addr & 0xffffffff;
507 desc->des5 = mem_addr >> 32;
509 /* Update physical address for the next desc */
510 mem_addr += desc_len;
512 /* Save pointer to the last descriptor */
517 /* Set first descriptor */
518 desc_first->des0 |= IDMAC_DES0_FD;
520 /* Set last descriptor */
521 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
522 desc_last->des0 |= IDMAC_DES0_LD;
525 struct idmac_desc *desc_first, *desc_last, *desc;
527 desc_first = desc_last = desc = host->sg_cpu;
529 for (i = 0; i < sg_len; i++) {
530 unsigned int length = sg_dma_len(&data->sg[i]);
532 u32 mem_addr = sg_dma_address(&data->sg[i]);
534 for ( ; length ; desc++) {
535 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
536 length : DW_MCI_DESC_DATA_LENGTH;
541 * Set the OWN bit and disable interrupts
542 * for this descriptor
544 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
549 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
551 /* Physical address to DMA to/from */
552 desc->des2 = cpu_to_le32(mem_addr);
554 /* Update physical address for the next desc */
555 mem_addr += desc_len;
557 /* Save pointer to the last descriptor */
562 /* Set first descriptor */
563 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
565 /* Set last descriptor */
566 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
568 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
571 wmb(); /* drain writebuffer */
574 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
578 dw_mci_translate_sglist(host, host->data, sg_len);
580 /* Make sure to reset DMA in case we did PIO before this */
581 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
582 dw_mci_idmac_reset(host);
584 /* Select IDMAC interface */
585 temp = mci_readl(host, CTRL);
586 temp |= SDMMC_CTRL_USE_IDMAC;
587 mci_writel(host, CTRL, temp);
589 /* drain writebuffer */
592 /* Enable the IDMAC */
593 temp = mci_readl(host, BMOD);
594 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
595 mci_writel(host, BMOD, temp);
597 /* Start it running */
598 mci_writel(host, PLDMND, 1);
603 static int dw_mci_idmac_init(struct dw_mci *host)
607 if (host->dma_64bit_address == 1) {
608 struct idmac_desc_64addr *p;
609 /* Number of descriptors in the ring buffer */
610 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
612 /* Forward link the descriptor list */
613 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
615 p->des6 = (host->sg_dma +
616 (sizeof(struct idmac_desc_64addr) *
617 (i + 1))) & 0xffffffff;
619 p->des7 = (u64)(host->sg_dma +
620 (sizeof(struct idmac_desc_64addr) *
622 /* Initialize reserved and buffer size fields to "0" */
628 /* Set the last descriptor as the end-of-ring descriptor */
629 p->des6 = host->sg_dma & 0xffffffff;
630 p->des7 = (u64)host->sg_dma >> 32;
631 p->des0 = IDMAC_DES0_ER;
634 struct idmac_desc *p;
635 /* Number of descriptors in the ring buffer */
636 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
638 /* Forward link the descriptor list */
639 for (i = 0, p = host->sg_cpu;
640 i < host->ring_size - 1;
642 p->des3 = cpu_to_le32(host->sg_dma +
643 (sizeof(struct idmac_desc) * (i + 1)));
647 /* Set the last descriptor as the end-of-ring descriptor */
648 p->des3 = cpu_to_le32(host->sg_dma);
649 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
652 dw_mci_idmac_reset(host);
654 if (host->dma_64bit_address == 1) {
655 /* Mask out interrupts - get Tx & Rx complete only */
656 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
657 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
658 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
660 /* Set the descriptor base address */
661 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
662 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
665 /* Mask out interrupts - get Tx & Rx complete only */
666 mci_writel(host, IDSTS, IDMAC_INT_CLR);
667 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
668 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
670 /* Set the descriptor base address */
671 mci_writel(host, DBADDR, host->sg_dma);
677 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
678 .init = dw_mci_idmac_init,
679 .start = dw_mci_idmac_start_dma,
680 .stop = dw_mci_idmac_stop_dma,
681 .complete = dw_mci_dmac_complete_dma,
682 .cleanup = dw_mci_dma_cleanup,
685 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
687 dmaengine_terminate_all(host->dms->ch);
690 static int dw_mci_edmac_start_dma(struct dw_mci *host,
693 struct dma_slave_config cfg;
694 struct dma_async_tx_descriptor *desc = NULL;
695 struct scatterlist *sgl = host->data->sg;
696 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
697 u32 sg_elems = host->data->sg_len;
699 u32 fifo_offset = host->fifo_reg - host->regs;
702 /* Set external dma config: burst size, burst width */
703 cfg.dst_addr = host->phy_regs + fifo_offset;
704 cfg.src_addr = cfg.dst_addr;
705 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
706 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
708 /* Match burst msize with external dma config */
709 fifoth_val = mci_readl(host, FIFOTH);
710 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
711 cfg.src_maxburst = cfg.dst_maxburst;
713 if (host->data->flags & MMC_DATA_WRITE)
714 cfg.direction = DMA_MEM_TO_DEV;
716 cfg.direction = DMA_DEV_TO_MEM;
718 ret = dmaengine_slave_config(host->dms->ch, &cfg);
720 dev_err(host->dev, "Failed to config edmac.\n");
724 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
725 sg_len, cfg.direction,
726 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
728 dev_err(host->dev, "Can't prepare slave sg.\n");
732 /* Set dw_mci_dmac_complete_dma as callback */
733 desc->callback = dw_mci_dmac_complete_dma;
734 desc->callback_param = (void *)host;
735 dmaengine_submit(desc);
737 /* Flush cache before write */
738 if (host->data->flags & MMC_DATA_WRITE)
739 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
740 sg_elems, DMA_TO_DEVICE);
742 dma_async_issue_pending(host->dms->ch);
747 static int dw_mci_edmac_init(struct dw_mci *host)
749 /* Request external dma channel */
750 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
754 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
755 if (!host->dms->ch) {
756 dev_err(host->dev, "Failed to get external DMA channel.\n");
765 static void dw_mci_edmac_exit(struct dw_mci *host)
769 dma_release_channel(host->dms->ch);
770 host->dms->ch = NULL;
777 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
778 .init = dw_mci_edmac_init,
779 .exit = dw_mci_edmac_exit,
780 .start = dw_mci_edmac_start_dma,
781 .stop = dw_mci_edmac_stop_dma,
782 .complete = dw_mci_dmac_complete_dma,
783 .cleanup = dw_mci_dma_cleanup,
786 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
787 struct mmc_data *data,
790 struct scatterlist *sg;
791 unsigned int i, sg_len;
793 if (!next && data->host_cookie)
794 return data->host_cookie;
797 * We don't do DMA on "complex" transfers, i.e. with
798 * non-word-aligned buffers or lengths. Also, we don't bother
799 * with all the DMA setup overhead for short transfers.
801 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
807 for_each_sg(data->sg, sg, data->sg_len, i) {
808 if (sg->offset & 3 || sg->length & 3)
812 sg_len = dma_map_sg(host->dev,
815 dw_mci_get_dma_dir(data));
820 data->host_cookie = sg_len;
825 static void dw_mci_pre_req(struct mmc_host *mmc,
826 struct mmc_request *mrq,
829 struct dw_mci_slot *slot = mmc_priv(mmc);
830 struct mmc_data *data = mrq->data;
832 if (!slot->host->use_dma || !data)
835 if (data->host_cookie) {
836 data->host_cookie = 0;
840 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
841 data->host_cookie = 0;
844 static void dw_mci_post_req(struct mmc_host *mmc,
845 struct mmc_request *mrq,
848 struct dw_mci_slot *slot = mmc_priv(mmc);
849 struct mmc_data *data = mrq->data;
851 if (!slot->host->use_dma || !data)
854 if (data->host_cookie)
855 dma_unmap_sg(slot->host->dev,
858 dw_mci_get_dma_dir(data));
859 data->host_cookie = 0;
862 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
864 unsigned int blksz = data->blksz;
865 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
866 u32 fifo_width = 1 << host->data_shift;
867 u32 blksz_depth = blksz / fifo_width, fifoth_val;
868 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
869 int idx = ARRAY_SIZE(mszs) - 1;
871 /* pio should ship this scenario */
875 tx_wmark = (host->fifo_depth) / 2;
876 tx_wmark_invers = host->fifo_depth - tx_wmark;
880 * if blksz is not a multiple of the FIFO width
882 if (blksz % fifo_width) {
889 if (!((blksz_depth % mszs[idx]) ||
890 (tx_wmark_invers % mszs[idx]))) {
892 rx_wmark = mszs[idx] - 1;
897 * If idx is '0', it won't be tried
898 * Thus, initial values are uesed
901 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
902 mci_writel(host, FIFOTH, fifoth_val);
905 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
907 unsigned int blksz = data->blksz;
908 u32 blksz_depth, fifo_depth;
911 WARN_ON(!(data->flags & MMC_DATA_READ));
914 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
915 * in the FIFO region, so we really shouldn't access it).
917 if (host->verid < DW_MMC_240A)
920 if (host->timing != MMC_TIMING_MMC_HS200 &&
921 host->timing != MMC_TIMING_MMC_HS400 &&
922 host->timing != MMC_TIMING_UHS_SDR104)
925 blksz_depth = blksz / (1 << host->data_shift);
926 fifo_depth = host->fifo_depth;
928 if (blksz_depth > fifo_depth)
932 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
933 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
934 * Currently just choose blksz.
937 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
941 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
944 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
946 unsigned long irqflags;
952 /* If we don't have a channel, we can't do DMA */
956 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
958 host->dma_ops->stop(host);
964 if (host->use_dma == TRANS_MODE_IDMAC)
966 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
967 (unsigned long)host->sg_cpu,
968 (unsigned long)host->sg_dma,
972 * Decide the MSIZE and RX/TX Watermark.
973 * If current block size is same with previous size,
974 * no need to update fifoth.
976 if (host->prev_blksz != data->blksz)
977 dw_mci_adjust_fifoth(host, data);
979 /* Enable the DMA interface */
980 temp = mci_readl(host, CTRL);
981 temp |= SDMMC_CTRL_DMA_ENABLE;
982 mci_writel(host, CTRL, temp);
984 /* Disable RX/TX IRQs, let DMA handle it */
985 spin_lock_irqsave(&host->irq_lock, irqflags);
986 temp = mci_readl(host, INTMASK);
987 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
988 mci_writel(host, INTMASK, temp);
989 spin_unlock_irqrestore(&host->irq_lock, irqflags);
991 if (host->dma_ops->start(host, sg_len)) {
992 /* We can't do DMA */
993 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
1000 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1002 unsigned long irqflags;
1003 int flags = SG_MITER_ATOMIC;
1006 data->error = -EINPROGRESS;
1008 WARN_ON(host->data);
1012 if (data->flags & MMC_DATA_READ) {
1013 host->dir_status = DW_MCI_RECV_STATUS;
1014 dw_mci_ctrl_rd_thld(host, data);
1016 host->dir_status = DW_MCI_SEND_STATUS;
1019 if (dw_mci_submit_data_dma(host, data)) {
1020 if (host->data->flags & MMC_DATA_READ)
1021 flags |= SG_MITER_TO_SG;
1023 flags |= SG_MITER_FROM_SG;
1025 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1026 host->sg = data->sg;
1027 host->part_buf_start = 0;
1028 host->part_buf_count = 0;
1030 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1032 spin_lock_irqsave(&host->irq_lock, irqflags);
1033 temp = mci_readl(host, INTMASK);
1034 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1035 mci_writel(host, INTMASK, temp);
1036 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1038 temp = mci_readl(host, CTRL);
1039 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1040 mci_writel(host, CTRL, temp);
1043 * Use the initial fifoth_val for PIO mode.
1044 * If next issued data may be transfered by DMA mode,
1045 * prev_blksz should be invalidated.
1047 mci_writel(host, FIFOTH, host->fifoth_val);
1048 host->prev_blksz = 0;
1051 * Keep the current block size.
1052 * It will be used to decide whether to update
1053 * fifoth register next time.
1055 host->prev_blksz = data->blksz;
1059 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1061 struct dw_mci *host = slot->host;
1062 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1063 unsigned int cmd_status = 0;
1065 mci_writel(host, CMDARG, arg);
1066 wmb(); /* drain writebuffer */
1067 dw_mci_wait_while_busy(host, cmd);
1068 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1070 while (time_before(jiffies, timeout)) {
1071 cmd_status = mci_readl(host, CMD);
1072 if (!(cmd_status & SDMMC_CMD_START))
1075 dev_err(&slot->mmc->class_dev,
1076 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1077 cmd, arg, cmd_status);
1080 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1082 struct dw_mci *host = slot->host;
1083 unsigned int clock = slot->clock;
1086 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1088 /* We must continue to set bit 28 in CMD until the change is complete */
1089 if (host->state == STATE_WAITING_CMD11_DONE)
1090 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1093 mci_writel(host, CLKENA, 0);
1094 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1095 } else if (clock != host->current_speed || force_clkinit) {
1096 div = host->bus_hz / clock;
1097 if (host->bus_hz % clock && host->bus_hz > clock)
1099 * move the + 1 after the divide to prevent
1100 * over-clocking the card.
1104 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1106 if ((clock << div) != slot->__clk_old || force_clkinit)
1107 dev_info(&slot->mmc->class_dev,
1108 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1109 slot->id, host->bus_hz, clock,
1110 div ? ((host->bus_hz / div) >> 1) :
1114 mci_writel(host, CLKENA, 0);
1115 mci_writel(host, CLKSRC, 0);
1118 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1120 /* set clock to desired speed */
1121 mci_writel(host, CLKDIV, div);
1124 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1126 /* enable clock; only low power if no SDIO */
1127 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1128 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1129 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1130 mci_writel(host, CLKENA, clk_en_a);
1133 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1135 /* keep the clock with reflecting clock dividor */
1136 slot->__clk_old = clock << div;
1139 host->current_speed = clock;
1141 /* Set the current slot bus width */
1142 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1145 static void __dw_mci_start_request(struct dw_mci *host,
1146 struct dw_mci_slot *slot,
1147 struct mmc_command *cmd)
1149 struct mmc_request *mrq;
1150 struct mmc_data *data;
1155 host->cur_slot = slot;
1158 host->pending_events = 0;
1159 host->completed_events = 0;
1160 host->cmd_status = 0;
1161 host->data_status = 0;
1162 host->dir_status = 0;
1166 mci_writel(host, TMOUT, 0xFFFFFFFF);
1167 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1168 mci_writel(host, BLKSIZ, data->blksz);
1171 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1173 /* this is the first command, send the initialization clock */
1174 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1175 cmdflags |= SDMMC_CMD_INIT;
1178 dw_mci_submit_data(host, data);
1179 wmb(); /* drain writebuffer */
1182 dw_mci_start_command(host, cmd, cmdflags);
1184 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1185 unsigned long irqflags;
1188 * Databook says to fail after 2ms w/ no response, but evidence
1189 * shows that sometimes the cmd11 interrupt takes over 130ms.
1190 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1191 * is just about to roll over.
1193 * We do this whole thing under spinlock and only if the
1194 * command hasn't already completed (indicating the the irq
1195 * already ran so we don't want the timeout).
1197 spin_lock_irqsave(&host->irq_lock, irqflags);
1198 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1199 mod_timer(&host->cmd11_timer,
1200 jiffies + msecs_to_jiffies(500) + 1);
1201 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1205 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1207 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1210 static void dw_mci_start_request(struct dw_mci *host,
1211 struct dw_mci_slot *slot)
1213 struct mmc_request *mrq = slot->mrq;
1214 struct mmc_command *cmd;
1216 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1217 __dw_mci_start_request(host, slot, cmd);
1220 /* must be called with host->lock held */
1221 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1222 struct mmc_request *mrq)
1224 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1229 if (host->state == STATE_WAITING_CMD11_DONE) {
1230 dev_warn(&slot->mmc->class_dev,
1231 "Voltage change didn't complete\n");
1233 * this case isn't expected to happen, so we can
1234 * either crash here or just try to continue on
1235 * in the closest possible state
1237 host->state = STATE_IDLE;
1240 if (host->state == STATE_IDLE) {
1241 host->state = STATE_SENDING_CMD;
1242 dw_mci_start_request(host, slot);
1244 list_add_tail(&slot->queue_node, &host->queue);
1248 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1250 struct dw_mci_slot *slot = mmc_priv(mmc);
1251 struct dw_mci *host = slot->host;
1256 * The check for card presence and queueing of the request must be
1257 * atomic, otherwise the card could be removed in between and the
1258 * request wouldn't fail until another card was inserted.
1261 if (!dw_mci_get_cd(mmc)) {
1262 mrq->cmd->error = -ENOMEDIUM;
1263 mmc_request_done(mmc, mrq);
1267 spin_lock_bh(&host->lock);
1269 dw_mci_queue_request(host, slot, mrq);
1271 spin_unlock_bh(&host->lock);
1274 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1276 struct dw_mci_slot *slot = mmc_priv(mmc);
1277 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1281 switch (ios->bus_width) {
1282 case MMC_BUS_WIDTH_4:
1283 slot->ctype = SDMMC_CTYPE_4BIT;
1285 case MMC_BUS_WIDTH_8:
1286 slot->ctype = SDMMC_CTYPE_8BIT;
1289 /* set default 1 bit mode */
1290 slot->ctype = SDMMC_CTYPE_1BIT;
1293 regs = mci_readl(slot->host, UHS_REG);
1296 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1297 ios->timing == MMC_TIMING_UHS_DDR50 ||
1298 ios->timing == MMC_TIMING_MMC_HS400)
1299 regs |= ((0x1 << slot->id) << 16);
1301 regs &= ~((0x1 << slot->id) << 16);
1303 mci_writel(slot->host, UHS_REG, regs);
1304 slot->host->timing = ios->timing;
1307 * Use mirror of ios->clock to prevent race with mmc
1308 * core ios update when finding the minimum.
1310 slot->clock = ios->clock;
1312 if (drv_data && drv_data->set_ios)
1313 drv_data->set_ios(slot->host, ios);
1315 switch (ios->power_mode) {
1317 if (!IS_ERR(mmc->supply.vmmc)) {
1318 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1321 dev_err(slot->host->dev,
1322 "failed to enable vmmc regulator\n");
1323 /*return, if failed turn on vmmc*/
1327 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1328 regs = mci_readl(slot->host, PWREN);
1329 regs |= (1 << slot->id);
1330 mci_writel(slot->host, PWREN, regs);
1333 if (!slot->host->vqmmc_enabled) {
1334 if (!IS_ERR(mmc->supply.vqmmc)) {
1335 ret = regulator_enable(mmc->supply.vqmmc);
1337 dev_err(slot->host->dev,
1338 "failed to enable vqmmc\n");
1340 slot->host->vqmmc_enabled = true;
1343 /* Keep track so we don't reset again */
1344 slot->host->vqmmc_enabled = true;
1347 /* Reset our state machine after powering on */
1348 dw_mci_ctrl_reset(slot->host,
1349 SDMMC_CTRL_ALL_RESET_FLAGS);
1352 /* Adjust clock / bus width after power is up */
1353 dw_mci_setup_bus(slot, false);
1357 /* Turn clock off before power goes down */
1358 dw_mci_setup_bus(slot, false);
1360 if (!IS_ERR(mmc->supply.vmmc))
1361 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1363 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1364 regulator_disable(mmc->supply.vqmmc);
1365 slot->host->vqmmc_enabled = false;
1367 regs = mci_readl(slot->host, PWREN);
1368 regs &= ~(1 << slot->id);
1369 mci_writel(slot->host, PWREN, regs);
1375 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1376 slot->host->state = STATE_IDLE;
1379 static int dw_mci_card_busy(struct mmc_host *mmc)
1381 struct dw_mci_slot *slot = mmc_priv(mmc);
1385 * Check the busy bit which is low when DAT[3:0]
1386 * (the data lines) are 0000
1388 status = mci_readl(slot->host, STATUS);
1390 return !!(status & SDMMC_STATUS_BUSY);
1393 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1395 struct dw_mci_slot *slot = mmc_priv(mmc);
1396 struct dw_mci *host = slot->host;
1397 const struct dw_mci_drv_data *drv_data = host->drv_data;
1399 u32 v18 = SDMMC_UHS_18V << slot->id;
1402 if (drv_data && drv_data->switch_voltage)
1403 return drv_data->switch_voltage(mmc, ios);
1406 * Program the voltage. Note that some instances of dw_mmc may use
1407 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1408 * does no harm but you need to set the regulator directly. Try both.
1410 uhs = mci_readl(host, UHS_REG);
1411 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1416 if (!IS_ERR(mmc->supply.vqmmc)) {
1417 ret = mmc_regulator_set_vqmmc(mmc, ios);
1420 dev_dbg(&mmc->class_dev,
1421 "Regulator set error %d - %s V\n",
1422 ret, uhs & v18 ? "1.8" : "3.3");
1426 mci_writel(host, UHS_REG, uhs);
1431 static int dw_mci_get_ro(struct mmc_host *mmc)
1434 struct dw_mci_slot *slot = mmc_priv(mmc);
1435 int gpio_ro = mmc_gpio_get_ro(mmc);
1437 /* Use platform get_ro function, else try on board write protect */
1438 if (!IS_ERR_VALUE(gpio_ro))
1439 read_only = gpio_ro;
1442 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1444 dev_dbg(&mmc->class_dev, "card is %s\n",
1445 read_only ? "read-only" : "read-write");
1450 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1452 struct dw_mci_slot *slot = mmc_priv(mmc);
1453 struct dw_mci *host = slot->host;
1455 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1458 spin_lock_bh(&host->lock);
1461 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1463 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1465 spin_unlock_bh(&host->lock);
1467 mmc_detect_change(slot->mmc, 20);
1472 static int dw_mci_get_cd(struct mmc_host *mmc)
1475 struct dw_mci_slot *slot = mmc_priv(mmc);
1476 struct dw_mci_board *brd = slot->host->pdata;
1477 struct dw_mci *host = slot->host;
1478 int gpio_cd = mmc_gpio_get_cd(mmc);
1480 /* Use platform get_cd function, else try onboard card detect */
1481 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1482 (mmc->caps & MMC_CAP_NONREMOVABLE))
1484 else if (!IS_ERR_VALUE(gpio_cd))
1487 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1490 spin_lock_bh(&host->lock);
1492 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1493 dev_dbg(&mmc->class_dev, "card is present\n");
1495 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1496 dev_dbg(&mmc->class_dev, "card is not present\n");
1498 spin_unlock_bh(&host->lock);
1503 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1505 struct dw_mci_slot *slot = mmc_priv(mmc);
1506 struct dw_mci *host = slot->host;
1509 * Low power mode will stop the card clock when idle. According to the
1510 * description of the CLKENA register we should disable low power mode
1511 * for SDIO cards if we need SDIO interrupts to work.
1513 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1514 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1518 clk_en_a_old = mci_readl(host, CLKENA);
1520 if (card->type == MMC_TYPE_SDIO ||
1521 card->type == MMC_TYPE_SD_COMBO) {
1522 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1523 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1525 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1526 clk_en_a = clk_en_a_old | clken_low_pwr;
1529 if (clk_en_a != clk_en_a_old) {
1530 mci_writel(host, CLKENA, clk_en_a);
1531 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1532 SDMMC_CMD_PRV_DAT_WAIT, 0);
1537 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1539 struct dw_mci_slot *slot = mmc_priv(mmc);
1540 struct dw_mci *host = slot->host;
1541 unsigned long irqflags;
1544 spin_lock_irqsave(&host->irq_lock, irqflags);
1546 /* Enable/disable Slot Specific SDIO interrupt */
1547 int_mask = mci_readl(host, INTMASK);
1549 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1551 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1552 mci_writel(host, INTMASK, int_mask);
1554 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1557 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1559 struct dw_mci_slot *slot = mmc_priv(mmc);
1560 struct dw_mci *host = slot->host;
1561 const struct dw_mci_drv_data *drv_data = host->drv_data;
1564 if (drv_data && drv_data->execute_tuning)
1565 err = drv_data->execute_tuning(slot, opcode);
1569 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1570 struct mmc_ios *ios)
1572 struct dw_mci_slot *slot = mmc_priv(mmc);
1573 struct dw_mci *host = slot->host;
1574 const struct dw_mci_drv_data *drv_data = host->drv_data;
1576 if (drv_data && drv_data->prepare_hs400_tuning)
1577 return drv_data->prepare_hs400_tuning(host, ios);
1582 static const struct mmc_host_ops dw_mci_ops = {
1583 .request = dw_mci_request,
1584 .pre_req = dw_mci_pre_req,
1585 .post_req = dw_mci_post_req,
1586 .set_ios = dw_mci_set_ios,
1587 .set_sdio_status = dw_mci_set_sdio_status,
1588 .get_ro = dw_mci_get_ro,
1589 .get_cd = dw_mci_get_cd,
1590 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1591 .execute_tuning = dw_mci_execute_tuning,
1592 .card_busy = dw_mci_card_busy,
1593 .start_signal_voltage_switch = dw_mci_switch_voltage,
1594 .init_card = dw_mci_init_card,
1595 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1598 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1599 __releases(&host->lock)
1600 __acquires(&host->lock)
1602 struct dw_mci_slot *slot;
1603 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1605 WARN_ON(host->cmd || host->data);
1607 host->cur_slot->mrq = NULL;
1609 if (!list_empty(&host->queue)) {
1610 slot = list_entry(host->queue.next,
1611 struct dw_mci_slot, queue_node);
1612 list_del(&slot->queue_node);
1613 dev_vdbg(host->dev, "list not empty: %s is next\n",
1614 mmc_hostname(slot->mmc));
1615 host->state = STATE_SENDING_CMD;
1616 dw_mci_start_request(host, slot);
1618 dev_vdbg(host->dev, "list empty\n");
1620 if (host->state == STATE_SENDING_CMD11)
1621 host->state = STATE_WAITING_CMD11_DONE;
1623 host->state = STATE_IDLE;
1626 spin_unlock(&host->lock);
1627 mmc_request_done(prev_mmc, mrq);
1628 spin_lock(&host->lock);
1631 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1633 u32 status = host->cmd_status;
1635 host->cmd_status = 0;
1637 /* Read the response from the card (up to 16 bytes) */
1638 if (cmd->flags & MMC_RSP_PRESENT) {
1639 if (cmd->flags & MMC_RSP_136) {
1640 cmd->resp[3] = mci_readl(host, RESP0);
1641 cmd->resp[2] = mci_readl(host, RESP1);
1642 cmd->resp[1] = mci_readl(host, RESP2);
1643 cmd->resp[0] = mci_readl(host, RESP3);
1645 cmd->resp[0] = mci_readl(host, RESP0);
1652 if (status & SDMMC_INT_RTO)
1653 cmd->error = -ETIMEDOUT;
1654 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1655 cmd->error = -EILSEQ;
1656 else if (status & SDMMC_INT_RESP_ERR)
1662 /* newer ip versions need a delay between retries */
1663 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1670 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1672 u32 status = host->data_status;
1674 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1675 if (status & SDMMC_INT_DRTO) {
1676 data->error = -ETIMEDOUT;
1677 } else if (status & SDMMC_INT_DCRC) {
1678 data->error = -EILSEQ;
1679 } else if (status & SDMMC_INT_EBE) {
1680 if (host->dir_status ==
1681 DW_MCI_SEND_STATUS) {
1683 * No data CRC status was returned.
1684 * The number of bytes transferred
1685 * will be exaggerated in PIO mode.
1687 data->bytes_xfered = 0;
1688 data->error = -ETIMEDOUT;
1689 } else if (host->dir_status ==
1690 DW_MCI_RECV_STATUS) {
1694 /* SDMMC_INT_SBE is included */
1698 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1701 * After an error, there may be data lingering
1706 data->bytes_xfered = data->blocks * data->blksz;
1713 static void dw_mci_set_drto(struct dw_mci *host)
1715 unsigned int drto_clks;
1716 unsigned int drto_ms;
1718 drto_clks = mci_readl(host, TMOUT) >> 8;
1719 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1721 /* add a bit spare time */
1724 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1727 static void dw_mci_tasklet_func(unsigned long priv)
1729 struct dw_mci *host = (struct dw_mci *)priv;
1730 struct mmc_data *data;
1731 struct mmc_command *cmd;
1732 struct mmc_request *mrq;
1733 enum dw_mci_state state;
1734 enum dw_mci_state prev_state;
1737 spin_lock(&host->lock);
1739 state = host->state;
1748 case STATE_WAITING_CMD11_DONE:
1751 case STATE_SENDING_CMD11:
1752 case STATE_SENDING_CMD:
1753 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1754 &host->pending_events))
1759 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1760 err = dw_mci_command_complete(host, cmd);
1761 if (cmd == mrq->sbc && !err) {
1762 prev_state = state = STATE_SENDING_CMD;
1763 __dw_mci_start_request(host, host->cur_slot,
1768 if (cmd->data && err) {
1770 * Controller will move into a data transfer
1771 * state after a response error or response CRC
1772 * error. Let's let that finish before trying
1773 * to send a stop, so we'll go to
1774 * STATE_SENDING_DATA.
1776 * Although letting the data transfer take place
1777 * will waste a bit of time (we already know
1778 * the command was bad), it can't cause any
1779 * errors since it's possible it would have
1780 * taken place anyway if this tasklet got
1781 * delayed. Allowing the transfer to take place
1782 * avoids races and keeps things simple.
1784 if (err != -ETIMEDOUT) {
1785 state = STATE_SENDING_DATA;
1789 dw_mci_stop_dma(host);
1790 send_stop_abort(host, data);
1791 state = STATE_SENDING_STOP;
1795 if (!cmd->data || err) {
1796 dw_mci_request_end(host, mrq);
1800 prev_state = state = STATE_SENDING_DATA;
1803 case STATE_SENDING_DATA:
1805 * We could get a data error and never a transfer
1806 * complete so we'd better check for it here.
1808 * Note that we don't really care if we also got a
1809 * transfer complete; stopping the DMA and sending an
1812 if (test_and_clear_bit(EVENT_DATA_ERROR,
1813 &host->pending_events)) {
1814 dw_mci_stop_dma(host);
1816 !(host->data_status & (SDMMC_INT_DRTO |
1818 send_stop_abort(host, data);
1819 state = STATE_DATA_ERROR;
1823 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1824 &host->pending_events)) {
1826 * If all data-related interrupts don't come
1827 * within the given time in reading data state.
1829 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1830 (host->dir_status == DW_MCI_RECV_STATUS))
1831 dw_mci_set_drto(host);
1835 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1838 * Handle an EVENT_DATA_ERROR that might have shown up
1839 * before the transfer completed. This might not have
1840 * been caught by the check above because the interrupt
1841 * could have gone off between the previous check and
1842 * the check for transfer complete.
1844 * Technically this ought not be needed assuming we
1845 * get a DATA_COMPLETE eventually (we'll notice the
1846 * error and end the request), but it shouldn't hurt.
1848 * This has the advantage of sending the stop command.
1850 if (test_and_clear_bit(EVENT_DATA_ERROR,
1851 &host->pending_events)) {
1852 dw_mci_stop_dma(host);
1854 !(host->data_status & (SDMMC_INT_DRTO |
1856 send_stop_abort(host, data);
1857 state = STATE_DATA_ERROR;
1860 prev_state = state = STATE_DATA_BUSY;
1864 case STATE_DATA_BUSY:
1865 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1866 &host->pending_events)) {
1868 * If data error interrupt comes but data over
1869 * interrupt doesn't come within the given time.
1870 * in reading data state.
1872 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1873 (host->dir_status == DW_MCI_RECV_STATUS))
1874 dw_mci_set_drto(host);
1879 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1880 err = dw_mci_data_complete(host, data);
1883 if (!data->stop || mrq->sbc) {
1884 if (mrq->sbc && data->stop)
1885 data->stop->error = 0;
1886 dw_mci_request_end(host, mrq);
1890 /* stop command for open-ended transfer*/
1892 send_stop_abort(host, data);
1895 * If we don't have a command complete now we'll
1896 * never get one since we just reset everything;
1897 * better end the request.
1899 * If we do have a command complete we'll fall
1900 * through to the SENDING_STOP command and
1901 * everything will be peachy keen.
1903 if (!test_bit(EVENT_CMD_COMPLETE,
1904 &host->pending_events)) {
1906 dw_mci_request_end(host, mrq);
1912 * If err has non-zero,
1913 * stop-abort command has been already issued.
1915 prev_state = state = STATE_SENDING_STOP;
1919 case STATE_SENDING_STOP:
1920 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1921 &host->pending_events))
1924 /* CMD error in data command */
1925 if (mrq->cmd->error && mrq->data)
1932 dw_mci_command_complete(host, mrq->stop);
1934 host->cmd_status = 0;
1936 dw_mci_request_end(host, mrq);
1939 case STATE_DATA_ERROR:
1940 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1941 &host->pending_events))
1944 state = STATE_DATA_BUSY;
1947 } while (state != prev_state);
1949 host->state = state;
1951 spin_unlock(&host->lock);
1955 /* push final bytes to part_buf, only use during push */
1956 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1958 memcpy((void *)&host->part_buf, buf, cnt);
1959 host->part_buf_count = cnt;
1962 /* append bytes to part_buf, only use during push */
1963 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1965 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1966 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1967 host->part_buf_count += cnt;
1971 /* pull first bytes from part_buf, only use during pull */
1972 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1974 cnt = min_t(int, cnt, host->part_buf_count);
1976 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1978 host->part_buf_count -= cnt;
1979 host->part_buf_start += cnt;
1984 /* pull final bytes from the part_buf, assuming it's just been filled */
1985 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1987 memcpy(buf, &host->part_buf, cnt);
1988 host->part_buf_start = cnt;
1989 host->part_buf_count = (1 << host->data_shift) - cnt;
1992 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1994 struct mmc_data *data = host->data;
1997 /* try and push anything in the part_buf */
1998 if (unlikely(host->part_buf_count)) {
1999 int len = dw_mci_push_part_bytes(host, buf, cnt);
2003 if (host->part_buf_count == 2) {
2004 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2005 host->part_buf_count = 0;
2008 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2009 if (unlikely((unsigned long)buf & 0x1)) {
2011 u16 aligned_buf[64];
2012 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2013 int items = len >> 1;
2015 /* memcpy from input buffer into aligned buffer */
2016 memcpy(aligned_buf, buf, len);
2019 /* push data from aligned buffer into fifo */
2020 for (i = 0; i < items; ++i)
2021 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2028 for (; cnt >= 2; cnt -= 2)
2029 mci_fifo_writew(host->fifo_reg, *pdata++);
2032 /* put anything remaining in the part_buf */
2034 dw_mci_set_part_bytes(host, buf, cnt);
2035 /* Push data if we have reached the expected data length */
2036 if ((data->bytes_xfered + init_cnt) ==
2037 (data->blksz * data->blocks))
2038 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2042 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2044 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2045 if (unlikely((unsigned long)buf & 0x1)) {
2047 /* pull data from fifo into aligned buffer */
2048 u16 aligned_buf[64];
2049 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2050 int items = len >> 1;
2053 for (i = 0; i < items; ++i)
2054 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2055 /* memcpy from aligned buffer into output buffer */
2056 memcpy(buf, aligned_buf, len);
2065 for (; cnt >= 2; cnt -= 2)
2066 *pdata++ = mci_fifo_readw(host->fifo_reg);
2070 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2071 dw_mci_pull_final_bytes(host, buf, cnt);
2075 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2077 struct mmc_data *data = host->data;
2080 /* try and push anything in the part_buf */
2081 if (unlikely(host->part_buf_count)) {
2082 int len = dw_mci_push_part_bytes(host, buf, cnt);
2086 if (host->part_buf_count == 4) {
2087 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2088 host->part_buf_count = 0;
2091 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2092 if (unlikely((unsigned long)buf & 0x3)) {
2094 u32 aligned_buf[32];
2095 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2096 int items = len >> 2;
2098 /* memcpy from input buffer into aligned buffer */
2099 memcpy(aligned_buf, buf, len);
2102 /* push data from aligned buffer into fifo */
2103 for (i = 0; i < items; ++i)
2104 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2111 for (; cnt >= 4; cnt -= 4)
2112 mci_fifo_writel(host->fifo_reg, *pdata++);
2115 /* put anything remaining in the part_buf */
2117 dw_mci_set_part_bytes(host, buf, cnt);
2118 /* Push data if we have reached the expected data length */
2119 if ((data->bytes_xfered + init_cnt) ==
2120 (data->blksz * data->blocks))
2121 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2125 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2127 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2128 if (unlikely((unsigned long)buf & 0x3)) {
2130 /* pull data from fifo into aligned buffer */
2131 u32 aligned_buf[32];
2132 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2133 int items = len >> 2;
2136 for (i = 0; i < items; ++i)
2137 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2138 /* memcpy from aligned buffer into output buffer */
2139 memcpy(buf, aligned_buf, len);
2148 for (; cnt >= 4; cnt -= 4)
2149 *pdata++ = mci_fifo_readl(host->fifo_reg);
2153 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2154 dw_mci_pull_final_bytes(host, buf, cnt);
2158 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2160 struct mmc_data *data = host->data;
2163 /* try and push anything in the part_buf */
2164 if (unlikely(host->part_buf_count)) {
2165 int len = dw_mci_push_part_bytes(host, buf, cnt);
2170 if (host->part_buf_count == 8) {
2171 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2172 host->part_buf_count = 0;
2175 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2176 if (unlikely((unsigned long)buf & 0x7)) {
2178 u64 aligned_buf[16];
2179 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2180 int items = len >> 3;
2182 /* memcpy from input buffer into aligned buffer */
2183 memcpy(aligned_buf, buf, len);
2186 /* push data from aligned buffer into fifo */
2187 for (i = 0; i < items; ++i)
2188 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2195 for (; cnt >= 8; cnt -= 8)
2196 mci_fifo_writeq(host->fifo_reg, *pdata++);
2199 /* put anything remaining in the part_buf */
2201 dw_mci_set_part_bytes(host, buf, cnt);
2202 /* Push data if we have reached the expected data length */
2203 if ((data->bytes_xfered + init_cnt) ==
2204 (data->blksz * data->blocks))
2205 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2209 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2211 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2212 if (unlikely((unsigned long)buf & 0x7)) {
2214 /* pull data from fifo into aligned buffer */
2215 u64 aligned_buf[16];
2216 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2217 int items = len >> 3;
2220 for (i = 0; i < items; ++i)
2221 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2223 /* memcpy from aligned buffer into output buffer */
2224 memcpy(buf, aligned_buf, len);
2233 for (; cnt >= 8; cnt -= 8)
2234 *pdata++ = mci_fifo_readq(host->fifo_reg);
2238 host->part_buf = mci_fifo_readq(host->fifo_reg);
2239 dw_mci_pull_final_bytes(host, buf, cnt);
2243 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2247 /* get remaining partial bytes */
2248 len = dw_mci_pull_part_bytes(host, buf, cnt);
2249 if (unlikely(len == cnt))
2254 /* get the rest of the data */
2255 host->pull_data(host, buf, cnt);
2258 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2260 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2262 unsigned int offset;
2263 struct mmc_data *data = host->data;
2264 int shift = host->data_shift;
2267 unsigned int remain, fcnt;
2270 if (!sg_miter_next(sg_miter))
2273 host->sg = sg_miter->piter.sg;
2274 buf = sg_miter->addr;
2275 remain = sg_miter->length;
2279 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2280 << shift) + host->part_buf_count;
2281 len = min(remain, fcnt);
2284 dw_mci_pull_data(host, (void *)(buf + offset), len);
2285 data->bytes_xfered += len;
2290 sg_miter->consumed = offset;
2291 status = mci_readl(host, MINTSTS);
2292 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2293 /* if the RXDR is ready read again */
2294 } while ((status & SDMMC_INT_RXDR) ||
2295 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2298 if (!sg_miter_next(sg_miter))
2300 sg_miter->consumed = 0;
2302 sg_miter_stop(sg_miter);
2306 sg_miter_stop(sg_miter);
2308 smp_wmb(); /* drain writebuffer */
2309 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2312 static void dw_mci_write_data_pio(struct dw_mci *host)
2314 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2316 unsigned int offset;
2317 struct mmc_data *data = host->data;
2318 int shift = host->data_shift;
2321 unsigned int fifo_depth = host->fifo_depth;
2322 unsigned int remain, fcnt;
2325 if (!sg_miter_next(sg_miter))
2328 host->sg = sg_miter->piter.sg;
2329 buf = sg_miter->addr;
2330 remain = sg_miter->length;
2334 fcnt = ((fifo_depth -
2335 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2336 << shift) - host->part_buf_count;
2337 len = min(remain, fcnt);
2340 host->push_data(host, (void *)(buf + offset), len);
2341 data->bytes_xfered += len;
2346 sg_miter->consumed = offset;
2347 status = mci_readl(host, MINTSTS);
2348 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2349 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2352 if (!sg_miter_next(sg_miter))
2354 sg_miter->consumed = 0;
2356 sg_miter_stop(sg_miter);
2360 sg_miter_stop(sg_miter);
2362 smp_wmb(); /* drain writebuffer */
2363 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2366 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2368 if (!host->cmd_status)
2369 host->cmd_status = status;
2371 smp_wmb(); /* drain writebuffer */
2373 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2374 tasklet_schedule(&host->tasklet);
2377 static void dw_mci_handle_cd(struct dw_mci *host)
2381 for (i = 0; i < host->num_slots; i++) {
2382 struct dw_mci_slot *slot = host->slot[i];
2387 if (slot->mmc->ops->card_event)
2388 slot->mmc->ops->card_event(slot->mmc);
2389 mmc_detect_change(slot->mmc,
2390 msecs_to_jiffies(host->pdata->detect_delay_ms));
2394 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2396 struct dw_mci *host = dev_id;
2400 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2403 * DTO fix - version 2.10a and below, and only if internal DMA
2406 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2408 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2409 pending |= SDMMC_INT_DATA_OVER;
2413 /* Check volt switch first, since it can look like an error */
2414 if ((host->state == STATE_SENDING_CMD11) &&
2415 (pending & SDMMC_INT_VOLT_SWITCH)) {
2416 unsigned long irqflags;
2418 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2419 pending &= ~SDMMC_INT_VOLT_SWITCH;
2422 * Hold the lock; we know cmd11_timer can't be kicked
2423 * off after the lock is released, so safe to delete.
2425 spin_lock_irqsave(&host->irq_lock, irqflags);
2426 dw_mci_cmd_interrupt(host, pending);
2427 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2429 del_timer(&host->cmd11_timer);
2432 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2433 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2434 host->cmd_status = pending;
2435 smp_wmb(); /* drain writebuffer */
2436 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2439 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2440 /* if there is an error report DATA_ERROR */
2441 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2442 host->data_status = pending;
2443 smp_wmb(); /* drain writebuffer */
2444 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2445 tasklet_schedule(&host->tasklet);
2448 if (pending & SDMMC_INT_DATA_OVER) {
2449 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2450 del_timer(&host->dto_timer);
2452 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2453 if (!host->data_status)
2454 host->data_status = pending;
2455 smp_wmb(); /* drain writebuffer */
2456 if (host->dir_status == DW_MCI_RECV_STATUS) {
2457 if (host->sg != NULL)
2458 dw_mci_read_data_pio(host, true);
2460 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2461 tasklet_schedule(&host->tasklet);
2464 if (pending & SDMMC_INT_RXDR) {
2465 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2466 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2467 dw_mci_read_data_pio(host, false);
2470 if (pending & SDMMC_INT_TXDR) {
2471 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2472 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2473 dw_mci_write_data_pio(host);
2476 if (pending & SDMMC_INT_CMD_DONE) {
2477 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2478 dw_mci_cmd_interrupt(host, pending);
2481 if (pending & SDMMC_INT_CD) {
2482 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2483 dw_mci_handle_cd(host);
2486 /* Handle SDIO Interrupts */
2487 for (i = 0; i < host->num_slots; i++) {
2488 struct dw_mci_slot *slot = host->slot[i];
2493 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2494 mci_writel(host, RINTSTS,
2495 SDMMC_INT_SDIO(slot->sdio_id));
2496 mmc_signal_sdio_irq(slot->mmc);
2502 if (host->use_dma != TRANS_MODE_IDMAC)
2505 /* Handle IDMA interrupts */
2506 if (host->dma_64bit_address == 1) {
2507 pending = mci_readl(host, IDSTS64);
2508 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2509 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2510 SDMMC_IDMAC_INT_RI);
2511 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2512 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2513 host->dma_ops->complete((void *)host);
2516 pending = mci_readl(host, IDSTS);
2517 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2518 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2519 SDMMC_IDMAC_INT_RI);
2520 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2521 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2522 host->dma_ops->complete((void *)host);
2530 /* given a slot, find out the device node representing that slot */
2531 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2533 struct device *dev = slot->mmc->parent;
2534 struct device_node *np;
2538 if (!dev || !dev->of_node)
2541 for_each_child_of_node(dev->of_node, np) {
2542 addr = of_get_property(np, "reg", &len);
2543 if (!addr || (len < sizeof(int)))
2545 if (be32_to_cpup(addr) == slot->id)
2551 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2553 struct device_node *np = dw_mci_of_find_slot_node(slot);
2558 if (of_property_read_bool(np, "disable-wp")) {
2559 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2560 dev_warn(slot->mmc->parent,
2561 "Slot quirk 'disable-wp' is deprecated\n");
2564 #else /* CONFIG_OF */
2565 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2568 #endif /* CONFIG_OF */
2570 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2572 struct mmc_host *mmc;
2573 struct dw_mci_slot *slot;
2574 const struct dw_mci_drv_data *drv_data = host->drv_data;
2578 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2582 slot = mmc_priv(mmc);
2584 slot->sdio_id = host->sdio_id0 + id;
2587 host->slot[id] = slot;
2589 mmc->ops = &dw_mci_ops;
2590 if (of_property_read_u32_array(host->dev->of_node,
2591 "clock-freq-min-max", freq, 2)) {
2592 mmc->f_min = DW_MCI_FREQ_MIN;
2593 mmc->f_max = DW_MCI_FREQ_MAX;
2596 "'clock-freq-min-max' property was deprecated.\n");
2597 mmc->f_min = freq[0];
2598 mmc->f_max = freq[1];
2601 /*if there are external regulators, get them*/
2602 ret = mmc_regulator_get_supply(mmc);
2603 if (ret == -EPROBE_DEFER)
2604 goto err_host_allocated;
2606 if (!mmc->ocr_avail)
2607 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2609 if (host->pdata->caps)
2610 mmc->caps = host->pdata->caps;
2612 if (host->pdata->pm_caps)
2613 mmc->pm_caps = host->pdata->pm_caps;
2615 if (host->dev->of_node) {
2616 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2620 ctrl_id = to_platform_device(host->dev)->id;
2622 if (drv_data && drv_data->caps)
2623 mmc->caps |= drv_data->caps[ctrl_id];
2625 if (host->pdata->caps2)
2626 mmc->caps2 = host->pdata->caps2;
2628 dw_mci_slot_of_parse(slot);
2630 ret = mmc_of_parse(mmc);
2632 goto err_host_allocated;
2634 /* Useful defaults if platform data is unset. */
2635 if (host->use_dma == TRANS_MODE_IDMAC) {
2636 mmc->max_segs = host->ring_size;
2637 mmc->max_blk_size = 65536;
2638 mmc->max_seg_size = 0x1000;
2639 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2640 mmc->max_blk_count = mmc->max_req_size / 512;
2641 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2643 mmc->max_blk_size = 65536;
2644 mmc->max_blk_count = 65535;
2646 mmc->max_blk_size * mmc->max_blk_count;
2647 mmc->max_seg_size = mmc->max_req_size;
2649 /* TRANS_MODE_PIO */
2651 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2652 mmc->max_blk_count = 512;
2653 mmc->max_req_size = mmc->max_blk_size *
2655 mmc->max_seg_size = mmc->max_req_size;
2660 ret = mmc_add_host(mmc);
2662 goto err_host_allocated;
2664 #if defined(CONFIG_DEBUG_FS)
2665 dw_mci_init_debugfs(slot);
2675 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2677 /* Debugfs stuff is cleaned up by mmc core */
2678 mmc_remove_host(slot->mmc);
2679 slot->host->slot[id] = NULL;
2680 mmc_free_host(slot->mmc);
2683 static void dw_mci_init_dma(struct dw_mci *host)
2686 struct device *dev = host->dev;
2687 struct device_node *np = dev->of_node;
2690 * Check tansfer mode from HCON[17:16]
2691 * Clear the ambiguous description of dw_mmc databook:
2692 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2693 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2694 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2695 * 2b'11: Non DW DMA Interface -> pio only
2696 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2697 * simpler request/acknowledge handshake mechanism and both of them
2698 * are regarded as external dma master for dw_mmc.
2700 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2701 if (host->use_dma == DMA_INTERFACE_IDMA) {
2702 host->use_dma = TRANS_MODE_IDMAC;
2703 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2704 host->use_dma == DMA_INTERFACE_GDMA) {
2705 host->use_dma = TRANS_MODE_EDMAC;
2710 /* Determine which DMA interface to use */
2711 if (host->use_dma == TRANS_MODE_IDMAC) {
2713 * Check ADDR_CONFIG bit in HCON to find
2714 * IDMAC address bus width
2716 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2718 if (addr_config == 1) {
2719 /* host supports IDMAC in 64-bit address mode */
2720 host->dma_64bit_address = 1;
2722 "IDMAC supports 64-bit address mode.\n");
2723 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2724 dma_set_coherent_mask(host->dev,
2727 /* host supports IDMAC in 32-bit address mode */
2728 host->dma_64bit_address = 0;
2730 "IDMAC supports 32-bit address mode.\n");
2733 /* Alloc memory for sg translation */
2734 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2735 &host->sg_dma, GFP_KERNEL);
2736 if (!host->sg_cpu) {
2738 "%s: could not alloc DMA memory\n",
2743 host->dma_ops = &dw_mci_idmac_ops;
2744 dev_info(host->dev, "Using internal DMA controller.\n");
2746 /* TRANS_MODE_EDMAC: check dma bindings again */
2747 if ((of_property_count_strings(np, "dma-names") < 0) ||
2748 (!of_find_property(np, "dmas", NULL))) {
2751 host->dma_ops = &dw_mci_edmac_ops;
2752 dev_info(host->dev, "Using external DMA controller.\n");
2755 if (host->dma_ops->init && host->dma_ops->start &&
2756 host->dma_ops->stop && host->dma_ops->cleanup) {
2757 if (host->dma_ops->init(host)) {
2758 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2763 dev_err(host->dev, "DMA initialization not found.\n");
2770 dev_info(host->dev, "Using PIO mode.\n");
2771 host->use_dma = TRANS_MODE_PIO;
2774 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2776 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2779 ctrl = mci_readl(host, CTRL);
2781 mci_writel(host, CTRL, ctrl);
2783 /* wait till resets clear */
2785 ctrl = mci_readl(host, CTRL);
2786 if (!(ctrl & reset))
2788 } while (time_before(jiffies, timeout));
2791 "Timeout resetting block (ctrl reset %#x)\n",
2797 static bool dw_mci_reset(struct dw_mci *host)
2799 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2803 * Reseting generates a block interrupt, hence setting
2804 * the scatter-gather pointer to NULL.
2807 sg_miter_stop(&host->sg_miter);
2812 flags |= SDMMC_CTRL_DMA_RESET;
2814 if (dw_mci_ctrl_reset(host, flags)) {
2816 * In all cases we clear the RAWINTS register to clear any
2819 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2821 /* if using dma we wait for dma_req to clear */
2822 if (host->use_dma) {
2823 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2827 status = mci_readl(host, STATUS);
2828 if (!(status & SDMMC_STATUS_DMA_REQ))
2831 } while (time_before(jiffies, timeout));
2833 if (status & SDMMC_STATUS_DMA_REQ) {
2835 "%s: Timeout waiting for dma_req to clear during reset\n",
2840 /* when using DMA next we reset the fifo again */
2841 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2845 /* if the controller reset bit did clear, then set clock regs */
2846 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2848 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2854 if (host->use_dma == TRANS_MODE_IDMAC)
2855 /* It is also recommended that we reset and reprogram idmac */
2856 dw_mci_idmac_reset(host);
2861 /* After a CTRL reset we need to have CIU set clock registers */
2862 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2867 static void dw_mci_cmd11_timer(unsigned long arg)
2869 struct dw_mci *host = (struct dw_mci *)arg;
2871 if (host->state != STATE_SENDING_CMD11) {
2872 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2876 host->cmd_status = SDMMC_INT_RTO;
2877 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2878 tasklet_schedule(&host->tasklet);
2881 static void dw_mci_dto_timer(unsigned long arg)
2883 struct dw_mci *host = (struct dw_mci *)arg;
2885 switch (host->state) {
2886 case STATE_SENDING_DATA:
2887 case STATE_DATA_BUSY:
2889 * If DTO interrupt does NOT come in sending data state,
2890 * we should notify the driver to terminate current transfer
2891 * and report a data timeout to the core.
2893 host->data_status = SDMMC_INT_DRTO;
2894 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2895 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2896 tasklet_schedule(&host->tasklet);
2904 static struct dw_mci_of_quirks {
2909 .quirk = "broken-cd",
2910 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2914 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2916 struct dw_mci_board *pdata;
2917 struct device *dev = host->dev;
2918 struct device_node *np = dev->of_node;
2919 const struct dw_mci_drv_data *drv_data = host->drv_data;
2921 u32 clock_frequency;
2923 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2925 return ERR_PTR(-ENOMEM);
2927 /* find out number of slots supported */
2928 if (of_property_read_u32(dev->of_node, "num-slots",
2929 &pdata->num_slots)) {
2931 "num-slots property not found, assuming 1 slot is available\n");
2932 pdata->num_slots = 1;
2936 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2937 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2938 pdata->quirks |= of_quirks[idx].id;
2940 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2942 "fifo-depth property not found, using value of FIFOTH register as default\n");
2944 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2946 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2947 pdata->bus_hz = clock_frequency;
2949 if (drv_data && drv_data->parse_dt) {
2950 ret = drv_data->parse_dt(host);
2952 return ERR_PTR(ret);
2955 if (of_find_property(np, "supports-highspeed", NULL)) {
2956 dev_info(dev, "supports-highspeed property is deprecated.\n");
2957 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2963 #else /* CONFIG_OF */
2964 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2966 return ERR_PTR(-EINVAL);
2968 #endif /* CONFIG_OF */
2970 static void dw_mci_enable_cd(struct dw_mci *host)
2972 struct dw_mci_board *brd = host->pdata;
2973 unsigned long irqflags;
2977 /* No need for CD if broken card detection */
2978 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2981 /* No need for CD if all slots have a non-error GPIO */
2982 for (i = 0; i < host->num_slots; i++) {
2983 struct dw_mci_slot *slot = host->slot[i];
2985 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2988 if (i == host->num_slots)
2991 spin_lock_irqsave(&host->irq_lock, irqflags);
2992 temp = mci_readl(host, INTMASK);
2993 temp |= SDMMC_INT_CD;
2994 mci_writel(host, INTMASK, temp);
2995 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2998 int dw_mci_probe(struct dw_mci *host)
3000 const struct dw_mci_drv_data *drv_data = host->drv_data;
3001 int width, i, ret = 0;
3006 host->pdata = dw_mci_parse_dt(host);
3007 if (IS_ERR(host->pdata)) {
3008 dev_err(host->dev, "platform data not available\n");
3013 if (host->pdata->num_slots < 1) {
3015 "Platform data must supply num_slots.\n");
3019 host->biu_clk = devm_clk_get(host->dev, "biu");
3020 if (IS_ERR(host->biu_clk)) {
3021 dev_dbg(host->dev, "biu clock not available\n");
3023 ret = clk_prepare_enable(host->biu_clk);
3025 dev_err(host->dev, "failed to enable biu clock\n");
3030 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3031 if (IS_ERR(host->ciu_clk)) {
3032 dev_dbg(host->dev, "ciu clock not available\n");
3033 host->bus_hz = host->pdata->bus_hz;
3035 ret = clk_prepare_enable(host->ciu_clk);
3037 dev_err(host->dev, "failed to enable ciu clock\n");
3041 if (host->pdata->bus_hz) {
3042 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3045 "Unable to set bus rate to %uHz\n",
3046 host->pdata->bus_hz);
3048 host->bus_hz = clk_get_rate(host->ciu_clk);
3051 if (!host->bus_hz) {
3053 "Platform data must supply bus speed\n");
3058 if (drv_data && drv_data->init) {
3059 ret = drv_data->init(host);
3062 "implementation specific init failed\n");
3067 if (drv_data && drv_data->setup_clock) {
3068 ret = drv_data->setup_clock(host);
3071 "implementation specific clock setup failed\n");
3076 setup_timer(&host->cmd11_timer,
3077 dw_mci_cmd11_timer, (unsigned long)host);
3079 host->quirks = host->pdata->quirks;
3081 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3082 setup_timer(&host->dto_timer,
3083 dw_mci_dto_timer, (unsigned long)host);
3085 spin_lock_init(&host->lock);
3086 spin_lock_init(&host->irq_lock);
3087 INIT_LIST_HEAD(&host->queue);
3090 * Get the host data width - this assumes that HCON has been set with
3091 * the correct values.
3093 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3095 host->push_data = dw_mci_push_data16;
3096 host->pull_data = dw_mci_pull_data16;
3098 host->data_shift = 1;
3099 } else if (i == 2) {
3100 host->push_data = dw_mci_push_data64;
3101 host->pull_data = dw_mci_pull_data64;
3103 host->data_shift = 3;
3105 /* Check for a reserved value, and warn if it is */
3107 "HCON reports a reserved host data width!\n"
3108 "Defaulting to 32-bit access.\n");
3109 host->push_data = dw_mci_push_data32;
3110 host->pull_data = dw_mci_pull_data32;
3112 host->data_shift = 2;
3115 /* Reset all blocks */
3116 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
3119 host->dma_ops = host->pdata->dma_ops;
3120 dw_mci_init_dma(host);
3122 /* Clear the interrupts for the host controller */
3123 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3124 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3126 /* Put in max timeout */
3127 mci_writel(host, TMOUT, 0xFFFFFFFF);
3130 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3131 * Tx Mark = fifo_size / 2 DMA Size = 8
3133 if (!host->pdata->fifo_depth) {
3135 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3136 * have been overwritten by the bootloader, just like we're
3137 * about to do, so if you know the value for your hardware, you
3138 * should put it in the platform data.
3140 fifo_size = mci_readl(host, FIFOTH);
3141 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3143 fifo_size = host->pdata->fifo_depth;
3145 host->fifo_depth = fifo_size;
3147 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3148 mci_writel(host, FIFOTH, host->fifoth_val);
3150 /* disable clock to CIU */
3151 mci_writel(host, CLKENA, 0);
3152 mci_writel(host, CLKSRC, 0);
3155 * In 2.40a spec, Data offset is changed.
3156 * Need to check the version-id and set data-offset for DATA register.
3158 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3159 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3161 if (host->verid < DW_MMC_240A)
3162 host->fifo_reg = host->regs + DATA_OFFSET;
3164 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3166 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3167 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3168 host->irq_flags, "dw-mci", host);
3172 if (host->pdata->num_slots)
3173 host->num_slots = host->pdata->num_slots;
3175 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
3178 * Enable interrupts for command done, data over, data empty,
3179 * receive ready and error such as transmit, receive timeout, crc error
3181 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3182 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3183 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3184 DW_MCI_ERROR_FLAGS);
3185 /* Enable mci interrupt */
3186 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3189 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3190 host->irq, width, fifo_size);
3192 /* We need at least one slot to succeed */
3193 for (i = 0; i < host->num_slots; i++) {
3194 ret = dw_mci_init_slot(host, i);
3196 dev_dbg(host->dev, "slot %d init failed\n", i);
3202 dev_info(host->dev, "%d slots initialized\n", init_slots);
3205 "attempted to initialize %d slots, but failed on all\n",
3210 /* Now that slots are all setup, we can enable card detect */
3211 dw_mci_enable_cd(host);
3213 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3214 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3219 if (host->use_dma && host->dma_ops->exit)
3220 host->dma_ops->exit(host);
3223 if (!IS_ERR(host->ciu_clk))
3224 clk_disable_unprepare(host->ciu_clk);
3227 if (!IS_ERR(host->biu_clk))
3228 clk_disable_unprepare(host->biu_clk);
3232 EXPORT_SYMBOL(dw_mci_probe);
3234 void dw_mci_remove(struct dw_mci *host)
3238 for (i = 0; i < host->num_slots; i++) {
3239 dev_dbg(host->dev, "remove slot %d\n", i);
3241 dw_mci_cleanup_slot(host->slot[i], i);
3244 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3245 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3247 /* disable clock to CIU */
3248 mci_writel(host, CLKENA, 0);
3249 mci_writel(host, CLKSRC, 0);
3251 if (host->use_dma && host->dma_ops->exit)
3252 host->dma_ops->exit(host);
3254 if (!IS_ERR(host->ciu_clk))
3255 clk_disable_unprepare(host->ciu_clk);
3257 if (!IS_ERR(host->biu_clk))
3258 clk_disable_unprepare(host->biu_clk);
3260 EXPORT_SYMBOL(dw_mci_remove);
3264 #ifdef CONFIG_PM_SLEEP
3266 * TODO: we should probably disable the clock to the card in the suspend path.
3268 int dw_mci_suspend(struct dw_mci *host)
3270 if (host->use_dma && host->dma_ops->exit)
3271 host->dma_ops->exit(host);
3275 EXPORT_SYMBOL(dw_mci_suspend);
3277 int dw_mci_resume(struct dw_mci *host)
3281 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3286 if (host->use_dma && host->dma_ops->init)
3287 host->dma_ops->init(host);
3290 * Restore the initial value at FIFOTH register
3291 * And Invalidate the prev_blksz with zero
3293 mci_writel(host, FIFOTH, host->fifoth_val);
3294 host->prev_blksz = 0;
3296 /* Put in max timeout */
3297 mci_writel(host, TMOUT, 0xFFFFFFFF);
3299 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3300 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3301 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3302 DW_MCI_ERROR_FLAGS);
3303 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3305 for (i = 0; i < host->num_slots; i++) {
3306 struct dw_mci_slot *slot = host->slot[i];
3310 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3311 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3312 dw_mci_setup_bus(slot, true);
3316 /* Now that slots are all setup, we can enable card detect */
3317 dw_mci_enable_cd(host);
3321 EXPORT_SYMBOL(dw_mci_resume);
3322 #endif /* CONFIG_PM_SLEEP */
3324 static int __init dw_mci_init(void)
3326 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3330 static void __exit dw_mci_exit(void)
3334 module_init(dw_mci_init);
3335 module_exit(dw_mci_exit);
3337 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3338 MODULE_AUTHOR("NXP Semiconductor VietNam");
3339 MODULE_AUTHOR("Imagination Technologies Ltd");
3340 MODULE_LICENSE("GPL v2");