drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/slab.h>
  28 #include <linux/stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/irq.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/dw_mmc.h>
  34 #include <linux/bitops.h>
  35
  36 #include "dw_mmc.h"
  37
  38 /* Common flag combinations */
  39 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  40                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  41                                  SDMMC_INT_EBE)
  42 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  43                                  SDMMC_INT_RESP_ERR)
  44 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  45                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  46 #define DW_MCI_SEND_STATUS      1
  47 #define DW_MCI_RECV_STATUS      2
  48 #define DW_MCI_DMA_THRESHOLD    16
  49
  50 #ifdef CONFIG_MMC_DW_IDMAC
  51 struct idmac_desc {
  52         u32             des0;   /* Control Descriptor */
  53 #define IDMAC_DES0_DIC  BIT(1)
  54 #define IDMAC_DES0_LD   BIT(2)
  55 #define IDMAC_DES0_FD   BIT(3)
  56 #define IDMAC_DES0_CH   BIT(4)
  57 #define IDMAC_DES0_ER   BIT(5)
  58 #define IDMAC_DES0_CES  BIT(30)
  59 #define IDMAC_DES0_OWN  BIT(31)
  60
  61         u32             des1;   /* Buffer sizes */
  62 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  63         ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
  64
  65         u32             des2;   /* buffer 1 physical address */
  66
  67         u32             des3;   /* buffer 2 physical address */
  68 };
  69 #endif /* CONFIG_MMC_DW_IDMAC */
  70
  71 /**
  72  * struct dw_mci_slot - MMC slot state
  73  * @mmc: The mmc_host representing this slot.
  74  * @host: The MMC controller this slot is using.
  75  * @ctype: Card type for this slot.
  76  * @mrq: mmc_request currently being processed or waiting to be
  77  *      processed, or NULL when the slot is idle.
  78  * @queue_node: List node for placing this node in the @queue list of
  79  *      &struct dw_mci.
  80  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  81  * @flags: Random state bits associated with the slot.
  82  * @id: Number of this slot.
  83  * @last_detect_state: Most recently observed card detect state.
  84  */
  85 struct dw_mci_slot {
  86         struct mmc_host         *mmc;
  87         struct dw_mci           *host;
  88
  89         u32                     ctype;
  90
  91         struct mmc_request      *mrq;
  92         struct list_head        queue_node;
  93
  94         unsigned int            clock;
  95         unsigned long           flags;
  96 #define DW_MMC_CARD_PRESENT     0
  97 #define DW_MMC_CARD_NEED_INIT   1
  98         int                     id;
  99         int                     last_detect_state;
 100 };
 101
 102 #if defined(CONFIG_DEBUG_FS)
 103 static int dw_mci_req_show(struct seq_file *s, void *v)
 104 {
 105         struct dw_mci_slot *slot = s->private;
 106         struct mmc_request *mrq;
 107         struct mmc_command *cmd;
 108         struct mmc_command *stop;
 109         struct mmc_data *data;
 110
 111         /* Make sure we get a consistent snapshot */
 112         spin_lock_bh(&slot->host->lock);
 113         mrq = slot->mrq;
 114
 115         if (mrq) {
 116                 cmd = mrq->cmd;
 117                 data = mrq->data;
 118                 stop = mrq->stop;
 119
 120                 if (cmd)
 121                         seq_printf(s,
 122                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 123                                    cmd->opcode, cmd->arg, cmd->flags,
 124                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 125                                    cmd->resp[2], cmd->error);
 126                 if (data)
 127                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 128                                    data->bytes_xfered, data->blocks,
 129                                    data->blksz, data->flags, data->error);
 130                 if (stop)
 131                         seq_printf(s,
 132                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 133                                    stop->opcode, stop->arg, stop->flags,
 134                                    stop->resp[0], stop->resp[1], stop->resp[2],
 135                                    stop->resp[2], stop->error);
 136         }
 137
 138         spin_unlock_bh(&slot->host->lock);
 139
 140         return 0;
 141 }
 142
 143 static int dw_mci_req_open(struct inode *inode, struct file *file)
 144 {
 145         return single_open(file, dw_mci_req_show, inode->i_private);
 146 }
 147
 148 static const struct file_operations dw_mci_req_fops = {
 149         .owner          = THIS_MODULE,
 150         .open           = dw_mci_req_open,
 151         .read           = seq_read,
 152         .llseek         = seq_lseek,
 153         .release        = single_release,
 154 };
 155
 156 static int dw_mci_regs_show(struct seq_file *s, void *v)
 157 {
 158         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 159         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 160         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 161         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 162         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 163         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 164
 165         return 0;
 166 }
 167
 168 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 169 {
 170         return single_open(file, dw_mci_regs_show, inode->i_private);
 171 }
 172
 173 static const struct file_operations dw_mci_regs_fops = {
 174         .owner          = THIS_MODULE,
 175         .open           = dw_mci_regs_open,
 176         .read           = seq_read,
 177         .llseek         = seq_lseek,
 178         .release        = single_release,
 179 };
 180
 181 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 182 {
 183         struct mmc_host *mmc = slot->mmc;
 184         struct dw_mci *host = slot->host;
 185         struct dentry *root;
 186         struct dentry *node;
 187
 188         root = mmc->debugfs_root;
 189         if (!root)
 190                 return;
 191
 192         node = debugfs_create_file("regs", S_IRUSR, root, host,
 193                                    &dw_mci_regs_fops);
 194         if (!node)
 195                 goto err;
 196
 197         node = debugfs_create_file("req", S_IRUSR, root, slot,
 198                                    &dw_mci_req_fops);
 199         if (!node)
 200                 goto err;
 201
 202         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 203         if (!node)
 204                 goto err;
 205
 206         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 207                                   (u32 *)&host->pending_events);
 208         if (!node)
 209                 goto err;
 210
 211         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 212                                   (u32 *)&host->completed_events);
 213         if (!node)
 214                 goto err;
 215
 216         return;
 217
 218 err:
 219         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 220 }
 221 #endif /* defined(CONFIG_DEBUG_FS) */
 222
 223 static void dw_mci_set_timeout(struct dw_mci *host)
 224 {
 225         /* timeout (maximum) */
 226         mci_writel(host, TMOUT, 0xffffffff);
 227 }
 228
 229 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 230 {
 231         struct mmc_data *data;
 232         u32 cmdr;
 233         cmd->error = -EINPROGRESS;
 234
 235         cmdr = cmd->opcode;
 236
 237         if (cmdr == MMC_STOP_TRANSMISSION)
 238                 cmdr |= SDMMC_CMD_STOP;
 239         else
 240                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 241
 242         if (cmd->flags & MMC_RSP_PRESENT) {
 243                 /* We expect a response, so set this bit */
 244                 cmdr |= SDMMC_CMD_RESP_EXP;
 245                 if (cmd->flags & MMC_RSP_136)
 246                         cmdr |= SDMMC_CMD_RESP_LONG;
 247         }
 248
 249         if (cmd->flags & MMC_RSP_CRC)
 250                 cmdr |= SDMMC_CMD_RESP_CRC;
 251
 252         data = cmd->data;
 253         if (data) {
 254                 cmdr |= SDMMC_CMD_DAT_EXP;
 255                 if (data->flags & MMC_DATA_STREAM)
 256                         cmdr |= SDMMC_CMD_STRM_MODE;
 257                 if (data->flags & MMC_DATA_WRITE)
 258                         cmdr |= SDMMC_CMD_DAT_WR;
 259         }
 260
 261         return cmdr;
 262 }
 263
 264 static void dw_mci_start_command(struct dw_mci *host,
 265                                  struct mmc_command *cmd, u32 cmd_flags)
 266 {
 267         host->cmd = cmd;
 268         dev_vdbg(&host->pdev->dev,
 269                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 270                  cmd->arg, cmd_flags);
 271
 272         mci_writel(host, CMDARG, cmd->arg);
 273         wmb();
 274
 275         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 276 }
 277
 278 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 279 {
 280         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 281 }
 282
 283 /* DMA interface functions */
 284 static void dw_mci_stop_dma(struct dw_mci *host)
 285 {
 286         if (host->use_dma) {
 287                 host->dma_ops->stop(host);
 288                 host->dma_ops->cleanup(host);
 289         } else {
 290                 /* Data transfer was stopped by the interrupt handler */
 291                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 292         }
 293 }
 294
 295 #ifdef CONFIG_MMC_DW_IDMAC
 296 static void dw_mci_dma_cleanup(struct dw_mci *host)
 297 {
 298         struct mmc_data *data = host->data;
 299
 300         if (data)
 301                 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
 302                              ((data->flags & MMC_DATA_WRITE)
 303                               ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 304 }
 305
 306 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 307 {
 308         u32 temp;
 309
 310         /* Disable and reset the IDMAC interface */
 311         temp = mci_readl(host, CTRL);
 312         temp &= ~SDMMC_CTRL_USE_IDMAC;
 313         temp |= SDMMC_CTRL_DMA_RESET;
 314         mci_writel(host, CTRL, temp);
 315
 316         /* Stop the IDMAC running */
 317         temp = mci_readl(host, BMOD);
 318         temp &= ~SDMMC_IDMAC_ENABLE;
 319         mci_writel(host, BMOD, temp);
 320 }
 321
 322 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 323 {
 324         struct mmc_data *data = host->data;
 325
 326         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 327
 328         host->dma_ops->cleanup(host);
 329
 330         /*
 331          * If the card was removed, data will be NULL. No point in trying to
 332          * send the stop command or waiting for NBUSY in this case.
 333          */
 334         if (data) {
 335                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 336                 tasklet_schedule(&host->tasklet);
 337         }
 338 }
 339
 340 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 341                                     unsigned int sg_len)
 342 {
 343         int i;
 344         struct idmac_desc *desc = host->sg_cpu;
 345
 346         for (i = 0; i < sg_len; i++, desc++) {
 347                 unsigned int length = sg_dma_len(&data->sg[i]);
 348                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 349
 350                 /* Set the OWN bit and disable interrupts for this descriptor */
 351                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 352
 353                 /* Buffer length */
 354                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 355
 356                 /* Physical address to DMA to/from */
 357                 desc->des2 = mem_addr;
 358         }
 359
 360         /* Set first descriptor */
 361         desc = host->sg_cpu;
 362         desc->des0 |= IDMAC_DES0_FD;
 363
 364         /* Set last descriptor */
 365         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 366         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 367         desc->des0 |= IDMAC_DES0_LD;
 368
 369         wmb();
 370 }
 371
 372 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 373 {
 374         u32 temp;
 375
 376         dw_mci_translate_sglist(host, host->data, sg_len);
 377
 378         /* Select IDMAC interface */
 379         temp = mci_readl(host, CTRL);
 380         temp |= SDMMC_CTRL_USE_IDMAC;
 381         mci_writel(host, CTRL, temp);
 382
 383         wmb();
 384
 385         /* Enable the IDMAC */
 386         temp = mci_readl(host, BMOD);
 387         temp |= SDMMC_IDMAC_ENABLE;
 388         mci_writel(host, BMOD, temp);
 389
 390         /* Start it running */
 391         mci_writel(host, PLDMND, 1);
 392 }
 393
 394 static int dw_mci_idmac_init(struct dw_mci *host)
 395 {
 396         struct idmac_desc *p;
 397         int i;
 398
 399         /* Number of descriptors in the ring buffer */
 400         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 401
 402         /* Forward link the descriptor list */
 403         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 404                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 405
 406         /* Set the last descriptor as the end-of-ring descriptor */
 407         p->des3 = host->sg_dma;
 408         p->des0 = IDMAC_DES0_ER;
 409
 410         /* Mask out interrupts - get Tx & Rx complete only */
 411         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 412                    SDMMC_IDMAC_INT_TI);
 413
 414         /* Set the descriptor base address */
 415         mci_writel(host, DBADDR, host->sg_dma);
 416         return 0;
 417 }
 418
 419 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 420         .init = dw_mci_idmac_init,
 421         .start = dw_mci_idmac_start_dma,
 422         .stop = dw_mci_idmac_stop_dma,
 423         .complete = dw_mci_idmac_complete_dma,
 424         .cleanup = dw_mci_dma_cleanup,
 425 };
 426 #endif /* CONFIG_MMC_DW_IDMAC */
 427
 428 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 429 {
 430         struct scatterlist *sg;
 431         unsigned int i, direction, sg_len;
 432         u32 temp;
 433
 434         /* If we don't have a channel, we can't do DMA */
 435         if (!host->use_dma)
 436                 return -ENODEV;
 437
 438         /*
 439          * We don't do DMA on "complex" transfers, i.e. with
 440          * non-word-aligned buffers or lengths. Also, we don't bother
 441          * with all the DMA setup overhead for short transfers.
 442          */
 443         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 444                 return -EINVAL;
 445         if (data->blksz & 3)
 446                 return -EINVAL;
 447
 448         for_each_sg(data->sg, sg, data->sg_len, i) {
 449                 if (sg->offset & 3 || sg->length & 3)
 450                         return -EINVAL;
 451         }
 452
 453         if (data->flags & MMC_DATA_READ)
 454                 direction = DMA_FROM_DEVICE;
 455         else
 456                 direction = DMA_TO_DEVICE;
 457
 458         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
 459                             direction);
 460
 461         dev_vdbg(&host->pdev->dev,
 462                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 463                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 464                  sg_len);
 465
 466         /* Enable the DMA interface */
 467         temp = mci_readl(host, CTRL);
 468         temp |= SDMMC_CTRL_DMA_ENABLE;
 469         mci_writel(host, CTRL, temp);
 470
 471         /* Disable RX/TX IRQs, let DMA handle it */
 472         temp = mci_readl(host, INTMASK);
 473         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 474         mci_writel(host, INTMASK, temp);
 475
 476         host->dma_ops->start(host, sg_len);
 477
 478         return 0;
 479 }
 480
 481 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 482 {
 483         u32 temp;
 484
 485         data->error = -EINPROGRESS;
 486
 487         WARN_ON(host->data);
 488         host->sg = NULL;
 489         host->data = data;
 490
 491         if (dw_mci_submit_data_dma(host, data)) {
 492                 host->sg = data->sg;
 493                 host->pio_offset = 0;
 494                 if (data->flags & MMC_DATA_READ)
 495                         host->dir_status = DW_MCI_RECV_STATUS;
 496                 else
 497                         host->dir_status = DW_MCI_SEND_STATUS;
 498
 499                 temp = mci_readl(host, INTMASK);
 500                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 501                 mci_writel(host, INTMASK, temp);
 502
 503                 temp = mci_readl(host, CTRL);
 504                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 505                 mci_writel(host, CTRL, temp);
 506         }
 507 }
 508
 509 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 510 {
 511         struct dw_mci *host = slot->host;
 512         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 513         unsigned int cmd_status = 0;
 514
 515         mci_writel(host, CMDARG, arg);
 516         wmb();
 517         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 518
 519         while (time_before(jiffies, timeout)) {
 520                 cmd_status = mci_readl(host, CMD);
 521                 if (!(cmd_status & SDMMC_CMD_START))
 522                         return;
 523         }
 524         dev_err(&slot->mmc->class_dev,
 525                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 526                 cmd, arg, cmd_status);
 527 }
 528
 529 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 530 {
 531         struct dw_mci *host = slot->host;
 532         u32 div;
 533
 534         if (slot->clock != host->current_speed) {
 535                 if (host->bus_hz % slot->clock)
 536                         /*
 537                          * move the + 1 after the divide to prevent
 538                          * over-clocking the card.
 539                          */
 540                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 541                 else
 542                         div = (host->bus_hz  / slot->clock) >> 1;
 543
 544                 dev_info(&slot->mmc->class_dev,
 545                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 546                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 547                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 548
 549                 /* disable clock */
 550                 mci_writel(host, CLKENA, 0);
 551                 mci_writel(host, CLKSRC, 0);
 552
 553                 /* inform CIU */
 554                 mci_send_cmd(slot,
 555                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 556
 557                 /* set clock to desired speed */
 558                 mci_writel(host, CLKDIV, div);
 559
 560                 /* inform CIU */
 561                 mci_send_cmd(slot,
 562                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 563
 564                 /* enable clock */
 565                 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
 566                            SDMMC_CLKEN_LOW_PWR);
 567
 568                 /* inform CIU */
 569                 mci_send_cmd(slot,
 570                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 571
 572                 host->current_speed = slot->clock;
 573         }
 574
 575         /* Set the current slot bus width */
 576         mci_writel(host, CTYPE, slot->ctype);
 577 }
 578
 579 static void dw_mci_start_request(struct dw_mci *host,
 580                                  struct dw_mci_slot *slot)
 581 {
 582         struct mmc_request *mrq;
 583         struct mmc_command *cmd;
 584         struct mmc_data *data;
 585         u32 cmdflags;
 586
 587         mrq = slot->mrq;
 588         if (host->pdata->select_slot)
 589                 host->pdata->select_slot(slot->id);
 590
 591         /* Slot specific timing and width adjustment */
 592         dw_mci_setup_bus(slot);
 593
 594         host->cur_slot = slot;
 595         host->mrq = mrq;
 596
 597         host->pending_events = 0;
 598         host->completed_events = 0;
 599         host->data_status = 0;
 600
 601         data = mrq->data;
 602         if (data) {
 603                 dw_mci_set_timeout(host);
 604                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 605                 mci_writel(host, BLKSIZ, data->blksz);
 606         }
 607
 608         cmd = mrq->cmd;
 609         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 610
 611         /* this is the first command, send the initialization clock */
 612         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 613                 cmdflags |= SDMMC_CMD_INIT;
 614
 615         if (data) {
 616                 dw_mci_submit_data(host, data);
 617                 wmb();
 618         }
 619
 620         dw_mci_start_command(host, cmd, cmdflags);
 621
 622         if (mrq->stop)
 623                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 624 }
 625
 626 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 627                                  struct mmc_request *mrq)
 628 {
 629         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 630                  host->state);
 631
 632         spin_lock_bh(&host->lock);
 633         slot->mrq = mrq;
 634
 635         if (host->state == STATE_IDLE) {
 636                 host->state = STATE_SENDING_CMD;
 637                 dw_mci_start_request(host, slot);
 638         } else {
 639                 list_add_tail(&slot->queue_node, &host->queue);
 640         }
 641
 642         spin_unlock_bh(&host->lock);
 643 }
 644
 645 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 646 {
 647         struct dw_mci_slot *slot = mmc_priv(mmc);
 648         struct dw_mci *host = slot->host;
 649
 650         WARN_ON(slot->mrq);
 651
 652         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 653                 mrq->cmd->error = -ENOMEDIUM;
 654                 mmc_request_done(mmc, mrq);
 655                 return;
 656         }
 657
 658         /* We don't support multiple blocks of weird lengths. */
 659         dw_mci_queue_request(host, slot, mrq);
 660 }
 661
 662 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 663 {
 664         struct dw_mci_slot *slot = mmc_priv(mmc);
 665
 666         /* set default 1 bit mode */
 667         slot->ctype = SDMMC_CTYPE_1BIT;
 668
 669         switch (ios->bus_width) {
 670         case MMC_BUS_WIDTH_1:
 671                 slot->ctype = SDMMC_CTYPE_1BIT;
 672                 break;
 673         case MMC_BUS_WIDTH_4:
 674                 slot->ctype = SDMMC_CTYPE_4BIT;
 675                 break;
 676         }
 677
 678         if (ios->clock) {
 679                 /*
 680                  * Use mirror of ios->clock to prevent race with mmc
 681                  * core ios update when finding the minimum.
 682                  */
 683                 slot->clock = ios->clock;
 684         }
 685
 686         switch (ios->power_mode) {
 687         case MMC_POWER_UP:
 688                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 689                 break;
 690         default:
 691                 break;
 692         }
 693 }
 694
 695 static int dw_mci_get_ro(struct mmc_host *mmc)
 696 {
 697         int read_only;
 698         struct dw_mci_slot *slot = mmc_priv(mmc);
 699         struct dw_mci_board *brd = slot->host->pdata;
 700
 701         /* Use platform get_ro function, else try on board write protect */
 702         if (brd->get_ro)
 703                 read_only = brd->get_ro(slot->id);
 704         else
 705                 read_only =
 706                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 707
 708         dev_dbg(&mmc->class_dev, "card is %s\n",
 709                 read_only ? "read-only" : "read-write");
 710
 711         return read_only;
 712 }
 713
 714 static int dw_mci_get_cd(struct mmc_host *mmc)
 715 {
 716         int present;
 717         struct dw_mci_slot *slot = mmc_priv(mmc);
 718         struct dw_mci_board *brd = slot->host->pdata;
 719
 720         /* Use platform get_cd function, else try onboard card detect */
 721         if (brd->get_cd)
 722                 present = !brd->get_cd(slot->id);
 723         else
 724                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 725                         == 0 ? 1 : 0;
 726
 727         if (present)
 728                 dev_dbg(&mmc->class_dev, "card is present\n");
 729         else
 730                 dev_dbg(&mmc->class_dev, "card is not present\n");
 731
 732         return present;
 733 }
 734
 735 static const struct mmc_host_ops dw_mci_ops = {
 736         .request        = dw_mci_request,
 737         .set_ios        = dw_mci_set_ios,
 738         .get_ro         = dw_mci_get_ro,
 739         .get_cd         = dw_mci_get_cd,
 740 };
 741
 742 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 743         __releases(&host->lock)
 744         __acquires(&host->lock)
 745 {
 746         struct dw_mci_slot *slot;
 747         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 748
 749         WARN_ON(host->cmd || host->data);
 750
 751         host->cur_slot->mrq = NULL;
 752         host->mrq = NULL;
 753         if (!list_empty(&host->queue)) {
 754                 slot = list_entry(host->queue.next,
 755                                   struct dw_mci_slot, queue_node);
 756                 list_del(&slot->queue_node);
 757                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
 758                          mmc_hostname(slot->mmc));
 759                 host->state = STATE_SENDING_CMD;
 760                 dw_mci_start_request(host, slot);
 761         } else {
 762                 dev_vdbg(&host->pdev->dev, "list empty\n");
 763                 host->state = STATE_IDLE;
 764         }
 765
 766         spin_unlock(&host->lock);
 767         mmc_request_done(prev_mmc, mrq);
 768         spin_lock(&host->lock);
 769 }
 770
 771 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 772 {
 773         u32 status = host->cmd_status;
 774
 775         host->cmd_status = 0;
 776
 777         /* Read the response from the card (up to 16 bytes) */
 778         if (cmd->flags & MMC_RSP_PRESENT) {
 779                 if (cmd->flags & MMC_RSP_136) {
 780                         cmd->resp[3] = mci_readl(host, RESP0);
 781                         cmd->resp[2] = mci_readl(host, RESP1);
 782                         cmd->resp[1] = mci_readl(host, RESP2);
 783                         cmd->resp[0] = mci_readl(host, RESP3);
 784                 } else {
 785                         cmd->resp[0] = mci_readl(host, RESP0);
 786                         cmd->resp[1] = 0;
 787                         cmd->resp[2] = 0;
 788                         cmd->resp[3] = 0;
 789                 }
 790         }
 791
 792         if (status & SDMMC_INT_RTO)
 793                 cmd->error = -ETIMEDOUT;
 794         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 795                 cmd->error = -EILSEQ;
 796         else if (status & SDMMC_INT_RESP_ERR)
 797                 cmd->error = -EIO;
 798         else
 799                 cmd->error = 0;
 800
 801         if (cmd->error) {
 802                 /* newer ip versions need a delay between retries */
 803                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 804                         mdelay(20);
 805
 806                 if (cmd->data) {
 807                         host->data = NULL;
 808                         dw_mci_stop_dma(host);
 809                 }
 810         }
 811 }
 812
 813 static void dw_mci_tasklet_func(unsigned long priv)
 814 {
 815         struct dw_mci *host = (struct dw_mci *)priv;
 816         struct mmc_data *data;
 817         struct mmc_command *cmd;
 818         enum dw_mci_state state;
 819         enum dw_mci_state prev_state;
 820         u32 status;
 821
 822         spin_lock(&host->lock);
 823
 824         state = host->state;
 825         data = host->data;
 826
 827         do {
 828                 prev_state = state;
 829
 830                 switch (state) {
 831                 case STATE_IDLE:
 832                         break;
 833
 834                 case STATE_SENDING_CMD:
 835                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 836                                                 &host->pending_events))
 837                                 break;
 838
 839                         cmd = host->cmd;
 840                         host->cmd = NULL;
 841                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 842                         dw_mci_command_complete(host, host->mrq->cmd);
 843                         if (!host->mrq->data || cmd->error) {
 844                                 dw_mci_request_end(host, host->mrq);
 845                                 goto unlock;
 846                         }
 847
 848                         prev_state = state = STATE_SENDING_DATA;
 849                         /* fall through */
 850
 851                 case STATE_SENDING_DATA:
 852                         if (test_and_clear_bit(EVENT_DATA_ERROR,
 853                                                &host->pending_events)) {
 854                                 dw_mci_stop_dma(host);
 855                                 if (data->stop)
 856                                         send_stop_cmd(host, data);
 857                                 state = STATE_DATA_ERROR;
 858                                 break;
 859                         }
 860
 861                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 862                                                 &host->pending_events))
 863                                 break;
 864
 865                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
 866                         prev_state = state = STATE_DATA_BUSY;
 867                         /* fall through */
 868
 869                 case STATE_DATA_BUSY:
 870                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
 871                                                 &host->pending_events))
 872                                 break;
 873
 874                         host->data = NULL;
 875                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
 876                         status = host->data_status;
 877
 878                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
 879                                 if (status & SDMMC_INT_DTO) {
 880                                         dev_err(&host->pdev->dev,
 881                                                 "data timeout error\n");
 882                                         data->error = -ETIMEDOUT;
 883                                 } else if (status & SDMMC_INT_DCRC) {
 884                                         dev_err(&host->pdev->dev,
 885                                                 "data CRC error\n");
 886                                         data->error = -EILSEQ;
 887                                 } else {
 888                                         dev_err(&host->pdev->dev,
 889                                                 "data FIFO error "
 890                                                 "(status=%08x)\n",
 891                                                 status);
 892                                         data->error = -EIO;
 893                                 }
 894                         } else {
 895                                 data->bytes_xfered = data->blocks * data->blksz;
 896                                 data->error = 0;
 897                         }
 898
 899                         if (!data->stop) {
 900                                 dw_mci_request_end(host, host->mrq);
 901                                 goto unlock;
 902                         }
 903
 904                         prev_state = state = STATE_SENDING_STOP;
 905                         if (!data->error)
 906                                 send_stop_cmd(host, data);
 907                         /* fall through */
 908
 909                 case STATE_SENDING_STOP:
 910                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 911                                                 &host->pending_events))
 912                                 break;
 913
 914                         host->cmd = NULL;
 915                         dw_mci_command_complete(host, host->mrq->stop);
 916                         dw_mci_request_end(host, host->mrq);
 917                         goto unlock;
 918
 919                 case STATE_DATA_ERROR:
 920                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 921                                                 &host->pending_events))
 922                                 break;
 923
 924                         state = STATE_DATA_BUSY;
 925                         break;
 926                 }
 927         } while (state != prev_state);
 928
 929         host->state = state;
 930 unlock:
 931         spin_unlock(&host->lock);
 932
 933 }
 934
 935 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
 936 {
 937         u16 *pdata = (u16 *)buf;
 938
 939         WARN_ON(cnt % 2 != 0);
 940
 941         cnt = cnt >> 1;
 942         while (cnt > 0) {
 943                 mci_writew(host, DATA, *pdata++);
 944                 cnt--;
 945         }
 946 }
 947
 948 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
 949 {
 950         u16 *pdata = (u16 *)buf;
 951
 952         WARN_ON(cnt % 2 != 0);
 953
 954         cnt = cnt >> 1;
 955         while (cnt > 0) {
 956                 *pdata++ = mci_readw(host, DATA);
 957                 cnt--;
 958         }
 959 }
 960
 961 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
 962 {
 963         u32 *pdata = (u32 *)buf;
 964
 965         WARN_ON(cnt % 4 != 0);
 966         WARN_ON((unsigned long)pdata & 0x3);
 967
 968         cnt = cnt >> 2;
 969         while (cnt > 0) {
 970                 mci_writel(host, DATA, *pdata++);
 971                 cnt--;
 972         }
 973 }
 974
 975 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
 976 {
 977         u32 *pdata = (u32 *)buf;
 978
 979         WARN_ON(cnt % 4 != 0);
 980         WARN_ON((unsigned long)pdata & 0x3);
 981
 982         cnt = cnt >> 2;
 983         while (cnt > 0) {
 984                 *pdata++ = mci_readl(host, DATA);
 985                 cnt--;
 986         }
 987 }
 988
 989 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
 990 {
 991         u64 *pdata = (u64 *)buf;
 992
 993         WARN_ON(cnt % 8 != 0);
 994
 995         cnt = cnt >> 3;
 996         while (cnt > 0) {
 997                 mci_writeq(host, DATA, *pdata++);
 998                 cnt--;
 999         }
1000 }
1001
1002 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1003 {
1004         u64 *pdata = (u64 *)buf;
1005
1006         WARN_ON(cnt % 8 != 0);
1007
1008         cnt = cnt >> 3;
1009         while (cnt > 0) {
1010                 *pdata++ = mci_readq(host, DATA);
1011                 cnt--;
1012         }
1013 }
1014
1015 static void dw_mci_read_data_pio(struct dw_mci *host)
1016 {
1017         struct scatterlist *sg = host->sg;
1018         void *buf = sg_virt(sg);
1019         unsigned int offset = host->pio_offset;
1020         struct mmc_data *data = host->data;
1021         int shift = host->data_shift;
1022         u32 status;
1023         unsigned int nbytes = 0, len, old_len, count = 0;
1024
1025         do {
1026                 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
1027                 if (count == 0)
1028                         old_len = len;
1029
1030                 if (offset + len <= sg->length) {
1031                         host->pull_data(host, (void *)(buf + offset), len);
1032
1033                         offset += len;
1034                         nbytes += len;
1035
1036                         if (offset == sg->length) {
1037                                 flush_dcache_page(sg_page(sg));
1038                                 host->sg = sg = sg_next(sg);
1039                                 if (!sg)
1040                                         goto done;
1041
1042                                 offset = 0;
1043                                 buf = sg_virt(sg);
1044                         }
1045                 } else {
1046                         unsigned int remaining = sg->length - offset;
1047                         host->pull_data(host, (void *)(buf + offset),
1048                                         remaining);
1049                         nbytes += remaining;
1050
1051                         flush_dcache_page(sg_page(sg));
1052                         host->sg = sg = sg_next(sg);
1053                         if (!sg)
1054                                 goto done;
1055
1056                         offset = len - remaining;
1057                         buf = sg_virt(sg);
1058                         host->pull_data(host, buf, offset);
1059                         nbytes += offset;
1060                 }
1061
1062                 status = mci_readl(host, MINTSTS);
1063                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1064                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1065                         host->data_status = status;
1066                         data->bytes_xfered += nbytes;
1067                         smp_wmb();
1068
1069                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1070
1071                         tasklet_schedule(&host->tasklet);
1072                         return;
1073                 }
1074                 count++;
1075         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1076         len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1077         host->pio_offset = offset;
1078         data->bytes_xfered += nbytes;
1079         return;
1080
1081 done:
1082         data->bytes_xfered += nbytes;
1083         smp_wmb();
1084         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1085 }
1086
1087 static void dw_mci_write_data_pio(struct dw_mci *host)
1088 {
1089         struct scatterlist *sg = host->sg;
1090         void *buf = sg_virt(sg);
1091         unsigned int offset = host->pio_offset;
1092         struct mmc_data *data = host->data;
1093         int shift = host->data_shift;
1094         u32 status;
1095         unsigned int nbytes = 0, len;
1096
1097         do {
1098                 len = SDMMC_FIFO_SZ -
1099                         (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1100                 if (offset + len <= sg->length) {
1101                         host->push_data(host, (void *)(buf + offset), len);
1102
1103                         offset += len;
1104                         nbytes += len;
1105                         if (offset == sg->length) {
1106                                 host->sg = sg = sg_next(sg);
1107                                 if (!sg)
1108                                         goto done;
1109
1110                                 offset = 0;
1111                                 buf = sg_virt(sg);
1112                         }
1113                 } else {
1114                         unsigned int remaining = sg->length - offset;
1115
1116                         host->push_data(host, (void *)(buf + offset),
1117                                         remaining);
1118                         nbytes += remaining;
1119
1120                         host->sg = sg = sg_next(sg);
1121                         if (!sg)
1122                                 goto done;
1123
1124                         offset = len - remaining;
1125                         buf = sg_virt(sg);
1126                         host->push_data(host, (void *)buf, offset);
1127                         nbytes += offset;
1128                 }
1129
1130                 status = mci_readl(host, MINTSTS);
1131                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1132                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1133                         host->data_status = status;
1134                         data->bytes_xfered += nbytes;
1135
1136                         smp_wmb();
1137
1138                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1139
1140                         tasklet_schedule(&host->tasklet);
1141                         return;
1142                 }
1143         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1144
1145         host->pio_offset = offset;
1146         data->bytes_xfered += nbytes;
1147
1148         return;
1149
1150 done:
1151         data->bytes_xfered += nbytes;
1152         smp_wmb();
1153         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1154 }
1155
1156 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1157 {
1158         if (!host->cmd_status)
1159                 host->cmd_status = status;
1160
1161         smp_wmb();
1162
1163         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1164         tasklet_schedule(&host->tasklet);
1165 }
1166
1167 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1168 {
1169         struct dw_mci *host = dev_id;
1170         u32 status, pending;
1171         unsigned int pass_count = 0;
1172
1173         do {
1174                 status = mci_readl(host, RINTSTS);
1175                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1176
1177                 /*
1178                  * DTO fix - version 2.10a and below, and only if internal DMA
1179                  * is configured.
1180                  */
1181                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1182                         if (!pending &&
1183                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1184                                 pending |= SDMMC_INT_DATA_OVER;
1185                 }
1186
1187                 if (!pending)
1188                         break;
1189
1190                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1191                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1192                         host->cmd_status = status;
1193                         smp_wmb();
1194                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1195                         tasklet_schedule(&host->tasklet);
1196                 }
1197
1198                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1199                         /* if there is an error report DATA_ERROR */
1200                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1201                         host->data_status = status;
1202                         smp_wmb();
1203                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1204                         tasklet_schedule(&host->tasklet);
1205                 }
1206
1207                 if (pending & SDMMC_INT_DATA_OVER) {
1208                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1209                         if (!host->data_status)
1210                                 host->data_status = status;
1211                         smp_wmb();
1212                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1213                                 if (host->sg != NULL)
1214                                         dw_mci_read_data_pio(host);
1215                         }
1216                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1217                         tasklet_schedule(&host->tasklet);
1218                 }
1219
1220                 if (pending & SDMMC_INT_RXDR) {
1221                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1222                         if (host->sg)
1223                                 dw_mci_read_data_pio(host);
1224                 }
1225
1226                 if (pending & SDMMC_INT_TXDR) {
1227                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1228                         if (host->sg)
1229                                 dw_mci_write_data_pio(host);
1230                 }
1231
1232                 if (pending & SDMMC_INT_CMD_DONE) {
1233                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1234                         dw_mci_cmd_interrupt(host, status);
1235                 }
1236
1237                 if (pending & SDMMC_INT_CD) {
1238                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1239                         tasklet_schedule(&host->card_tasklet);
1240                 }
1241
1242         } while (pass_count++ < 5);
1243
1244 #ifdef CONFIG_MMC_DW_IDMAC
1245         /* Handle DMA interrupts */
1246         pending = mci_readl(host, IDSTS);
1247         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1248                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1249                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1250                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1251                 host->dma_ops->complete(host);
1252         }
1253 #endif
1254
1255         return IRQ_HANDLED;
1256 }
1257
1258 static void dw_mci_tasklet_card(unsigned long data)
1259 {
1260         struct dw_mci *host = (struct dw_mci *)data;
1261         int i;
1262
1263         for (i = 0; i < host->num_slots; i++) {
1264                 struct dw_mci_slot *slot = host->slot[i];
1265                 struct mmc_host *mmc = slot->mmc;
1266                 struct mmc_request *mrq;
1267                 int present;
1268                 u32 ctrl;
1269
1270                 present = dw_mci_get_cd(mmc);
1271                 while (present != slot->last_detect_state) {
1272                         spin_lock(&host->lock);
1273
1274                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1275                                 present ? "inserted" : "removed");
1276
1277                         /* Card change detected */
1278                         slot->last_detect_state = present;
1279
1280                         /* Power up slot */
1281                         if (present != 0) {
1282                                 if (host->pdata->setpower)
1283                                         host->pdata->setpower(slot->id,
1284                                                               mmc->ocr_avail);
1285
1286                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1287                         }
1288
1289                         /* Clean up queue if present */
1290                         mrq = slot->mrq;
1291                         if (mrq) {
1292                                 if (mrq == host->mrq) {
1293                                         host->data = NULL;
1294                                         host->cmd = NULL;
1295
1296                                         switch (host->state) {
1297                                         case STATE_IDLE:
1298                                                 break;
1299                                         case STATE_SENDING_CMD:
1300                                                 mrq->cmd->error = -ENOMEDIUM;
1301                                                 if (!mrq->data)
1302                                                         break;
1303                                                 /* fall through */
1304                                         case STATE_SENDING_DATA:
1305                                                 mrq->data->error = -ENOMEDIUM;
1306                                                 dw_mci_stop_dma(host);
1307                                                 break;
1308                                         case STATE_DATA_BUSY:
1309                                         case STATE_DATA_ERROR:
1310                                                 if (mrq->data->error == -EINPROGRESS)
1311                                                         mrq->data->error = -ENOMEDIUM;
1312                                                 if (!mrq->stop)
1313                                                         break;
1314                                                 /* fall through */
1315                                         case STATE_SENDING_STOP:
1316                                                 mrq->stop->error = -ENOMEDIUM;
1317                                                 break;
1318                                         }
1319
1320                                         dw_mci_request_end(host, mrq);
1321                                 } else {
1322                                         list_del(&slot->queue_node);
1323                                         mrq->cmd->error = -ENOMEDIUM;
1324                                         if (mrq->data)
1325                                                 mrq->data->error = -ENOMEDIUM;
1326                                         if (mrq->stop)
1327                                                 mrq->stop->error = -ENOMEDIUM;
1328
1329                                         spin_unlock(&host->lock);
1330                                         mmc_request_done(slot->mmc, mrq);
1331                                         spin_lock(&host->lock);
1332                                 }
1333                         }
1334
1335                         /* Power down slot */
1336                         if (present == 0) {
1337                                 if (host->pdata->setpower)
1338                                         host->pdata->setpower(slot->id, 0);
1339                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1340
1341                                 /*
1342                                  * Clear down the FIFO - doing so generates a
1343                                  * block interrupt, hence setting the
1344                                  * scatter-gather pointer to NULL.
1345                                  */
1346                                 host->sg = NULL;
1347
1348                                 ctrl = mci_readl(host, CTRL);
1349                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1350                                 mci_writel(host, CTRL, ctrl);
1351
1352 #ifdef CONFIG_MMC_DW_IDMAC
1353                                 ctrl = mci_readl(host, BMOD);
1354                                 ctrl |= 0x01; /* Software reset of DMA */
1355                                 mci_writel(host, BMOD, ctrl);
1356 #endif
1357
1358                         }
1359
1360                         spin_unlock(&host->lock);
1361                         present = dw_mci_get_cd(mmc);
1362                 }
1363
1364                 mmc_detect_change(slot->mmc,
1365                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1366         }
1367 }
1368
1369 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1370 {
1371         struct mmc_host *mmc;
1372         struct dw_mci_slot *slot;
1373
1374         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1375         if (!mmc)
1376                 return -ENOMEM;
1377
1378         slot = mmc_priv(mmc);
1379         slot->id = id;
1380         slot->mmc = mmc;
1381         slot->host = host;
1382
1383         mmc->ops = &dw_mci_ops;
1384         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1385         mmc->f_max = host->bus_hz;
1386
1387         if (host->pdata->get_ocr)
1388                 mmc->ocr_avail = host->pdata->get_ocr(id);
1389         else
1390                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1391
1392         /*
1393          * Start with slot power disabled, it will be enabled when a card
1394          * is detected.
1395          */
1396         if (host->pdata->setpower)
1397                 host->pdata->setpower(id, 0);
1398
1399         mmc->caps = 0;
1400         if (host->pdata->get_bus_wd)
1401                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1402                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1403
1404         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1405                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1406
1407 #ifdef CONFIG_MMC_DW_IDMAC
1408         mmc->max_segs = host->ring_size;
1409         mmc->max_blk_size = 65536;
1410         mmc->max_blk_count = host->ring_size;
1411         mmc->max_seg_size = 0x1000;
1412         mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1413 #else
1414         if (host->pdata->blk_settings) {
1415                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1416                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1417                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1418                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1419                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1420         } else {
1421                 /* Useful defaults if platform data is unset. */
1422                 mmc->max_segs = 64;
1423                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1424                 mmc->max_blk_count = 512;
1425                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1426                 mmc->max_seg_size = mmc->max_req_size;
1427         }
1428 #endif /* CONFIG_MMC_DW_IDMAC */
1429
1430         if (dw_mci_get_cd(mmc))
1431                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1432         else
1433                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1434
1435         host->slot[id] = slot;
1436         mmc_add_host(mmc);
1437
1438 #if defined(CONFIG_DEBUG_FS)
1439         dw_mci_init_debugfs(slot);
1440 #endif
1441
1442         /* Card initially undetected */
1443         slot->last_detect_state = 0;
1444
1445         /*
1446          * Card may have been plugged in prior to boot so we
1447          * need to run the detect tasklet
1448          */
1449         tasklet_schedule(&host->card_tasklet);
1450
1451         return 0;
1452 }
1453
1454 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1455 {
1456         /* Shutdown detect IRQ */
1457         if (slot->host->pdata->exit)
1458                 slot->host->pdata->exit(id);
1459
1460         /* Debugfs stuff is cleaned up by mmc core */
1461         mmc_remove_host(slot->mmc);
1462         slot->host->slot[id] = NULL;
1463         mmc_free_host(slot->mmc);
1464 }
1465
1466 static void dw_mci_init_dma(struct dw_mci *host)
1467 {
1468         /* Alloc memory for sg translation */
1469         host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1470                                           &host->sg_dma, GFP_KERNEL);
1471         if (!host->sg_cpu) {
1472                 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1473                         __func__);
1474                 goto no_dma;
1475         }
1476
1477         /* Determine which DMA interface to use */
1478 #ifdef CONFIG_MMC_DW_IDMAC
1479         host->dma_ops = &dw_mci_idmac_ops;
1480         dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1481 #endif
1482
1483         if (!host->dma_ops)
1484                 goto no_dma;
1485
1486         if (host->dma_ops->init) {
1487                 if (host->dma_ops->init(host)) {
1488                         dev_err(&host->pdev->dev, "%s: Unable to initialize "
1489                                 "DMA Controller.\n", __func__);
1490                         goto no_dma;
1491                 }
1492         } else {
1493                 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1494                 goto no_dma;
1495         }
1496
1497         host->use_dma = 1;
1498         return;
1499
1500 no_dma:
1501         dev_info(&host->pdev->dev, "Using PIO mode.\n");
1502         host->use_dma = 0;
1503         return;
1504 }
1505
1506 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1507 {
1508         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1509         unsigned int ctrl;
1510
1511         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1512                                 SDMMC_CTRL_DMA_RESET));
1513
1514         /* wait till resets clear */
1515         do {
1516                 ctrl = mci_readl(host, CTRL);
1517                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1518                               SDMMC_CTRL_DMA_RESET)))
1519                         return true;
1520         } while (time_before(jiffies, timeout));
1521
1522         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1523
1524         return false;
1525 }
1526
1527 static int dw_mci_probe(struct platform_device *pdev)
1528 {
1529         struct dw_mci *host;
1530         struct resource *regs;
1531         struct dw_mci_board *pdata;
1532         int irq, ret, i, width;
1533         u32 fifo_size;
1534
1535         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536         if (!regs)
1537                 return -ENXIO;
1538
1539         irq = platform_get_irq(pdev, 0);
1540         if (irq < 0)
1541                 return irq;
1542
1543         host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1544         if (!host)
1545                 return -ENOMEM;
1546
1547         host->pdev = pdev;
1548         host->pdata = pdata = pdev->dev.platform_data;
1549         if (!pdata || !pdata->init) {
1550                 dev_err(&pdev->dev,
1551                         "Platform data must supply init function\n");
1552                 ret = -ENODEV;
1553                 goto err_freehost;
1554         }
1555
1556         if (!pdata->select_slot && pdata->num_slots > 1) {
1557                 dev_err(&pdev->dev,
1558                         "Platform data must supply select_slot function\n");
1559                 ret = -ENODEV;
1560                 goto err_freehost;
1561         }
1562
1563         if (!pdata->bus_hz) {
1564                 dev_err(&pdev->dev,
1565                         "Platform data must supply bus speed\n");
1566                 ret = -ENODEV;
1567                 goto err_freehost;
1568         }
1569
1570         host->bus_hz = pdata->bus_hz;
1571         host->quirks = pdata->quirks;
1572
1573         spin_lock_init(&host->lock);
1574         INIT_LIST_HEAD(&host->queue);
1575
1576         ret = -ENOMEM;
1577         host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1578         if (!host->regs)
1579                 goto err_freehost;
1580
1581         host->dma_ops = pdata->dma_ops;
1582         dw_mci_init_dma(host);
1583
1584         /*
1585          * Get the host data width - this assumes that HCON has been set with
1586          * the correct values.
1587          */
1588         i = (mci_readl(host, HCON) >> 7) & 0x7;
1589         if (!i) {
1590                 host->push_data = dw_mci_push_data16;
1591                 host->pull_data = dw_mci_pull_data16;
1592                 width = 16;
1593                 host->data_shift = 1;
1594         } else if (i == 2) {
1595                 host->push_data = dw_mci_push_data64;
1596                 host->pull_data = dw_mci_pull_data64;
1597                 width = 64;
1598                 host->data_shift = 3;
1599         } else {
1600                 /* Check for a reserved value, and warn if it is */
1601                 WARN((i != 1),
1602                      "HCON reports a reserved host data width!\n"
1603                      "Defaulting to 32-bit access.\n");
1604                 host->push_data = dw_mci_push_data32;
1605                 host->pull_data = dw_mci_pull_data32;
1606                 width = 32;
1607                 host->data_shift = 2;
1608         }
1609
1610         /* Reset all blocks */
1611         if (!mci_wait_reset(&pdev->dev, host)) {
1612                 ret = -ENODEV;
1613                 goto err_dmaunmap;
1614         }
1615
1616         /* Clear the interrupts for the host controller */
1617         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1618         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1619
1620         /* Put in max timeout */
1621         mci_writel(host, TMOUT, 0xFFFFFFFF);
1622
1623         /*
1624          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1625          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1626          */
1627         fifo_size = mci_readl(host, FIFOTH);
1628         fifo_size = (fifo_size >> 16) & 0x7ff;
1629         mci_writel(host, FIFOTH, ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1630                                   ((fifo_size/2) << 0)));
1631
1632         /* disable clock to CIU */
1633         mci_writel(host, CLKENA, 0);
1634         mci_writel(host, CLKSRC, 0);
1635
1636         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1637         tasklet_init(&host->card_tasklet,
1638                      dw_mci_tasklet_card, (unsigned long)host);
1639
1640         ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1641         if (ret)
1642                 goto err_dmaunmap;
1643
1644         platform_set_drvdata(pdev, host);
1645
1646         if (host->pdata->num_slots)
1647                 host->num_slots = host->pdata->num_slots;
1648         else
1649                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1650
1651         /* We need at least one slot to succeed */
1652         for (i = 0; i < host->num_slots; i++) {
1653                 ret = dw_mci_init_slot(host, i);
1654                 if (ret) {
1655                         ret = -ENODEV;
1656                         goto err_init_slot;
1657                 }
1658         }
1659
1660         /*
1661          * Enable interrupts for command done, data over, data empty, card det,
1662          * receive ready and error such as transmit, receive timeout, crc error
1663          */
1664         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1665         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1666                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1667                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1668         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1669
1670         dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1671                  "%d bit host data width\n", irq, width);
1672         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1673                 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1674
1675         return 0;
1676
1677 err_init_slot:
1678         /* De-init any initialized slots */
1679         while (i > 0) {
1680                 if (host->slot[i])
1681                         dw_mci_cleanup_slot(host->slot[i], i);
1682                 i--;
1683         }
1684         free_irq(irq, host);
1685
1686 err_dmaunmap:
1687         if (host->use_dma && host->dma_ops->exit)
1688                 host->dma_ops->exit(host);
1689         dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1690                           host->sg_cpu, host->sg_dma);
1691         iounmap(host->regs);
1692
1693 err_freehost:
1694         kfree(host);
1695         return ret;
1696 }
1697
1698 static int __exit dw_mci_remove(struct platform_device *pdev)
1699 {
1700         struct dw_mci *host = platform_get_drvdata(pdev);
1701         int i;
1702
1703         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1704         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1705
1706         platform_set_drvdata(pdev, NULL);
1707
1708         for (i = 0; i < host->num_slots; i++) {
1709                 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1710                 if (host->slot[i])
1711                         dw_mci_cleanup_slot(host->slot[i], i);
1712         }
1713
1714         /* disable clock to CIU */
1715         mci_writel(host, CLKENA, 0);
1716         mci_writel(host, CLKSRC, 0);
1717
1718         free_irq(platform_get_irq(pdev, 0), host);
1719         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1720
1721         if (host->use_dma && host->dma_ops->exit)
1722                 host->dma_ops->exit(host);
1723
1724         iounmap(host->regs);
1725
1726         kfree(host);
1727         return 0;
1728 }
1729
1730 #ifdef CONFIG_PM
1731 /*
1732  * TODO: we should probably disable the clock to the card in the suspend path.
1733  */
1734 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1735 {
1736         int i, ret;
1737         struct dw_mci *host = platform_get_drvdata(pdev);
1738
1739         for (i = 0; i < host->num_slots; i++) {
1740                 struct dw_mci_slot *slot = host->slot[i];
1741                 if (!slot)
1742                         continue;
1743                 ret = mmc_suspend_host(slot->mmc);
1744                 if (ret < 0) {
1745                         while (--i >= 0) {
1746                                 slot = host->slot[i];
1747                                 if (slot)
1748                                         mmc_resume_host(host->slot[i]->mmc);
1749                         }
1750                         return ret;
1751                 }
1752         }
1753
1754         return 0;
1755 }
1756
1757 static int dw_mci_resume(struct platform_device *pdev)
1758 {
1759         int i, ret;
1760         struct dw_mci *host = platform_get_drvdata(pdev);
1761
1762         for (i = 0; i < host->num_slots; i++) {
1763                 struct dw_mci_slot *slot = host->slot[i];
1764                 if (!slot)
1765                         continue;
1766                 ret = mmc_resume_host(host->slot[i]->mmc);
1767                 if (ret < 0)
1768                         return ret;
1769         }
1770
1771         return 0;
1772 }
1773 #else
1774 #define dw_mci_suspend  NULL
1775 #define dw_mci_resume   NULL
1776 #endif /* CONFIG_PM */
1777
1778 static struct platform_driver dw_mci_driver = {
1779         .remove         = __exit_p(dw_mci_remove),
1780         .suspend        = dw_mci_suspend,
1781         .resume         = dw_mci_resume,
1782         .driver         = {
1783                 .name           = "dw_mmc",
1784         },
1785 };
1786
1787 static int __init dw_mci_init(void)
1788 {
1789         return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1790 }
1791
1792 static void __exit dw_mci_exit(void)
1793 {
1794         platform_driver_unregister(&dw_mci_driver);
1795 }
1796
1797 module_init(dw_mci_init);
1798 module_exit(dw_mci_exit);
1799
1800 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1801 MODULE_AUTHOR("NXP Semiconductor VietNam");
1802 MODULE_AUTHOR("Imagination Technologies Ltd");
1803 MODULE_LICENSE("GPL v2");