drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_COVER_POLL_DELAY       500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct tasklet_struct   cover_tasklet;
 110         struct timer_list       cover_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         struct work_struct      cmd_abort_work;
 138         unsigned                abort:1;
 139         struct timer_list       cmd_abort_timer;
 140
 141         unsigned int            sg_len;
 142         int                     sg_idx;
 143         u16 *                   buffer;
 144         u32                     buffer_bytes_left;
 145         u32                     total_bytes_left;
 146
 147         unsigned                use_dma:1;
 148         unsigned                brs_received:1, dma_done:1;
 149         unsigned                dma_is_read:1;
 150         unsigned                dma_in_use:1;
 151         int                     dma_ch;
 152         spinlock_t              dma_lock;
 153         struct timer_list       dma_timer;
 154         unsigned                dma_len;
 155
 156         short                   power_pin;
 157
 158         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 159         struct mmc_omap_slot    *current_slot;
 160         spinlock_t              slot_lock;
 161         wait_queue_head_t       slot_wq;
 162         int                     nr_slots;
 163
 164         struct omap_mmc_platform_data *pdata;
 165 };
 166
 167 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 168 {
 169         struct mmc_omap_host *host = slot->host;
 170         unsigned long flags;
 171
 172         if (claimed)
 173                 goto no_claim;
 174         spin_lock_irqsave(&host->slot_lock, flags);
 175         while (host->mmc != NULL) {
 176                 spin_unlock_irqrestore(&host->slot_lock, flags);
 177                 wait_event(host->slot_wq, host->mmc == NULL);
 178                 spin_lock_irqsave(&host->slot_lock, flags);
 179         }
 180         host->mmc = slot->mmc;
 181         spin_unlock_irqrestore(&host->slot_lock, flags);
 182 no_claim:
 183         clk_enable(host->fclk);
 184         if (host->current_slot != slot) {
 185                 if (host->pdata->switch_slot != NULL)
 186                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 187                 host->current_slot = slot;
 188         }
 189
 190         /* Doing the dummy read here seems to work around some bug
 191          * at least in OMAP24xx silicon where the command would not
 192          * start after writing the CMD register. Sigh. */
 193         OMAP_MMC_READ(host, CON);
 194
 195         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 196 }
 197
 198 static void mmc_omap_start_request(struct mmc_omap_host *host,
 199                                    struct mmc_request *req);
 200
 201 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 202 {
 203         struct mmc_omap_host *host = slot->host;
 204         unsigned long flags;
 205         int i;
 206
 207         BUG_ON(slot == NULL || host->mmc == NULL);
 208         clk_disable(host->fclk);
 209
 210         spin_lock_irqsave(&host->slot_lock, flags);
 211         /* Check for any pending requests */
 212         for (i = 0; i < host->nr_slots; i++) {
 213                 struct mmc_omap_slot *new_slot;
 214                 struct mmc_request *rq;
 215
 216                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 217                         continue;
 218
 219                 new_slot = host->slots[i];
 220                 /* The current slot should not have a request in queue */
 221                 BUG_ON(new_slot == host->current_slot);
 222
 223                 host->mmc = new_slot->mmc;
 224                 spin_unlock_irqrestore(&host->slot_lock, flags);
 225                 mmc_omap_select_slot(new_slot, 1);
 226                 rq = new_slot->mrq;
 227                 new_slot->mrq = NULL;
 228                 mmc_omap_start_request(host, rq);
 229                 return;
 230         }
 231
 232         host->mmc = NULL;
 233         wake_up(&host->slot_wq);
 234         spin_unlock_irqrestore(&host->slot_lock, flags);
 235 }
 236
 237 static inline
 238 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 239 {
 240         if (slot->pdata->get_cover_state)
 241                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 242                                                     slot->id);
 243         return 0;
 244 }
 245
 246 static ssize_t
 247 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 248                            char *buf)
 249 {
 250         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 251         struct mmc_omap_slot *slot = mmc_priv(mmc);
 252
 253         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 254                        "closed");
 255 }
 256
 257 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 258
 259 static ssize_t
 260 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 261                         char *buf)
 262 {
 263         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 264         struct mmc_omap_slot *slot = mmc_priv(mmc);
 265
 266         return sprintf(buf, "%s\n", slot->pdata->name);
 267 }
 268
 269 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 270
 271 static void
 272 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 273 {
 274         u32 cmdreg;
 275         u32 resptype;
 276         u32 cmdtype;
 277
 278         host->cmd = cmd;
 279
 280         resptype = 0;
 281         cmdtype = 0;
 282
 283         /* Our hardware needs to know exact type */
 284         switch (mmc_resp_type(cmd)) {
 285         case MMC_RSP_NONE:
 286                 break;
 287         case MMC_RSP_R1:
 288         case MMC_RSP_R1B:
 289                 /* resp 1, 1b, 6, 7 */
 290                 resptype = 1;
 291                 break;
 292         case MMC_RSP_R2:
 293                 resptype = 2;
 294                 break;
 295         case MMC_RSP_R3:
 296                 resptype = 3;
 297                 break;
 298         default:
 299                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 300                 break;
 301         }
 302
 303         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 304                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 305         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 306                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 307         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 308                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 309         } else {
 310                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 311         }
 312
 313         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 314
 315         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 316                 cmdreg |= 1 << 6;
 317
 318         if (cmd->flags & MMC_RSP_BUSY)
 319                 cmdreg |= 1 << 11;
 320
 321         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 322                 cmdreg |= 1 << 15;
 323
 324         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 325
 326         OMAP_MMC_WRITE(host, CTO, 200);
 327         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 328         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 329         OMAP_MMC_WRITE(host, IE,
 330                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 331                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 332                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 333                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 334                        OMAP_MMC_STAT_END_OF_DATA);
 335         OMAP_MMC_WRITE(host, CMD, cmdreg);
 336 }
 337
 338 static void
 339 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 340                      int abort)
 341 {
 342         enum dma_data_direction dma_data_dir;
 343
 344         BUG_ON(host->dma_ch < 0);
 345         if (data->error)
 346                 omap_stop_dma(host->dma_ch);
 347         /* Release DMA channel lazily */
 348         mod_timer(&host->dma_timer, jiffies + HZ);
 349         if (data->flags & MMC_DATA_WRITE)
 350                 dma_data_dir = DMA_TO_DEVICE;
 351         else
 352                 dma_data_dir = DMA_FROM_DEVICE;
 353         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 354                      dma_data_dir);
 355 }
 356
 357 static void
 358 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 359 {
 360         if (host->dma_in_use)
 361                 mmc_omap_release_dma(host, data, data->error);
 362
 363         host->data = NULL;
 364         host->sg_len = 0;
 365
 366         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 367          * dozens of requests until the card finishes writing data.
 368          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 369          */
 370
 371         if (!data->stop) {
 372                 struct mmc_host *mmc;
 373
 374                 host->mrq = NULL;
 375                 mmc = host->mmc;
 376                 mmc_omap_release_slot(host->current_slot);
 377                 mmc_request_done(mmc, data->mrq);
 378                 return;
 379         }
 380
 381         mmc_omap_start_command(host, data->stop);
 382 }
 383
 384 static void
 385 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 386 {
 387         struct mmc_omap_slot *slot = host->current_slot;
 388         unsigned int restarts, passes, timeout;
 389         u16 stat = 0;
 390
 391         /* Sending abort takes 80 clocks. Have some extra and round up */
 392         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 393         restarts = 0;
 394         while (restarts < maxloops) {
 395                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 396                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 397
 398                 passes = 0;
 399                 while (passes < timeout) {
 400                         stat = OMAP_MMC_READ(host, STAT);
 401                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 402                                 goto out;
 403                         udelay(1);
 404                         passes++;
 405                 }
 406
 407                 restarts++;
 408         }
 409 out:
 410         OMAP_MMC_WRITE(host, STAT, stat);
 411 }
 412
 413 static void
 414 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 415 {
 416         if (host->dma_in_use)
 417                 mmc_omap_release_dma(host, data, 1);
 418
 419         host->data = NULL;
 420         host->sg_len = 0;
 421
 422         mmc_omap_send_abort(host, 10000);
 423 }
 424
 425 static void
 426 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 427 {
 428         unsigned long flags;
 429         int done;
 430
 431         if (!host->dma_in_use) {
 432                 mmc_omap_xfer_done(host, data);
 433                 return;
 434         }
 435         done = 0;
 436         spin_lock_irqsave(&host->dma_lock, flags);
 437         if (host->dma_done)
 438                 done = 1;
 439         else
 440                 host->brs_received = 1;
 441         spin_unlock_irqrestore(&host->dma_lock, flags);
 442         if (done)
 443                 mmc_omap_xfer_done(host, data);
 444 }
 445
 446 static void
 447 mmc_omap_dma_timer(unsigned long data)
 448 {
 449         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 450
 451         BUG_ON(host->dma_ch < 0);
 452         omap_free_dma(host->dma_ch);
 453         host->dma_ch = -1;
 454 }
 455
 456 static void
 457 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 458 {
 459         unsigned long flags;
 460         int done;
 461
 462         done = 0;
 463         spin_lock_irqsave(&host->dma_lock, flags);
 464         if (host->brs_received)
 465                 done = 1;
 466         else
 467                 host->dma_done = 1;
 468         spin_unlock_irqrestore(&host->dma_lock, flags);
 469         if (done)
 470                 mmc_omap_xfer_done(host, data);
 471 }
 472
 473 static void
 474 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 475 {
 476         host->cmd = NULL;
 477
 478         del_timer(&host->cmd_abort_timer);
 479
 480         if (cmd->flags & MMC_RSP_PRESENT) {
 481                 if (cmd->flags & MMC_RSP_136) {
 482                         /* response type 2 */
 483                         cmd->resp[3] =
 484                                 OMAP_MMC_READ(host, RSP0) |
 485                                 (OMAP_MMC_READ(host, RSP1) << 16);
 486                         cmd->resp[2] =
 487                                 OMAP_MMC_READ(host, RSP2) |
 488                                 (OMAP_MMC_READ(host, RSP3) << 16);
 489                         cmd->resp[1] =
 490                                 OMAP_MMC_READ(host, RSP4) |
 491                                 (OMAP_MMC_READ(host, RSP5) << 16);
 492                         cmd->resp[0] =
 493                                 OMAP_MMC_READ(host, RSP6) |
 494                                 (OMAP_MMC_READ(host, RSP7) << 16);
 495                 } else {
 496                         /* response types 1, 1b, 3, 4, 5, 6 */
 497                         cmd->resp[0] =
 498                                 OMAP_MMC_READ(host, RSP6) |
 499                                 (OMAP_MMC_READ(host, RSP7) << 16);
 500                 }
 501         }
 502
 503         if (host->data == NULL || cmd->error) {
 504                 struct mmc_host *mmc;
 505
 506                 if (host->data != NULL)
 507                         mmc_omap_abort_xfer(host, host->data);
 508                 host->mrq = NULL;
 509                 mmc = host->mmc;
 510                 mmc_omap_release_slot(host->current_slot);
 511                 mmc_request_done(mmc, cmd->mrq);
 512         }
 513 }
 514
 515 /*
 516  * Abort stuck command. Can occur when card is removed while it is being
 517  * read.
 518  */
 519 static void mmc_omap_abort_command(struct work_struct *work)
 520 {
 521         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 522                                                   cmd_abort_work);
 523         BUG_ON(!host->cmd);
 524
 525         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 526                 host->cmd->opcode);
 527
 528         if (host->cmd->error == 0)
 529                 host->cmd->error = -ETIMEDOUT;
 530
 531         if (host->data == NULL) {
 532                 struct mmc_command *cmd;
 533                 struct mmc_host    *mmc;
 534
 535                 cmd = host->cmd;
 536                 host->cmd = NULL;
 537                 mmc_omap_send_abort(host, 10000);
 538
 539                 host->mrq = NULL;
 540                 mmc = host->mmc;
 541                 mmc_omap_release_slot(host->current_slot);
 542                 mmc_request_done(mmc, cmd->mrq);
 543         } else
 544                 mmc_omap_cmd_done(host, host->cmd);
 545
 546         host->abort = 0;
 547         enable_irq(host->irq);
 548 }
 549
 550 static void
 551 mmc_omap_cmd_timer(unsigned long data)
 552 {
 553         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 554         unsigned long flags;
 555
 556         spin_lock_irqsave(&host->slot_lock, flags);
 557         if (host->cmd != NULL && !host->abort) {
 558                 OMAP_MMC_WRITE(host, IE, 0);
 559                 disable_irq(host->irq);
 560                 host->abort = 1;
 561                 schedule_work(&host->cmd_abort_work);
 562         }
 563         spin_unlock_irqrestore(&host->slot_lock, flags);
 564 }
 565
 566 /* PIO only */
 567 static void
 568 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 569 {
 570         struct scatterlist *sg;
 571
 572         sg = host->data->sg + host->sg_idx;
 573         host->buffer_bytes_left = sg->length;
 574         host->buffer = sg_virt(sg);
 575         if (host->buffer_bytes_left > host->total_bytes_left)
 576                 host->buffer_bytes_left = host->total_bytes_left;
 577 }
 578
 579 /* PIO only */
 580 static void
 581 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 582 {
 583         int n;
 584
 585         if (host->buffer_bytes_left == 0) {
 586                 host->sg_idx++;
 587                 BUG_ON(host->sg_idx == host->sg_len);
 588                 mmc_omap_sg_to_buf(host);
 589         }
 590         n = 64;
 591         if (n > host->buffer_bytes_left)
 592                 n = host->buffer_bytes_left;
 593         host->buffer_bytes_left -= n;
 594         host->total_bytes_left -= n;
 595         host->data->bytes_xfered += n;
 596
 597         if (write) {
 598                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 599         } else {
 600                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 601         }
 602 }
 603
 604 static inline void mmc_omap_report_irq(u16 status)
 605 {
 606         static const char *mmc_omap_status_bits[] = {
 607                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 608                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 609         };
 610         int i, c = 0;
 611
 612         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 613                 if (status & (1 << i)) {
 614                         if (c)
 615                                 printk(" ");
 616                         printk("%s", mmc_omap_status_bits[i]);
 617                         c++;
 618                 }
 619 }
 620
 621 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 622 {
 623         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 624         u16 status;
 625         int end_command;
 626         int end_transfer;
 627         int transfer_error, cmd_error;
 628
 629         if (host->cmd == NULL && host->data == NULL) {
 630                 status = OMAP_MMC_READ(host, STAT);
 631                 dev_info(mmc_dev(host->slots[0]->mmc),
 632                          "Spurious IRQ 0x%04x\n", status);
 633                 if (status != 0) {
 634                         OMAP_MMC_WRITE(host, STAT, status);
 635                         OMAP_MMC_WRITE(host, IE, 0);
 636                 }
 637                 return IRQ_HANDLED;
 638         }
 639
 640         end_command = 0;
 641         end_transfer = 0;
 642         transfer_error = 0;
 643         cmd_error = 0;
 644
 645         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 646                 int cmd;
 647
 648                 OMAP_MMC_WRITE(host, STAT, status);
 649                 if (host->cmd != NULL)
 650                         cmd = host->cmd->opcode;
 651                 else
 652                         cmd = -1;
 653 #ifdef CONFIG_MMC_DEBUG
 654                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 655                         status, cmd);
 656                 mmc_omap_report_irq(status);
 657                 printk("\n");
 658 #endif
 659                 if (host->total_bytes_left) {
 660                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 661                             (status & OMAP_MMC_STAT_END_OF_DATA))
 662                                 mmc_omap_xfer_data(host, 0);
 663                         if (status & OMAP_MMC_STAT_A_EMPTY)
 664                                 mmc_omap_xfer_data(host, 1);
 665                 }
 666
 667                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 668                         end_transfer = 1;
 669
 670                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 671                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 672                                 cmd);
 673                         if (host->data) {
 674                                 host->data->error = -ETIMEDOUT;
 675                                 transfer_error = 1;
 676                         }
 677                 }
 678
 679                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 680                         if (host->data) {
 681                                 host->data->error = -EILSEQ;
 682                                 dev_dbg(mmc_dev(host->mmc),
 683                                          "data CRC error, bytes left %d\n",
 684                                         host->total_bytes_left);
 685                                 transfer_error = 1;
 686                         } else {
 687                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 688                         }
 689                 }
 690
 691                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 692                         /* Timeouts are routine with some commands */
 693                         if (host->cmd) {
 694                                 struct mmc_omap_slot *slot =
 695                                         host->current_slot;
 696                                 if (slot == NULL ||
 697                                     !mmc_omap_cover_is_open(slot))
 698                                         dev_err(mmc_dev(host->mmc),
 699                                                 "command timeout (CMD%d)\n",
 700                                                 cmd);
 701                                 host->cmd->error = -ETIMEDOUT;
 702                                 end_command = 1;
 703                                 cmd_error = 1;
 704                         }
 705                 }
 706
 707                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 708                         if (host->cmd) {
 709                                 dev_err(mmc_dev(host->mmc),
 710                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 711                                         cmd, host->cmd->arg);
 712                                 host->cmd->error = -EILSEQ;
 713                                 end_command = 1;
 714                                 cmd_error = 1;
 715                         } else
 716                                 dev_err(mmc_dev(host->mmc),
 717                                         "command CRC error without cmd?\n");
 718                 }
 719
 720                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 721                         dev_dbg(mmc_dev(host->mmc),
 722                                 "ignoring card status error (CMD%d)\n",
 723                                 cmd);
 724                         end_command = 1;
 725                 }
 726
 727                 /*
 728                  * NOTE: On 1610 the END_OF_CMD may come too early when
 729                  * starting a write
 730                  */
 731                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 732                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 733                         end_command = 1;
 734                 }
 735         }
 736
 737         if (cmd_error && host->data) {
 738                 del_timer(&host->cmd_abort_timer);
 739                 host->abort = 1;
 740                 OMAP_MMC_WRITE(host, IE, 0);
 741                 disable_irq(host->irq);
 742                 schedule_work(&host->cmd_abort_work);
 743                 return IRQ_HANDLED;
 744         }
 745
 746         if (end_command)
 747                 mmc_omap_cmd_done(host, host->cmd);
 748         if (host->data != NULL) {
 749                 if (transfer_error)
 750                         mmc_omap_xfer_done(host, host->data);
 751                 else if (end_transfer)
 752                         mmc_omap_end_of_data(host, host->data);
 753         }
 754
 755         return IRQ_HANDLED;
 756 }
 757
 758 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 759 {
 760         int cover_open;
 761         struct mmc_omap_host *host = dev_get_drvdata(dev);
 762         struct mmc_omap_slot *slot = host->slots[num];
 763
 764         BUG_ON(num >= host->nr_slots);
 765
 766         /* Other subsystems can call in here before we're initialised. */
 767         if (host->nr_slots == 0 || !host->slots[num])
 768                 return;
 769
 770         cover_open = mmc_omap_cover_is_open(slot);
 771         if (cover_open != slot->cover_open) {
 772                 slot->cover_open = cover_open;
 773                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 774         }
 775
 776         tasklet_hi_schedule(&slot->cover_tasklet);
 777 }
 778
 779 static void mmc_omap_cover_timer(unsigned long arg)
 780 {
 781         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 782         tasklet_schedule(&slot->cover_tasklet);
 783 }
 784
 785 static void mmc_omap_cover_handler(unsigned long param)
 786 {
 787         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 788         int cover_open = mmc_omap_cover_is_open(slot);
 789
 790         mmc_detect_change(slot->mmc, 0);
 791         if (!cover_open)
 792                 return;
 793
 794         /*
 795          * If no card is inserted, we postpone polling until
 796          * the cover has been closed.
 797          */
 798         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 799                 return;
 800
 801         mod_timer(&slot->cover_timer,
 802                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 803 }
 804
 805 /* Prepare to transfer the next segment of a scatterlist */
 806 static void
 807 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 808 {
 809         int dma_ch = host->dma_ch;
 810         unsigned long data_addr;
 811         u16 buf, frame;
 812         u32 count;
 813         struct scatterlist *sg = &data->sg[host->sg_idx];
 814         int src_port = 0;
 815         int dst_port = 0;
 816         int sync_dev = 0;
 817
 818         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 819         frame = data->blksz;
 820         count = sg_dma_len(sg);
 821
 822         if ((data->blocks == 1) && (count > data->blksz))
 823                 count = frame;
 824
 825         host->dma_len = count;
 826
 827         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 828          * Use 16 or 32 word frames when the blocksize is at least that large.
 829          * Blocksize is usually 512 bytes; but not for some SD reads.
 830          */
 831         if (cpu_is_omap15xx() && frame > 32)
 832                 frame = 32;
 833         else if (frame > 64)
 834                 frame = 64;
 835         count /= frame;
 836         frame >>= 1;
 837
 838         if (!(data->flags & MMC_DATA_WRITE)) {
 839                 buf = 0x800f | ((frame - 1) << 8);
 840
 841                 if (cpu_class_is_omap1()) {
 842                         src_port = OMAP_DMA_PORT_TIPB;
 843                         dst_port = OMAP_DMA_PORT_EMIFF;
 844                 }
 845                 if (cpu_is_omap24xx())
 846                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 847
 848                 omap_set_dma_src_params(dma_ch, src_port,
 849                                         OMAP_DMA_AMODE_CONSTANT,
 850                                         data_addr, 0, 0);
 851                 omap_set_dma_dest_params(dma_ch, dst_port,
 852                                          OMAP_DMA_AMODE_POST_INC,
 853                                          sg_dma_address(sg), 0, 0);
 854                 omap_set_dma_dest_data_pack(dma_ch, 1);
 855                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 856         } else {
 857                 buf = 0x0f80 | ((frame - 1) << 0);
 858
 859                 if (cpu_class_is_omap1()) {
 860                         src_port = OMAP_DMA_PORT_EMIFF;
 861                         dst_port = OMAP_DMA_PORT_TIPB;
 862                 }
 863                 if (cpu_is_omap24xx())
 864                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 865
 866                 omap_set_dma_dest_params(dma_ch, dst_port,
 867                                          OMAP_DMA_AMODE_CONSTANT,
 868                                          data_addr, 0, 0);
 869                 omap_set_dma_src_params(dma_ch, src_port,
 870                                         OMAP_DMA_AMODE_POST_INC,
 871                                         sg_dma_address(sg), 0, 0);
 872                 omap_set_dma_src_data_pack(dma_ch, 1);
 873                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 874         }
 875
 876         /* Max limit for DMA frame count is 0xffff */
 877         BUG_ON(count > 0xffff);
 878
 879         OMAP_MMC_WRITE(host, BUF, buf);
 880         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 881                                      frame, count, OMAP_DMA_SYNC_FRAME,
 882                                      sync_dev, 0);
 883 }
 884
 885 /* A scatterlist segment completed */
 886 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 887 {
 888         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 889         struct mmc_data *mmcdat = host->data;
 890
 891         if (unlikely(host->dma_ch < 0)) {
 892                 dev_err(mmc_dev(host->mmc),
 893                         "DMA callback while DMA not enabled\n");
 894                 return;
 895         }
 896         /* FIXME: We really should do something to _handle_ the errors */
 897         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 898                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 899                 return;
 900         }
 901         if (ch_status & OMAP_DMA_DROP_IRQ) {
 902                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 903                 return;
 904         }
 905         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 906                 return;
 907         }
 908         mmcdat->bytes_xfered += host->dma_len;
 909         host->sg_idx++;
 910         if (host->sg_idx < host->sg_len) {
 911                 mmc_omap_prepare_dma(host, host->data);
 912                 omap_start_dma(host->dma_ch);
 913         } else
 914                 mmc_omap_dma_done(host, host->data);
 915 }
 916
 917 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 918 {
 919         const char *dev_name;
 920         int sync_dev, dma_ch, is_read, r;
 921
 922         is_read = !(data->flags & MMC_DATA_WRITE);
 923         del_timer_sync(&host->dma_timer);
 924         if (host->dma_ch >= 0) {
 925                 if (is_read == host->dma_is_read)
 926                         return 0;
 927                 omap_free_dma(host->dma_ch);
 928                 host->dma_ch = -1;
 929         }
 930
 931         if (is_read) {
 932                 if (host->id == 1) {
 933                         sync_dev = OMAP_DMA_MMC_RX;
 934                         dev_name = "MMC1 read";
 935                 } else {
 936                         sync_dev = OMAP_DMA_MMC2_RX;
 937                         dev_name = "MMC2 read";
 938                 }
 939         } else {
 940                 if (host->id == 1) {
 941                         sync_dev = OMAP_DMA_MMC_TX;
 942                         dev_name = "MMC1 write";
 943                 } else {
 944                         sync_dev = OMAP_DMA_MMC2_TX;
 945                         dev_name = "MMC2 write";
 946                 }
 947         }
 948         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 949                              host, &dma_ch);
 950         if (r != 0) {
 951                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 952                 return r;
 953         }
 954         host->dma_ch = dma_ch;
 955         host->dma_is_read = is_read;
 956
 957         return 0;
 958 }
 959
 960 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 961 {
 962         u16 reg;
 963
 964         reg = OMAP_MMC_READ(host, SDIO);
 965         reg &= ~(1 << 5);
 966         OMAP_MMC_WRITE(host, SDIO, reg);
 967         /* Set maximum timeout */
 968         OMAP_MMC_WRITE(host, CTO, 0xff);
 969 }
 970
 971 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 972 {
 973         unsigned int timeout, cycle_ns;
 974         u16 reg;
 975
 976         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 977         timeout = req->data->timeout_ns / cycle_ns;
 978         timeout += req->data->timeout_clks;
 979
 980         /* Check if we need to use timeout multiplier register */
 981         reg = OMAP_MMC_READ(host, SDIO);
 982         if (timeout > 0xffff) {
 983                 reg |= (1 << 5);
 984                 timeout /= 1024;
 985         } else
 986                 reg &= ~(1 << 5);
 987         OMAP_MMC_WRITE(host, SDIO, reg);
 988         OMAP_MMC_WRITE(host, DTO, timeout);
 989 }
 990
 991 static void
 992 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 993 {
 994         struct mmc_data *data = req->data;
 995         int i, use_dma, block_size;
 996         unsigned sg_len;
 997
 998         host->data = data;
 999         if (data == NULL) {
1000                 OMAP_MMC_WRITE(host, BLEN, 0);
1001                 OMAP_MMC_WRITE(host, NBLK, 0);
1002                 OMAP_MMC_WRITE(host, BUF, 0);
1003                 host->dma_in_use = 0;
1004                 set_cmd_timeout(host, req);
1005                 return;
1006         }
1007
1008         block_size = data->blksz;
1009
1010         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1011         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1012         set_data_timeout(host, req);
1013
1014         /* cope with calling layer confusion; it issues "single
1015          * block" writes using multi-block scatterlists.
1016          */
1017         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1018
1019         /* Only do DMA for entire blocks */
1020         use_dma = host->use_dma;
1021         if (use_dma) {
1022                 for (i = 0; i < sg_len; i++) {
1023                         if ((data->sg[i].length % block_size) != 0) {
1024                                 use_dma = 0;
1025                                 break;
1026                         }
1027                 }
1028         }
1029
1030         host->sg_idx = 0;
1031         if (use_dma) {
1032                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1033                         enum dma_data_direction dma_data_dir;
1034
1035                         if (data->flags & MMC_DATA_WRITE)
1036                                 dma_data_dir = DMA_TO_DEVICE;
1037                         else
1038                                 dma_data_dir = DMA_FROM_DEVICE;
1039
1040                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1041                                                 sg_len, dma_data_dir);
1042                         host->total_bytes_left = 0;
1043                         mmc_omap_prepare_dma(host, req->data);
1044                         host->brs_received = 0;
1045                         host->dma_done = 0;
1046                         host->dma_in_use = 1;
1047                 } else
1048                         use_dma = 0;
1049         }
1050
1051         /* Revert to PIO? */
1052         if (!use_dma) {
1053                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1054                 host->total_bytes_left = data->blocks * block_size;
1055                 host->sg_len = sg_len;
1056                 mmc_omap_sg_to_buf(host);
1057                 host->dma_in_use = 0;
1058         }
1059 }
1060
1061 static void mmc_omap_start_request(struct mmc_omap_host *host,
1062                                    struct mmc_request *req)
1063 {
1064         BUG_ON(host->mrq != NULL);
1065
1066         host->mrq = req;
1067
1068         /* only touch fifo AFTER the controller readies it */
1069         mmc_omap_prepare_data(host, req);
1070         mmc_omap_start_command(host, req->cmd);
1071         if (host->dma_in_use)
1072                 omap_start_dma(host->dma_ch);
1073         BUG_ON(irqs_disabled());
1074 }
1075
1076 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1077 {
1078         struct mmc_omap_slot *slot = mmc_priv(mmc);
1079         struct mmc_omap_host *host = slot->host;
1080         unsigned long flags;
1081
1082         spin_lock_irqsave(&host->slot_lock, flags);
1083         if (host->mmc != NULL) {
1084                 BUG_ON(slot->mrq != NULL);
1085                 slot->mrq = req;
1086                 spin_unlock_irqrestore(&host->slot_lock, flags);
1087                 return;
1088         } else
1089                 host->mmc = mmc;
1090         spin_unlock_irqrestore(&host->slot_lock, flags);
1091         mmc_omap_select_slot(slot, 1);
1092         mmc_omap_start_request(host, req);
1093 }
1094
1095 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1096                                 int vdd)
1097 {
1098         struct mmc_omap_host *host;
1099
1100         host = slot->host;
1101
1102         if (slot->pdata->set_power != NULL)
1103                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1104                                         vdd);
1105
1106         if (cpu_is_omap24xx()) {
1107                 u16 w;
1108
1109                 if (power_on) {
1110                         w = OMAP_MMC_READ(host, CON);
1111                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1112                 } else {
1113                         w = OMAP_MMC_READ(host, CON);
1114                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1115                 }
1116         }
1117 }
1118
1119 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1120 {
1121         struct mmc_omap_slot *slot = mmc_priv(mmc);
1122         struct mmc_omap_host *host = slot->host;
1123         int func_clk_rate = clk_get_rate(host->fclk);
1124         int dsor;
1125
1126         if (ios->clock == 0)
1127                 return 0;
1128
1129         dsor = func_clk_rate / ios->clock;
1130         if (dsor < 1)
1131                 dsor = 1;
1132
1133         if (func_clk_rate / dsor > ios->clock)
1134                 dsor++;
1135
1136         if (dsor > 250)
1137                 dsor = 250;
1138
1139         slot->fclk_freq = func_clk_rate / dsor;
1140
1141         if (ios->bus_width == MMC_BUS_WIDTH_4)
1142                 dsor |= 1 << 15;
1143
1144         return dsor;
1145 }
1146
1147 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1148 {
1149         struct mmc_omap_slot *slot = mmc_priv(mmc);
1150         struct mmc_omap_host *host = slot->host;
1151         int i, dsor;
1152
1153         dsor = mmc_omap_calc_divisor(mmc, ios);
1154
1155         mmc_omap_select_slot(slot, 0);
1156
1157         if (ios->vdd != slot->vdd)
1158                 slot->vdd = ios->vdd;
1159
1160         switch (ios->power_mode) {
1161         case MMC_POWER_OFF:
1162                 mmc_omap_set_power(slot, 0, ios->vdd);
1163                 break;
1164         case MMC_POWER_UP:
1165                 /* Cannot touch dsor yet, just power up MMC */
1166                 mmc_omap_set_power(slot, 1, ios->vdd);
1167                 goto exit;
1168         case MMC_POWER_ON:
1169                 dsor |= 1 << 11;
1170                 break;
1171         }
1172
1173         if (slot->bus_mode != ios->bus_mode) {
1174                 if (slot->pdata->set_bus_mode != NULL)
1175                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1176                                                   ios->bus_mode);
1177                 slot->bus_mode = ios->bus_mode;
1178         }
1179
1180         /* On insanely high arm_per frequencies something sometimes
1181          * goes somehow out of sync, and the POW bit is not being set,
1182          * which results in the while loop below getting stuck.
1183          * Writing to the CON register twice seems to do the trick. */
1184         for (i = 0; i < 2; i++)
1185                 OMAP_MMC_WRITE(host, CON, dsor);
1186         slot->saved_con = dsor;
1187         if (ios->power_mode == MMC_POWER_ON) {
1188                 /* Send clock cycles, poll completion */
1189                 OMAP_MMC_WRITE(host, IE, 0);
1190                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1191                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1192                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1193                 OMAP_MMC_WRITE(host, STAT, 1);
1194         }
1195
1196 exit:
1197         mmc_omap_release_slot(slot);
1198 }
1199
1200 static const struct mmc_host_ops mmc_omap_ops = {
1201         .request        = mmc_omap_request,
1202         .set_ios        = mmc_omap_set_ios,
1203 };
1204
1205 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1206 {
1207         struct mmc_omap_slot *slot = NULL;
1208         struct mmc_host *mmc;
1209         int r;
1210
1211         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1212         if (mmc == NULL)
1213                 return -ENOMEM;
1214
1215         slot = mmc_priv(mmc);
1216         slot->host = host;
1217         slot->mmc = mmc;
1218         slot->id = id;
1219         slot->pdata = &host->pdata->slots[id];
1220
1221         host->slots[id] = slot;
1222
1223         mmc->caps = MMC_CAP_MULTIWRITE;
1224         if (host->pdata->conf.wire4)
1225                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1226
1227         mmc->ops = &mmc_omap_ops;
1228         mmc->f_min = 400000;
1229
1230         if (cpu_class_is_omap2())
1231                 mmc->f_max = 48000000;
1232         else
1233                 mmc->f_max = 24000000;
1234         if (host->pdata->max_freq)
1235                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1236         mmc->ocr_avail = slot->pdata->ocr_mask;
1237
1238         /* Use scatterlist DMA to reduce per-transfer costs.
1239          * NOTE max_seg_size assumption that small blocks aren't
1240          * normally used (except e.g. for reading SD registers).
1241          */
1242         mmc->max_phys_segs = 32;
1243         mmc->max_hw_segs = 32;
1244         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1245         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1246         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1247         mmc->max_seg_size = mmc->max_req_size;
1248
1249         r = mmc_add_host(mmc);
1250         if (r < 0)
1251                 goto err_remove_host;
1252
1253         if (slot->pdata->name != NULL) {
1254                 r = device_create_file(&mmc->class_dev,
1255                                         &dev_attr_slot_name);
1256                 if (r < 0)
1257                         goto err_remove_host;
1258         }
1259
1260         if (slot->pdata->get_cover_state != NULL) {
1261                 r = device_create_file(&mmc->class_dev,
1262                                         &dev_attr_cover_switch);
1263                 if (r < 0)
1264                         goto err_remove_slot_name;
1265
1266                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1267                             (unsigned long)slot);
1268                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1269                              (unsigned long)slot);
1270                 tasklet_schedule(&slot->cover_tasklet);
1271         }
1272
1273         return 0;
1274
1275 err_remove_slot_name:
1276         if (slot->pdata->name != NULL)
1277                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1278 err_remove_host:
1279         mmc_remove_host(mmc);
1280         mmc_free_host(mmc);
1281         return r;
1282 }
1283
1284 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1285 {
1286         struct mmc_host *mmc = slot->mmc;
1287
1288         if (slot->pdata->name != NULL)
1289                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1290         if (slot->pdata->get_cover_state != NULL)
1291                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1292
1293         tasklet_kill(&slot->cover_tasklet);
1294         del_timer_sync(&slot->cover_timer);
1295         flush_scheduled_work();
1296
1297         mmc_remove_host(mmc);
1298         mmc_free_host(mmc);
1299 }
1300
1301 static int __init mmc_omap_probe(struct platform_device *pdev)
1302 {
1303         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1304         struct mmc_omap_host *host = NULL;
1305         struct resource *res;
1306         int i, ret = 0;
1307         int irq;
1308
1309         if (pdata == NULL) {
1310                 dev_err(&pdev->dev, "platform data missing\n");
1311                 return -ENXIO;
1312         }
1313         if (pdata->nr_slots == 0) {
1314                 dev_err(&pdev->dev, "no slots\n");
1315                 return -ENXIO;
1316         }
1317
1318         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1319         irq = platform_get_irq(pdev, 0);
1320         if (res == NULL || irq < 0)
1321                 return -ENXIO;
1322
1323         res = request_mem_region(res->start, res->end - res->start + 1,
1324                                  pdev->name);
1325         if (res == NULL)
1326                 return -EBUSY;
1327
1328         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1329         if (host == NULL) {
1330                 ret = -ENOMEM;
1331                 goto err_free_mem_region;
1332         }
1333
1334         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1335         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1336                     (unsigned long) host);
1337
1338         spin_lock_init(&host->dma_lock);
1339         setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1340         spin_lock_init(&host->slot_lock);
1341         init_waitqueue_head(&host->slot_wq);
1342
1343         host->pdata = pdata;
1344         host->dev = &pdev->dev;
1345         platform_set_drvdata(pdev, host);
1346
1347         host->id = pdev->id;
1348         host->mem_res = res;
1349         host->irq = irq;
1350
1351         host->use_dma = 1;
1352         host->dma_ch = -1;
1353
1354         host->irq = irq;
1355         host->phys_base = host->mem_res->start;
1356         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1357
1358         if (cpu_is_omap24xx()) {
1359                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1360                 if (IS_ERR(host->iclk))
1361                         goto err_free_mmc_host;
1362                 clk_enable(host->iclk);
1363         }
1364
1365         if (!cpu_is_omap24xx())
1366                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1367         else
1368                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1369
1370         if (IS_ERR(host->fclk)) {
1371                 ret = PTR_ERR(host->fclk);
1372                 goto err_free_iclk;
1373         }
1374
1375         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1376         if (ret)
1377                 goto err_free_fclk;
1378
1379         if (pdata->init != NULL) {
1380                 ret = pdata->init(&pdev->dev);
1381                 if (ret < 0)
1382                         goto err_free_irq;
1383         }
1384
1385         host->nr_slots = pdata->nr_slots;
1386         for (i = 0; i < pdata->nr_slots; i++) {
1387                 ret = mmc_omap_new_slot(host, i);
1388                 if (ret < 0) {
1389                         while (--i >= 0)
1390                                 mmc_omap_remove_slot(host->slots[i]);
1391
1392                         goto err_plat_cleanup;
1393                 }
1394         }
1395
1396         return 0;
1397
1398 err_plat_cleanup:
1399         if (pdata->cleanup)
1400                 pdata->cleanup(&pdev->dev);
1401 err_free_irq:
1402         free_irq(host->irq, host);
1403 err_free_fclk:
1404         clk_put(host->fclk);
1405 err_free_iclk:
1406         if (host->iclk != NULL) {
1407                 clk_disable(host->iclk);
1408                 clk_put(host->iclk);
1409         }
1410 err_free_mmc_host:
1411         kfree(host);
1412 err_free_mem_region:
1413         release_mem_region(res->start, res->end - res->start + 1);
1414         return ret;
1415 }
1416
1417 static int mmc_omap_remove(struct platform_device *pdev)
1418 {
1419         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1420         int i;
1421
1422         platform_set_drvdata(pdev, NULL);
1423
1424         BUG_ON(host == NULL);
1425
1426         for (i = 0; i < host->nr_slots; i++)
1427                 mmc_omap_remove_slot(host->slots[i]);
1428
1429         if (host->pdata->cleanup)
1430                 host->pdata->cleanup(&pdev->dev);
1431
1432         if (host->iclk && !IS_ERR(host->iclk))
1433                 clk_put(host->iclk);
1434         if (host->fclk && !IS_ERR(host->fclk))
1435                 clk_put(host->fclk);
1436
1437         release_mem_region(pdev->resource[0].start,
1438                            pdev->resource[0].end - pdev->resource[0].start + 1);
1439
1440         kfree(host);
1441
1442         return 0;
1443 }
1444
1445 #ifdef CONFIG_PM
1446 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1447 {
1448         int i, ret = 0;
1449         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1450
1451         if (host == NULL || host->suspended)
1452                 return 0;
1453
1454         for (i = 0; i < host->nr_slots; i++) {
1455                 struct mmc_omap_slot *slot;
1456
1457                 slot = host->slots[i];
1458                 ret = mmc_suspend_host(slot->mmc, mesg);
1459                 if (ret < 0) {
1460                         while (--i >= 0) {
1461                                 slot = host->slots[i];
1462                                 mmc_resume_host(slot->mmc);
1463                         }
1464                         return ret;
1465                 }
1466         }
1467         host->suspended = 1;
1468         return 0;
1469 }
1470
1471 static int mmc_omap_resume(struct platform_device *pdev)
1472 {
1473         int i, ret = 0;
1474         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1475
1476         if (host == NULL || !host->suspended)
1477                 return 0;
1478
1479         for (i = 0; i < host->nr_slots; i++) {
1480                 struct mmc_omap_slot *slot;
1481                 slot = host->slots[i];
1482                 ret = mmc_resume_host(slot->mmc);
1483                 if (ret < 0)
1484                         return ret;
1485
1486                 host->suspended = 0;
1487         }
1488         return 0;
1489 }
1490 #else
1491 #define mmc_omap_suspend        NULL
1492 #define mmc_omap_resume         NULL
1493 #endif
1494
1495 static struct platform_driver mmc_omap_driver = {
1496         .probe          = mmc_omap_probe,
1497         .remove         = mmc_omap_remove,
1498         .suspend        = mmc_omap_suspend,
1499         .resume         = mmc_omap_resume,
1500         .driver         = {
1501                 .name   = DRIVER_NAME,
1502                 .owner  = THIS_MODULE,
1503         },
1504 };
1505
1506 static int __init mmc_omap_init(void)
1507 {
1508         return platform_driver_register(&mmc_omap_driver);
1509 }
1510
1511 static void __exit mmc_omap_exit(void)
1512 {
1513         platform_driver_unregister(&mmc_omap_driver);
1514 }
1515
1516 module_init(mmc_omap_init);
1517 module_exit(mmc_omap_exit);
1518
1519 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1520 MODULE_LICENSE("GPL");
1521 MODULE_ALIAS("platform:" DRIVER_NAME);
1522 MODULE_AUTHOR("Juha Yrjölä");