drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/timer.h>
  29 #include <linux/clk.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of_device.h>
  33 #include <linux/omap-dma.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/core.h>
  36 #include <linux/mmc/mmc.h>
  37 #include <linux/io.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/pinctrl/consumer.h>
  41 #include <linux/pm_runtime.h>
  42 #include <mach/hardware.h>
  43 #include <plat/mmc.h>
  44 #include <plat/cpu.h>
  45
  46 /* OMAP HSMMC Host Controller Registers */
  47 #define OMAP_HSMMC_SYSSTATUS    0x0014
  48 #define OMAP_HSMMC_CON          0x002C
  49 #define OMAP_HSMMC_BLK          0x0104
  50 #define OMAP_HSMMC_ARG          0x0108
  51 #define OMAP_HSMMC_CMD          0x010C
  52 #define OMAP_HSMMC_RSP10        0x0110
  53 #define OMAP_HSMMC_RSP32        0x0114
  54 #define OMAP_HSMMC_RSP54        0x0118
  55 #define OMAP_HSMMC_RSP76        0x011C
  56 #define OMAP_HSMMC_DATA         0x0120
  57 #define OMAP_HSMMC_HCTL         0x0128
  58 #define OMAP_HSMMC_SYSCTL       0x012C
  59 #define OMAP_HSMMC_STAT         0x0130
  60 #define OMAP_HSMMC_IE           0x0134
  61 #define OMAP_HSMMC_ISE          0x0138
  62 #define OMAP_HSMMC_CAPA         0x0140
  63
  64 #define VS18                    (1 << 26)
  65 #define VS30                    (1 << 25)
  66 #define HSS                     (1 << 21)
  67 #define SDVS18                  (0x5 << 9)
  68 #define SDVS30                  (0x6 << 9)
  69 #define SDVS33                  (0x7 << 9)
  70 #define SDVS_MASK               0x00000E00
  71 #define SDVSCLR                 0xFFFFF1FF
  72 #define SDVSDET                 0x00000400
  73 #define AUTOIDLE                0x1
  74 #define SDBP                    (1 << 8)
  75 #define DTO                     0xe
  76 #define ICE                     0x1
  77 #define ICS                     0x2
  78 #define CEN                     (1 << 2)
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INT_EN_MASK             0x307F0033
  84 #define BWR_ENABLE              (1 << 4)
  85 #define BRR_ENABLE              (1 << 5)
  86 #define DTO_ENABLE              (1 << 20)
  87 #define INIT_STREAM             (1 << 1)
  88 #define DP_SELECT               (1 << 21)
  89 #define DDIR                    (1 << 4)
  90 #define DMA_EN                  0x1
  91 #define MSBS                    (1 << 5)
  92 #define BCE                     (1 << 1)
  93 #define FOUR_BIT                (1 << 1)
  94 #define HSPE                    (1 << 2)
  95 #define DDR                     (1 << 19)
  96 #define DW8                     (1 << 5)
  97 #define CC                      0x1
  98 #define TC                      0x02
  99 #define OD                      0x1
 100 #define ERR                     (1 << 15)
 101 #define CMD_TIMEOUT             (1 << 16)
 102 #define DATA_TIMEOUT            (1 << 20)
 103 #define CMD_CRC                 (1 << 17)
 104 #define DATA_CRC                (1 << 21)
 105 #define CARD_ERR                (1 << 28)
 106 #define STAT_CLEAR              0xFFFFFFFF
 107 #define INIT_STREAM_CMD         0x00000000
 108 #define DUAL_VOLT_OCR_BIT       7
 109 #define SRC                     (1 << 25)
 110 #define SRD                     (1 << 26)
 111 #define SOFTRESET               (1 << 1)
 112 #define RESETDONE               (1 << 0)
 113
 114 #define MMC_AUTOSUSPEND_DELAY   100
 115 #define MMC_TIMEOUT_MS          20
 116 #define OMAP_MMC_MIN_CLOCK      400000
 117 #define OMAP_MMC_MAX_CLOCK      52000000
 118 #define DRIVER_NAME             "omap_hsmmc"
 119
 120 /*
 121  * One controller can have multiple slots, like on some omap boards using
 122  * omap.c controller driver. Luckily this is not currently done on any known
 123  * omap_hsmmc.c device.
 124  */
 125 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 126
 127 /*
 128  * MMC Host controller read/write API's
 129  */
 130 #define OMAP_HSMMC_READ(base, reg)      \
 131         __raw_readl((base) + OMAP_HSMMC_##reg)
 132
 133 #define OMAP_HSMMC_WRITE(base, reg, val) \
 134         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 135
 136 struct omap_hsmmc_next {
 137         unsigned int    dma_len;
 138         s32             cookie;
 139 };
 140
 141 struct omap_hsmmc_host {
 142         struct  device          *dev;
 143         struct  mmc_host        *mmc;
 144         struct  mmc_request     *mrq;
 145         struct  mmc_command     *cmd;
 146         struct  mmc_data        *data;
 147         struct  clk             *fclk;
 148         struct  clk             *dbclk;
 149         /*
 150          * vcc == configured supply
 151          * vcc_aux == optional
 152          *   -  MMC1, supply for DAT4..DAT7
 153          *   -  MMC2/MMC2, external level shifter voltage supply, for
 154          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 155          */
 156         struct  regulator       *vcc;
 157         struct  regulator       *vcc_aux;
 158         void    __iomem         *base;
 159         resource_size_t         mapbase;
 160         spinlock_t              irq_lock; /* Prevent races with irq handler */
 161         unsigned int            dma_len;
 162         unsigned int            dma_sg_idx;
 163         unsigned char           bus_mode;
 164         unsigned char           power_mode;
 165         int                     suspended;
 166         int                     irq;
 167         int                     use_dma, dma_ch;
 168         struct dma_chan         *tx_chan;
 169         struct dma_chan         *rx_chan;
 170         int                     slot_id;
 171         int                     response_busy;
 172         int                     context_loss;
 173         int                     protect_card;
 174         int                     reqs_blocked;
 175         int                     use_reg;
 176         int                     req_in_progress;
 177         struct omap_hsmmc_next  next_data;
 178
 179         struct  omap_mmc_platform_data  *pdata;
 180 };
 181
 182 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 183 {
 184         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 185         struct omap_mmc_platform_data *mmc = host->pdata;
 186
 187         /* NOTE: assumes card detect signal is active-low */
 188         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 189 }
 190
 191 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 192 {
 193         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 194         struct omap_mmc_platform_data *mmc = host->pdata;
 195
 196         /* NOTE: assumes write protect signal is active-high */
 197         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 198 }
 199
 200 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 201 {
 202         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 203         struct omap_mmc_platform_data *mmc = host->pdata;
 204
 205         /* NOTE: assumes card detect signal is active-low */
 206         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 207 }
 208
 209 #ifdef CONFIG_PM
 210
 211 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 212 {
 213         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 214         struct omap_mmc_platform_data *mmc = host->pdata;
 215
 216         disable_irq(mmc->slots[0].card_detect_irq);
 217         return 0;
 218 }
 219
 220 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 221 {
 222         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 223         struct omap_mmc_platform_data *mmc = host->pdata;
 224
 225         enable_irq(mmc->slots[0].card_detect_irq);
 226         return 0;
 227 }
 228
 229 #else
 230
 231 #define omap_hsmmc_suspend_cdirq        NULL
 232 #define omap_hsmmc_resume_cdirq         NULL
 233
 234 #endif
 235
 236 #ifdef CONFIG_REGULATOR
 237
 238 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 239                                    int vdd)
 240 {
 241         struct omap_hsmmc_host *host =
 242                 platform_get_drvdata(to_platform_device(dev));
 243         int ret = 0;
 244
 245         /*
 246          * If we don't see a Vcc regulator, assume it's a fixed
 247          * voltage always-on regulator.
 248          */
 249         if (!host->vcc)
 250                 return 0;
 251         /*
 252          * With DT, never turn OFF the regulator. This is because
 253          * the pbias cell programming support is still missing when
 254          * booting with Device tree
 255          */
 256         if (dev->of_node && !vdd)
 257                 return 0;
 258
 259         if (mmc_slot(host).before_set_reg)
 260                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 261
 262         /*
 263          * Assume Vcc regulator is used only to power the card ... OMAP
 264          * VDDS is used to power the pins, optionally with a transceiver to
 265          * support cards using voltages other than VDDS (1.8V nominal).  When a
 266          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 267          *
 268          * In some cases this regulator won't support enable/disable;
 269          * e.g. it's a fixed rail for a WLAN chip.
 270          *
 271          * In other cases vcc_aux switches interface power.  Example, for
 272          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 273          * chips/cards need an interface voltage rail too.
 274          */
 275         if (power_on) {
 276                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 277                 /* Enable interface voltage rail, if needed */
 278                 if (ret == 0 && host->vcc_aux) {
 279                         ret = regulator_enable(host->vcc_aux);
 280                         if (ret < 0)
 281                                 ret = mmc_regulator_set_ocr(host->mmc,
 282                                                         host->vcc, 0);
 283                 }
 284         } else {
 285                 /* Shut down the rail */
 286                 if (host->vcc_aux)
 287                         ret = regulator_disable(host->vcc_aux);
 288                 if (!ret) {
 289                         /* Then proceed to shut down the local regulator */
 290                         ret = mmc_regulator_set_ocr(host->mmc,
 291                                                 host->vcc, 0);
 292                 }
 293         }
 294
 295         if (mmc_slot(host).after_set_reg)
 296                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 297
 298         return ret;
 299 }
 300
 301 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 302 {
 303         struct regulator *reg;
 304         int ocr_value = 0;
 305
 306         reg = regulator_get(host->dev, "vmmc");
 307         if (IS_ERR(reg)) {
 308                 dev_dbg(host->dev, "vmmc regulator missing\n");
 309                 return PTR_ERR(reg);
 310         } else {
 311                 mmc_slot(host).set_power = omap_hsmmc_set_power;
 312                 host->vcc = reg;
 313                 ocr_value = mmc_regulator_get_ocrmask(reg);
 314                 if (!mmc_slot(host).ocr_mask) {
 315                         mmc_slot(host).ocr_mask = ocr_value;
 316                 } else {
 317                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 318                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 319                                         mmc_slot(host).ocr_mask);
 320                                 mmc_slot(host).ocr_mask = 0;
 321                                 return -EINVAL;
 322                         }
 323                 }
 324
 325                 /* Allow an aux regulator */
 326                 reg = regulator_get(host->dev, "vmmc_aux");
 327                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 328
 329                 /* For eMMC do not power off when not in sleep state */
 330                 if (mmc_slot(host).no_regulator_off_init)
 331                         return 0;
 332                 /*
 333                 * UGLY HACK:  workaround regulator framework bugs.
 334                 * When the bootloader leaves a supply active, it's
 335                 * initialized with zero usecount ... and we can't
 336                 * disable it without first enabling it.  Until the
 337                 * framework is fixed, we need a workaround like this
 338                 * (which is safe for MMC, but not in general).
 339                 */
 340                 if (regulator_is_enabled(host->vcc) > 0 ||
 341                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 342                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 343
 344                         mmc_slot(host).set_power(host->dev, host->slot_id,
 345                                                  1, vdd);
 346                         mmc_slot(host).set_power(host->dev, host->slot_id,
 347                                                  0, 0);
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 355 {
 356         regulator_put(host->vcc);
 357         regulator_put(host->vcc_aux);
 358         mmc_slot(host).set_power = NULL;
 359 }
 360
 361 static inline int omap_hsmmc_have_reg(void)
 362 {
 363         return 1;
 364 }
 365
 366 #else
 367
 368 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 369 {
 370         return -EINVAL;
 371 }
 372
 373 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 374 {
 375 }
 376
 377 static inline int omap_hsmmc_have_reg(void)
 378 {
 379         return 0;
 380 }
 381
 382 #endif
 383
 384 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 385 {
 386         int ret;
 387
 388         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 389                 if (pdata->slots[0].cover)
 390                         pdata->slots[0].get_cover_state =
 391                                         omap_hsmmc_get_cover_state;
 392                 else
 393                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 394                 pdata->slots[0].card_detect_irq =
 395                                 gpio_to_irq(pdata->slots[0].switch_pin);
 396                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 397                 if (ret)
 398                         return ret;
 399                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 400                 if (ret)
 401                         goto err_free_sp;
 402         } else
 403                 pdata->slots[0].switch_pin = -EINVAL;
 404
 405         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 406                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 407                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 408                 if (ret)
 409                         goto err_free_cd;
 410                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 411                 if (ret)
 412                         goto err_free_wp;
 413         } else
 414                 pdata->slots[0].gpio_wp = -EINVAL;
 415
 416         return 0;
 417
 418 err_free_wp:
 419         gpio_free(pdata->slots[0].gpio_wp);
 420 err_free_cd:
 421         if (gpio_is_valid(pdata->slots[0].switch_pin))
 422 err_free_sp:
 423                 gpio_free(pdata->slots[0].switch_pin);
 424         return ret;
 425 }
 426
 427 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 428 {
 429         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 430                 gpio_free(pdata->slots[0].gpio_wp);
 431         if (gpio_is_valid(pdata->slots[0].switch_pin))
 432                 gpio_free(pdata->slots[0].switch_pin);
 433 }
 434
 435 /*
 436  * Start clock to the card
 437  */
 438 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 439 {
 440         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 441                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 442 }
 443
 444 /*
 445  * Stop clock to the card
 446  */
 447 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 448 {
 449         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 450                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 451         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 452                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 453 }
 454
 455 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 456                                   struct mmc_command *cmd)
 457 {
 458         unsigned int irq_mask;
 459
 460         if (host->use_dma)
 461                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 462         else
 463                 irq_mask = INT_EN_MASK;
 464
 465         /* Disable timeout for erases */
 466         if (cmd->opcode == MMC_ERASE)
 467                 irq_mask &= ~DTO_ENABLE;
 468
 469         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 470         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 471         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 472 }
 473
 474 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 475 {
 476         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 477         OMAP_HSMMC_WRITE(host->base, IE, 0);
 478         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 479 }
 480
 481 /* Calculate divisor for the given clock frequency */
 482 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 483 {
 484         u16 dsor = 0;
 485
 486         if (ios->clock) {
 487                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 488                 if (dsor > 250)
 489                         dsor = 250;
 490         }
 491
 492         return dsor;
 493 }
 494
 495 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 496 {
 497         struct mmc_ios *ios = &host->mmc->ios;
 498         unsigned long regval;
 499         unsigned long timeout;
 500         unsigned long clkdiv;
 501
 502         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 503
 504         omap_hsmmc_stop_clock(host);
 505
 506         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 507         regval = regval & ~(CLKD_MASK | DTO_MASK);
 508         clkdiv = calc_divisor(host, ios);
 509         regval = regval | (clkdiv << 6) | (DTO << 16);
 510         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 511         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 512                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 513
 514         /* Wait till the ICS bit is set */
 515         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 516         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 517                 && time_before(jiffies, timeout))
 518                 cpu_relax();
 519
 520         /*
 521          * Enable High-Speed Support
 522          * Pre-Requisites
 523          *      - Controller should support High-Speed-Enable Bit
 524          *      - Controller should not be using DDR Mode
 525          *      - Controller should advertise that it supports High Speed
 526          *        in capabilities register
 527          *      - MMC/SD clock coming out of controller > 25MHz
 528          */
 529         if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
 530             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 531             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 532                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 533                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 534                         regval |= HSPE;
 535                 else
 536                         regval &= ~HSPE;
 537
 538                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 539         }
 540
 541         omap_hsmmc_start_clock(host);
 542 }
 543
 544 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 545 {
 546         struct mmc_ios *ios = &host->mmc->ios;
 547         u32 con;
 548
 549         con = OMAP_HSMMC_READ(host->base, CON);
 550         if (ios->timing == MMC_TIMING_UHS_DDR50)
 551                 con |= DDR;     /* configure in DDR mode */
 552         else
 553                 con &= ~DDR;
 554         switch (ios->bus_width) {
 555         case MMC_BUS_WIDTH_8:
 556                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 557                 break;
 558         case MMC_BUS_WIDTH_4:
 559                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 560                 OMAP_HSMMC_WRITE(host->base, HCTL,
 561                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 562                 break;
 563         case MMC_BUS_WIDTH_1:
 564                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 565                 OMAP_HSMMC_WRITE(host->base, HCTL,
 566                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 567                 break;
 568         }
 569 }
 570
 571 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 572 {
 573         struct mmc_ios *ios = &host->mmc->ios;
 574         u32 con;
 575
 576         con = OMAP_HSMMC_READ(host->base, CON);
 577         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 578                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 579         else
 580                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 581 }
 582
 583 #ifdef CONFIG_PM
 584
 585 /*
 586  * Restore the MMC host context, if it was lost as result of a
 587  * power state change.
 588  */
 589 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 590 {
 591         struct mmc_ios *ios = &host->mmc->ios;
 592         struct omap_mmc_platform_data *pdata = host->pdata;
 593         int context_loss = 0;
 594         u32 hctl, capa;
 595         unsigned long timeout;
 596
 597         if (pdata->get_context_loss_count) {
 598                 context_loss = pdata->get_context_loss_count(host->dev);
 599                 if (context_loss < 0)
 600                         return 1;
 601         }
 602
 603         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 604                 context_loss == host->context_loss ? "not " : "");
 605         if (host->context_loss == context_loss)
 606                 return 1;
 607
 608         if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
 609                 return 1;
 610
 611         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 612                 if (host->power_mode != MMC_POWER_OFF &&
 613                     (1 << ios->vdd) <= MMC_VDD_23_24)
 614                         hctl = SDVS18;
 615                 else
 616                         hctl = SDVS30;
 617                 capa = VS30 | VS18;
 618         } else {
 619                 hctl = SDVS18;
 620                 capa = VS18;
 621         }
 622
 623         OMAP_HSMMC_WRITE(host->base, HCTL,
 624                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 625
 626         OMAP_HSMMC_WRITE(host->base, CAPA,
 627                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 628
 629         OMAP_HSMMC_WRITE(host->base, HCTL,
 630                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 631
 632         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 633         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 634                 && time_before(jiffies, timeout))
 635                 ;
 636
 637         omap_hsmmc_disable_irq(host);
 638
 639         /* Do not initialize card-specific things if the power is off */
 640         if (host->power_mode == MMC_POWER_OFF)
 641                 goto out;
 642
 643         omap_hsmmc_set_bus_width(host);
 644
 645         omap_hsmmc_set_clock(host);
 646
 647         omap_hsmmc_set_bus_mode(host);
 648
 649 out:
 650         host->context_loss = context_loss;
 651
 652         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 653         return 0;
 654 }
 655
 656 /*
 657  * Save the MMC host context (store the number of power state changes so far).
 658  */
 659 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 660 {
 661         struct omap_mmc_platform_data *pdata = host->pdata;
 662         int context_loss;
 663
 664         if (pdata->get_context_loss_count) {
 665                 context_loss = pdata->get_context_loss_count(host->dev);
 666                 if (context_loss < 0)
 667                         return;
 668                 host->context_loss = context_loss;
 669         }
 670 }
 671
 672 #else
 673
 674 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 675 {
 676         return 0;
 677 }
 678
 679 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 680 {
 681 }
 682
 683 #endif
 684
 685 /*
 686  * Send init stream sequence to card
 687  * before sending IDLE command
 688  */
 689 static void send_init_stream(struct omap_hsmmc_host *host)
 690 {
 691         int reg = 0;
 692         unsigned long timeout;
 693
 694         if (host->protect_card)
 695                 return;
 696
 697         disable_irq(host->irq);
 698
 699         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 700         OMAP_HSMMC_WRITE(host->base, CON,
 701                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 702         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 703
 704         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 705         while ((reg != CC) && time_before(jiffies, timeout))
 706                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 707
 708         OMAP_HSMMC_WRITE(host->base, CON,
 709                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 710
 711         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 712         OMAP_HSMMC_READ(host->base, STAT);
 713
 714         enable_irq(host->irq);
 715 }
 716
 717 static inline
 718 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 719 {
 720         int r = 1;
 721
 722         if (mmc_slot(host).get_cover_state)
 723                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 724         return r;
 725 }
 726
 727 static ssize_t
 728 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 729                            char *buf)
 730 {
 731         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 732         struct omap_hsmmc_host *host = mmc_priv(mmc);
 733
 734         return sprintf(buf, "%s\n",
 735                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 736 }
 737
 738 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 739
 740 static ssize_t
 741 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 742                         char *buf)
 743 {
 744         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 745         struct omap_hsmmc_host *host = mmc_priv(mmc);
 746
 747         return sprintf(buf, "%s\n", mmc_slot(host).name);
 748 }
 749
 750 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 751
 752 /*
 753  * Configure the response type and send the cmd.
 754  */
 755 static void
 756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 757         struct mmc_data *data)
 758 {
 759         int cmdreg = 0, resptype = 0, cmdtype = 0;
 760
 761         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 762                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 763         host->cmd = cmd;
 764
 765         omap_hsmmc_enable_irq(host, cmd);
 766
 767         host->response_busy = 0;
 768         if (cmd->flags & MMC_RSP_PRESENT) {
 769                 if (cmd->flags & MMC_RSP_136)
 770                         resptype = 1;
 771                 else if (cmd->flags & MMC_RSP_BUSY) {
 772                         resptype = 3;
 773                         host->response_busy = 1;
 774                 } else
 775                         resptype = 2;
 776         }
 777
 778         /*
 779          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 780          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 781          * a val of 0x3, rest 0x0.
 782          */
 783         if (cmd == host->mrq->stop)
 784                 cmdtype = 0x3;
 785
 786         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 787
 788         if (data) {
 789                 cmdreg |= DP_SELECT | MSBS | BCE;
 790                 if (data->flags & MMC_DATA_READ)
 791                         cmdreg |= DDIR;
 792                 else
 793                         cmdreg &= ~(DDIR);
 794         }
 795
 796         if (host->use_dma)
 797                 cmdreg |= DMA_EN;
 798
 799         host->req_in_progress = 1;
 800
 801         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 802         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 803 }
 804
 805 static int
 806 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 807 {
 808         if (data->flags & MMC_DATA_WRITE)
 809                 return DMA_TO_DEVICE;
 810         else
 811                 return DMA_FROM_DEVICE;
 812 }
 813
 814 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 815         struct mmc_data *data)
 816 {
 817         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 818 }
 819
 820 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 821 {
 822         int dma_ch;
 823         unsigned long flags;
 824
 825         spin_lock_irqsave(&host->irq_lock, flags);
 826         host->req_in_progress = 0;
 827         dma_ch = host->dma_ch;
 828         spin_unlock_irqrestore(&host->irq_lock, flags);
 829
 830         omap_hsmmc_disable_irq(host);
 831         /* Do not complete the request if DMA is still in progress */
 832         if (mrq->data && host->use_dma && dma_ch != -1)
 833                 return;
 834         host->mrq = NULL;
 835         mmc_request_done(host->mmc, mrq);
 836 }
 837
 838 /*
 839  * Notify the transfer complete to MMC core
 840  */
 841 static void
 842 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 843 {
 844         if (!data) {
 845                 struct mmc_request *mrq = host->mrq;
 846
 847                 /* TC before CC from CMD6 - don't know why, but it happens */
 848                 if (host->cmd && host->cmd->opcode == 6 &&
 849                     host->response_busy) {
 850                         host->response_busy = 0;
 851                         return;
 852                 }
 853
 854                 omap_hsmmc_request_done(host, mrq);
 855                 return;
 856         }
 857
 858         host->data = NULL;
 859
 860         if (!data->error)
 861                 data->bytes_xfered += data->blocks * (data->blksz);
 862         else
 863                 data->bytes_xfered = 0;
 864
 865         if (!data->stop) {
 866                 omap_hsmmc_request_done(host, data->mrq);
 867                 return;
 868         }
 869         omap_hsmmc_start_command(host, data->stop, NULL);
 870 }
 871
 872 /*
 873  * Notify the core about command completion
 874  */
 875 static void
 876 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 877 {
 878         host->cmd = NULL;
 879
 880         if (cmd->flags & MMC_RSP_PRESENT) {
 881                 if (cmd->flags & MMC_RSP_136) {
 882                         /* response type 2 */
 883                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 884                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 885                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 886                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 887                 } else {
 888                         /* response types 1, 1b, 3, 4, 5, 6 */
 889                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 890                 }
 891         }
 892         if ((host->data == NULL && !host->response_busy) || cmd->error)
 893                 omap_hsmmc_request_done(host, cmd->mrq);
 894 }
 895
 896 /*
 897  * DMA clean up for command errors
 898  */
 899 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 900 {
 901         int dma_ch;
 902         unsigned long flags;
 903
 904         host->data->error = errno;
 905
 906         spin_lock_irqsave(&host->irq_lock, flags);
 907         dma_ch = host->dma_ch;
 908         host->dma_ch = -1;
 909         spin_unlock_irqrestore(&host->irq_lock, flags);
 910
 911         if (host->use_dma && dma_ch != -1) {
 912                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 913
 914                 dmaengine_terminate_all(chan);
 915                 dma_unmap_sg(chan->device->dev,
 916                         host->data->sg, host->data->sg_len,
 917                         omap_hsmmc_get_dma_dir(host, host->data));
 918
 919                 host->data->host_cookie = 0;
 920         }
 921         host->data = NULL;
 922 }
 923
 924 /*
 925  * Readable error output
 926  */
 927 #ifdef CONFIG_MMC_DEBUG
 928 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 929 {
 930         /* --- means reserved bit without definition at documentation */
 931         static const char *omap_hsmmc_status_bits[] = {
 932                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 933                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 934                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 935                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 936         };
 937         char res[256];
 938         char *buf = res;
 939         int len, i;
 940
 941         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 942         buf += len;
 943
 944         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 945                 if (status & (1 << i)) {
 946                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 947                         buf += len;
 948                 }
 949
 950         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 951 }
 952 #else
 953 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 954                                              u32 status)
 955 {
 956 }
 957 #endif  /* CONFIG_MMC_DEBUG */
 958
 959 /*
 960  * MMC controller internal state machines reset
 961  *
 962  * Used to reset command or data internal state machines, using respectively
 963  *  SRC or SRD bit of SYSCTL register
 964  * Can be called from interrupt context
 965  */
 966 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 967                                                    unsigned long bit)
 968 {
 969         unsigned long i = 0;
 970         unsigned long limit = (loops_per_jiffy *
 971                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 972
 973         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 974                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 975
 976         /*
 977          * OMAP4 ES2 and greater has an updated reset logic.
 978          * Monitor a 0->1 transition first
 979          */
 980         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 981                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 982                                         && (i++ < limit))
 983                         cpu_relax();
 984         }
 985         i = 0;
 986
 987         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 988                 (i++ < limit))
 989                 cpu_relax();
 990
 991         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 992                 dev_err(mmc_dev(host->mmc),
 993                         "Timeout waiting on controller reset in %s\n",
 994                         __func__);
 995 }
 996
 997 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
 998                                         int err, int end_cmd)
 999 {
1000         if (end_cmd) {
1001                 omap_hsmmc_reset_controller_fsm(host, SRC);
1002                 if (host->cmd)
1003                         host->cmd->error = err;
1004         }
1005
1006         if (host->data) {
1007                 omap_hsmmc_reset_controller_fsm(host, SRD);
1008                 omap_hsmmc_dma_cleanup(host, err);
1009         } else if (host->mrq && host->mrq->cmd)
1010                 host->mrq->cmd->error = err;
1011 }
1012
1013 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1014 {
1015         struct mmc_data *data;
1016         int end_cmd = 0, end_trans = 0;
1017
1018         data = host->data;
1019         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1020
1021         if (status & ERR) {
1022                 omap_hsmmc_dbg_report_irq(host, status);
1023
1024                 if (status & (CMD_TIMEOUT | CMD_CRC))
1025                         end_cmd = 1;
1026                 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
1027                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1028                 else if (status & (CMD_CRC | DATA_CRC))
1029                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1030
1031                 if (host->data || host->response_busy) {
1032                         end_trans = !end_cmd;
1033                         host->response_busy = 0;
1034                 }
1035         }
1036
1037         if (end_cmd || ((status & CC) && host->cmd))
1038                 omap_hsmmc_cmd_done(host, host->cmd);
1039         if ((end_trans || (status & TC)) && host->mrq)
1040                 omap_hsmmc_xfer_done(host, data);
1041 }
1042
1043 /*
1044  * MMC controller IRQ handler
1045  */
1046 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1047 {
1048         struct omap_hsmmc_host *host = dev_id;
1049         int status;
1050
1051         status = OMAP_HSMMC_READ(host->base, STAT);
1052         while (status & INT_EN_MASK && host->req_in_progress) {
1053                 omap_hsmmc_do_irq(host, status);
1054
1055                 /* Flush posted write */
1056                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1057                 status = OMAP_HSMMC_READ(host->base, STAT);
1058         }
1059
1060         return IRQ_HANDLED;
1061 }
1062
1063 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1064 {
1065         unsigned long i;
1066
1067         OMAP_HSMMC_WRITE(host->base, HCTL,
1068                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1069         for (i = 0; i < loops_per_jiffy; i++) {
1070                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1071                         break;
1072                 cpu_relax();
1073         }
1074 }
1075
1076 /*
1077  * Switch MMC interface voltage ... only relevant for MMC1.
1078  *
1079  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1080  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1081  * Some chips, like eMMC ones, use internal transceivers.
1082  */
1083 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1084 {
1085         u32 reg_val = 0;
1086         int ret;
1087
1088         /* Disable the clocks */
1089         pm_runtime_put_sync(host->dev);
1090         if (host->dbclk)
1091                 clk_disable_unprepare(host->dbclk);
1092
1093         /* Turn the power off */
1094         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1095
1096         /* Turn the power ON with given VDD 1.8 or 3.0v */
1097         if (!ret)
1098                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1099                                                vdd);
1100         pm_runtime_get_sync(host->dev);
1101         if (host->dbclk)
1102                 clk_prepare_enable(host->dbclk);
1103
1104         if (ret != 0)
1105                 goto err;
1106
1107         OMAP_HSMMC_WRITE(host->base, HCTL,
1108                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1109         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1110
1111         /*
1112          * If a MMC dual voltage card is detected, the set_ios fn calls
1113          * this fn with VDD bit set for 1.8V. Upon card removal from the
1114          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1115          *
1116          * Cope with a bit of slop in the range ... per data sheets:
1117          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1118          *    but recommended values are 1.71V to 1.89V
1119          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1120          *    but recommended values are 2.7V to 3.3V
1121          *
1122          * Board setup code shouldn't permit anything very out-of-range.
1123          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1124          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1125          */
1126         if ((1 << vdd) <= MMC_VDD_23_24)
1127                 reg_val |= SDVS18;
1128         else
1129                 reg_val |= SDVS30;
1130
1131         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1132         set_sd_bus_power(host);
1133
1134         return 0;
1135 err:
1136         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1137         return ret;
1138 }
1139
1140 /* Protect the card while the cover is open */
1141 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1142 {
1143         if (!mmc_slot(host).get_cover_state)
1144                 return;
1145
1146         host->reqs_blocked = 0;
1147         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1148                 if (host->protect_card) {
1149                         dev_info(host->dev, "%s: cover is closed, "
1150                                          "card is now accessible\n",
1151                                          mmc_hostname(host->mmc));
1152                         host->protect_card = 0;
1153                 }
1154         } else {
1155                 if (!host->protect_card) {
1156                         dev_info(host->dev, "%s: cover is open, "
1157                                          "card is now inaccessible\n",
1158                                          mmc_hostname(host->mmc));
1159                         host->protect_card = 1;
1160                 }
1161         }
1162 }
1163
1164 /*
1165  * irq handler to notify the core about card insertion/removal
1166  */
1167 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1168 {
1169         struct omap_hsmmc_host *host = dev_id;
1170         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1171         int carddetect;
1172
1173         if (host->suspended)
1174                 return IRQ_HANDLED;
1175
1176         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1177
1178         if (slot->card_detect)
1179                 carddetect = slot->card_detect(host->dev, host->slot_id);
1180         else {
1181                 omap_hsmmc_protect_card(host);
1182                 carddetect = -ENOSYS;
1183         }
1184
1185         if (carddetect)
1186                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1187         else
1188                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1189         return IRQ_HANDLED;
1190 }
1191
1192 static void omap_hsmmc_dma_callback(void *param)
1193 {
1194         struct omap_hsmmc_host *host = param;
1195         struct dma_chan *chan;
1196         struct mmc_data *data;
1197         int req_in_progress;
1198
1199         spin_lock_irq(&host->irq_lock);
1200         if (host->dma_ch < 0) {
1201                 spin_unlock_irq(&host->irq_lock);
1202                 return;
1203         }
1204
1205         data = host->mrq->data;
1206         chan = omap_hsmmc_get_dma_chan(host, data);
1207         if (!data->host_cookie)
1208                 dma_unmap_sg(chan->device->dev,
1209                              data->sg, data->sg_len,
1210                              omap_hsmmc_get_dma_dir(host, data));
1211
1212         req_in_progress = host->req_in_progress;
1213         host->dma_ch = -1;
1214         spin_unlock_irq(&host->irq_lock);
1215
1216         /* If DMA has finished after TC, complete the request */
1217         if (!req_in_progress) {
1218                 struct mmc_request *mrq = host->mrq;
1219
1220                 host->mrq = NULL;
1221                 mmc_request_done(host->mmc, mrq);
1222         }
1223 }
1224
1225 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1226                                        struct mmc_data *data,
1227                                        struct omap_hsmmc_next *next,
1228                                        struct dma_chan *chan)
1229 {
1230         int dma_len;
1231
1232         if (!next && data->host_cookie &&
1233             data->host_cookie != host->next_data.cookie) {
1234                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1235                        " host->next_data.cookie %d\n",
1236                        __func__, data->host_cookie, host->next_data.cookie);
1237                 data->host_cookie = 0;
1238         }
1239
1240         /* Check if next job is already prepared */
1241         if (next ||
1242             (!next && data->host_cookie != host->next_data.cookie)) {
1243                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1244                                      omap_hsmmc_get_dma_dir(host, data));
1245
1246         } else {
1247                 dma_len = host->next_data.dma_len;
1248                 host->next_data.dma_len = 0;
1249         }
1250
1251
1252         if (dma_len == 0)
1253                 return -EINVAL;
1254
1255         if (next) {
1256                 next->dma_len = dma_len;
1257                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1258         } else
1259                 host->dma_len = dma_len;
1260
1261         return 0;
1262 }
1263
1264 /*
1265  * Routine to configure and start DMA for the MMC card
1266  */
1267 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1268                                         struct mmc_request *req)
1269 {
1270         struct dma_slave_config cfg;
1271         struct dma_async_tx_descriptor *tx;
1272         int ret = 0, i;
1273         struct mmc_data *data = req->data;
1274         struct dma_chan *chan;
1275
1276         /* Sanity check: all the SG entries must be aligned by block size. */
1277         for (i = 0; i < data->sg_len; i++) {
1278                 struct scatterlist *sgl;
1279
1280                 sgl = data->sg + i;
1281                 if (sgl->length % data->blksz)
1282                         return -EINVAL;
1283         }
1284         if ((data->blksz % 4) != 0)
1285                 /* REVISIT: The MMC buffer increments only when MSB is written.
1286                  * Return error for blksz which is non multiple of four.
1287                  */
1288                 return -EINVAL;
1289
1290         BUG_ON(host->dma_ch != -1);
1291
1292         chan = omap_hsmmc_get_dma_chan(host, data);
1293
1294         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1295         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1296         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1297         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1298         cfg.src_maxburst = data->blksz / 4;
1299         cfg.dst_maxburst = data->blksz / 4;
1300
1301         ret = dmaengine_slave_config(chan, &cfg);
1302         if (ret)
1303                 return ret;
1304
1305         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1306         if (ret)
1307                 return ret;
1308
1309         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1310                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1311                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312         if (!tx) {
1313                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1314                 /* FIXME: cleanup */
1315                 return -1;
1316         }
1317
1318         tx->callback = omap_hsmmc_dma_callback;
1319         tx->callback_param = host;
1320
1321         /* Does not fail */
1322         dmaengine_submit(tx);
1323
1324         host->dma_ch = 1;
1325
1326         dma_async_issue_pending(chan);
1327
1328         return 0;
1329 }
1330
1331 static void set_data_timeout(struct omap_hsmmc_host *host,
1332                              unsigned int timeout_ns,
1333                              unsigned int timeout_clks)
1334 {
1335         unsigned int timeout, cycle_ns;
1336         uint32_t reg, clkd, dto = 0;
1337
1338         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1339         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1340         if (clkd == 0)
1341                 clkd = 1;
1342
1343         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1344         timeout = timeout_ns / cycle_ns;
1345         timeout += timeout_clks;
1346         if (timeout) {
1347                 while ((timeout & 0x80000000) == 0) {
1348                         dto += 1;
1349                         timeout <<= 1;
1350                 }
1351                 dto = 31 - dto;
1352                 timeout <<= 1;
1353                 if (timeout && dto)
1354                         dto += 1;
1355                 if (dto >= 13)
1356                         dto -= 13;
1357                 else
1358                         dto = 0;
1359                 if (dto > 14)
1360                         dto = 14;
1361         }
1362
1363         reg &= ~DTO_MASK;
1364         reg |= dto << DTO_SHIFT;
1365         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1366 }
1367
1368 /*
1369  * Configure block length for MMC/SD cards and initiate the transfer.
1370  */
1371 static int
1372 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1373 {
1374         int ret;
1375         host->data = req->data;
1376
1377         if (req->data == NULL) {
1378                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1379                 /*
1380                  * Set an arbitrary 100ms data timeout for commands with
1381                  * busy signal.
1382                  */
1383                 if (req->cmd->flags & MMC_RSP_BUSY)
1384                         set_data_timeout(host, 100000000U, 0);
1385                 return 0;
1386         }
1387
1388         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1389                                         | (req->data->blocks << 16));
1390         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1391
1392         if (host->use_dma) {
1393                 ret = omap_hsmmc_start_dma_transfer(host, req);
1394                 if (ret != 0) {
1395                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1396                         return ret;
1397                 }
1398         }
1399         return 0;
1400 }
1401
1402 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1403                                 int err)
1404 {
1405         struct omap_hsmmc_host *host = mmc_priv(mmc);
1406         struct mmc_data *data = mrq->data;
1407
1408         if (host->use_dma && data->host_cookie) {
1409                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1410
1411                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1412                              omap_hsmmc_get_dma_dir(host, data));
1413                 data->host_cookie = 0;
1414         }
1415 }
1416
1417 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1418                                bool is_first_req)
1419 {
1420         struct omap_hsmmc_host *host = mmc_priv(mmc);
1421
1422         if (mrq->data->host_cookie) {
1423                 mrq->data->host_cookie = 0;
1424                 return ;
1425         }
1426
1427         if (host->use_dma) {
1428                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1429
1430                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1431                                                 &host->next_data, c))
1432                         mrq->data->host_cookie = 0;
1433         }
1434 }
1435
1436 /*
1437  * Request function. for read/write operation
1438  */
1439 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1440 {
1441         struct omap_hsmmc_host *host = mmc_priv(mmc);
1442         int err;
1443
1444         BUG_ON(host->req_in_progress);
1445         BUG_ON(host->dma_ch != -1);
1446         if (host->protect_card) {
1447                 if (host->reqs_blocked < 3) {
1448                         /*
1449                          * Ensure the controller is left in a consistent
1450                          * state by resetting the command and data state
1451                          * machines.
1452                          */
1453                         omap_hsmmc_reset_controller_fsm(host, SRD);
1454                         omap_hsmmc_reset_controller_fsm(host, SRC);
1455                         host->reqs_blocked += 1;
1456                 }
1457                 req->cmd->error = -EBADF;
1458                 if (req->data)
1459                         req->data->error = -EBADF;
1460                 req->cmd->retries = 0;
1461                 mmc_request_done(mmc, req);
1462                 return;
1463         } else if (host->reqs_blocked)
1464                 host->reqs_blocked = 0;
1465         WARN_ON(host->mrq != NULL);
1466         host->mrq = req;
1467         err = omap_hsmmc_prepare_data(host, req);
1468         if (err) {
1469                 req->cmd->error = err;
1470                 if (req->data)
1471                         req->data->error = err;
1472                 host->mrq = NULL;
1473                 mmc_request_done(mmc, req);
1474                 return;
1475         }
1476
1477         omap_hsmmc_start_command(host, req->cmd, req->data);
1478 }
1479
1480 /* Routine to configure clock values. Exposed API to core */
1481 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1482 {
1483         struct omap_hsmmc_host *host = mmc_priv(mmc);
1484         int do_send_init_stream = 0;
1485
1486         pm_runtime_get_sync(host->dev);
1487
1488         if (ios->power_mode != host->power_mode) {
1489                 switch (ios->power_mode) {
1490                 case MMC_POWER_OFF:
1491                         mmc_slot(host).set_power(host->dev, host->slot_id,
1492                                                  0, 0);
1493                         break;
1494                 case MMC_POWER_UP:
1495                         mmc_slot(host).set_power(host->dev, host->slot_id,
1496                                                  1, ios->vdd);
1497                         break;
1498                 case MMC_POWER_ON:
1499                         do_send_init_stream = 1;
1500                         break;
1501                 }
1502                 host->power_mode = ios->power_mode;
1503         }
1504
1505         /* FIXME: set registers based only on changes to ios */
1506
1507         omap_hsmmc_set_bus_width(host);
1508
1509         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1510                 /* Only MMC1 can interface at 3V without some flavor
1511                  * of external transceiver; but they all handle 1.8V.
1512                  */
1513                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1514                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1515                         /*
1516                          * With pbias cell programming missing, this
1517                          * can't be allowed when booting with device
1518                          * tree.
1519                          */
1520                         !host->dev->of_node) {
1521                                 /*
1522                                  * The mmc_select_voltage fn of the core does
1523                                  * not seem to set the power_mode to
1524                                  * MMC_POWER_UP upon recalculating the voltage.
1525                                  * vdd 1.8v.
1526                                  */
1527                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1528                                 dev_dbg(mmc_dev(host->mmc),
1529                                                 "Switch operation failed\n");
1530                 }
1531         }
1532
1533         omap_hsmmc_set_clock(host);
1534
1535         if (do_send_init_stream)
1536                 send_init_stream(host);
1537
1538         omap_hsmmc_set_bus_mode(host);
1539
1540         pm_runtime_put_autosuspend(host->dev);
1541 }
1542
1543 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1544 {
1545         struct omap_hsmmc_host *host = mmc_priv(mmc);
1546
1547         if (!mmc_slot(host).card_detect)
1548                 return -ENOSYS;
1549         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1550 }
1551
1552 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1553 {
1554         struct omap_hsmmc_host *host = mmc_priv(mmc);
1555
1556         if (!mmc_slot(host).get_ro)
1557                 return -ENOSYS;
1558         return mmc_slot(host).get_ro(host->dev, 0);
1559 }
1560
1561 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1562 {
1563         struct omap_hsmmc_host *host = mmc_priv(mmc);
1564
1565         if (mmc_slot(host).init_card)
1566                 mmc_slot(host).init_card(card);
1567 }
1568
1569 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1570 {
1571         u32 hctl, capa, value;
1572
1573         /* Only MMC1 supports 3.0V */
1574         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1575                 hctl = SDVS30;
1576                 capa = VS30 | VS18;
1577         } else {
1578                 hctl = SDVS18;
1579                 capa = VS18;
1580         }
1581
1582         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1583         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1584
1585         value = OMAP_HSMMC_READ(host->base, CAPA);
1586         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1587
1588         /* Set SD bus power bit */
1589         set_sd_bus_power(host);
1590 }
1591
1592 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1593 {
1594         struct omap_hsmmc_host *host = mmc_priv(mmc);
1595
1596         pm_runtime_get_sync(host->dev);
1597
1598         return 0;
1599 }
1600
1601 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1602 {
1603         struct omap_hsmmc_host *host = mmc_priv(mmc);
1604
1605         pm_runtime_mark_last_busy(host->dev);
1606         pm_runtime_put_autosuspend(host->dev);
1607
1608         return 0;
1609 }
1610
1611 static const struct mmc_host_ops omap_hsmmc_ops = {
1612         .enable = omap_hsmmc_enable_fclk,
1613         .disable = omap_hsmmc_disable_fclk,
1614         .post_req = omap_hsmmc_post_req,
1615         .pre_req = omap_hsmmc_pre_req,
1616         .request = omap_hsmmc_request,
1617         .set_ios = omap_hsmmc_set_ios,
1618         .get_cd = omap_hsmmc_get_cd,
1619         .get_ro = omap_hsmmc_get_ro,
1620         .init_card = omap_hsmmc_init_card,
1621         /* NYET -- enable_sdio_irq */
1622 };
1623
1624 #ifdef CONFIG_DEBUG_FS
1625
1626 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1627 {
1628         struct mmc_host *mmc = s->private;
1629         struct omap_hsmmc_host *host = mmc_priv(mmc);
1630         int context_loss = 0;
1631
1632         if (host->pdata->get_context_loss_count)
1633                 context_loss = host->pdata->get_context_loss_count(host->dev);
1634
1635         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1636                         mmc->index, host->context_loss, context_loss);
1637
1638         if (host->suspended) {
1639                 seq_printf(s, "host suspended, can't read registers\n");
1640                 return 0;
1641         }
1642
1643         pm_runtime_get_sync(host->dev);
1644
1645         seq_printf(s, "CON:\t\t0x%08x\n",
1646                         OMAP_HSMMC_READ(host->base, CON));
1647         seq_printf(s, "HCTL:\t\t0x%08x\n",
1648                         OMAP_HSMMC_READ(host->base, HCTL));
1649         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1650                         OMAP_HSMMC_READ(host->base, SYSCTL));
1651         seq_printf(s, "IE:\t\t0x%08x\n",
1652                         OMAP_HSMMC_READ(host->base, IE));
1653         seq_printf(s, "ISE:\t\t0x%08x\n",
1654                         OMAP_HSMMC_READ(host->base, ISE));
1655         seq_printf(s, "CAPA:\t\t0x%08x\n",
1656                         OMAP_HSMMC_READ(host->base, CAPA));
1657
1658         pm_runtime_mark_last_busy(host->dev);
1659         pm_runtime_put_autosuspend(host->dev);
1660
1661         return 0;
1662 }
1663
1664 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1665 {
1666         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1667 }
1668
1669 static const struct file_operations mmc_regs_fops = {
1670         .open           = omap_hsmmc_regs_open,
1671         .read           = seq_read,
1672         .llseek         = seq_lseek,
1673         .release        = single_release,
1674 };
1675
1676 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1677 {
1678         if (mmc->debugfs_root)
1679                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1680                         mmc, &mmc_regs_fops);
1681 }
1682
1683 #else
1684
1685 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1686 {
1687 }
1688
1689 #endif
1690
1691 #ifdef CONFIG_OF
1692 static u16 omap4_reg_offset = 0x100;
1693
1694 static const struct of_device_id omap_mmc_of_match[] = {
1695         {
1696                 .compatible = "ti,omap2-hsmmc",
1697         },
1698         {
1699                 .compatible = "ti,omap3-hsmmc",
1700         },
1701         {
1702                 .compatible = "ti,omap4-hsmmc",
1703                 .data = &omap4_reg_offset,
1704         },
1705         {},
1706 };
1707 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1708
1709 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1710 {
1711         struct omap_mmc_platform_data *pdata;
1712         struct device_node *np = dev->of_node;
1713         u32 bus_width, max_freq;
1714
1715         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1716         if (!pdata)
1717                 return NULL; /* out of memory */
1718
1719         if (of_find_property(np, "ti,dual-volt", NULL))
1720                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1721
1722         /* This driver only supports 1 slot */
1723         pdata->nr_slots = 1;
1724         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1725         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1726
1727         if (of_find_property(np, "ti,non-removable", NULL)) {
1728                 pdata->slots[0].nonremovable = true;
1729                 pdata->slots[0].no_regulator_off_init = true;
1730         }
1731         of_property_read_u32(np, "bus-width", &bus_width);
1732         if (bus_width == 4)
1733                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1734         else if (bus_width == 8)
1735                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1736
1737         if (of_find_property(np, "ti,needs-special-reset", NULL))
1738                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1739
1740         if (!of_property_read_u32(np, "max-frequency", &max_freq))
1741                 pdata->max_freq = max_freq;
1742
1743         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1744                 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1745
1746         return pdata;
1747 }
1748 #else
1749 static inline struct omap_mmc_platform_data
1750                         *of_get_hsmmc_pdata(struct device *dev)
1751 {
1752         return NULL;
1753 }
1754 #endif
1755
1756 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1757 {
1758         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1759         struct mmc_host *mmc;
1760         struct omap_hsmmc_host *host = NULL;
1761         struct resource *res;
1762         int ret, irq;
1763         const struct of_device_id *match;
1764         dma_cap_mask_t mask;
1765         unsigned tx_req, rx_req;
1766         struct pinctrl *pinctrl;
1767
1768         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1769         if (match) {
1770                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1771                 if (match->data) {
1772                         const u16 *offsetp = match->data;
1773                         pdata->reg_offset = *offsetp;
1774                 }
1775         }
1776
1777         if (pdata == NULL) {
1778                 dev_err(&pdev->dev, "Platform Data is missing\n");
1779                 return -ENXIO;
1780         }
1781
1782         if (pdata->nr_slots == 0) {
1783                 dev_err(&pdev->dev, "No Slots\n");
1784                 return -ENXIO;
1785         }
1786
1787         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1788         irq = platform_get_irq(pdev, 0);
1789         if (res == NULL || irq < 0)
1790                 return -ENXIO;
1791
1792         res = request_mem_region(res->start, resource_size(res), pdev->name);
1793         if (res == NULL)
1794                 return -EBUSY;
1795
1796         ret = omap_hsmmc_gpio_init(pdata);
1797         if (ret)
1798                 goto err;
1799
1800         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1801         if (!mmc) {
1802                 ret = -ENOMEM;
1803                 goto err_alloc;
1804         }
1805
1806         host            = mmc_priv(mmc);
1807         host->mmc       = mmc;
1808         host->pdata     = pdata;
1809         host->dev       = &pdev->dev;
1810         host->use_dma   = 1;
1811         host->dma_ch    = -1;
1812         host->irq       = irq;
1813         host->slot_id   = 0;
1814         host->mapbase   = res->start + pdata->reg_offset;
1815         host->base      = ioremap(host->mapbase, SZ_4K);
1816         host->power_mode = MMC_POWER_OFF;
1817         host->next_data.cookie = 1;
1818
1819         platform_set_drvdata(pdev, host);
1820
1821         mmc->ops        = &omap_hsmmc_ops;
1822
1823         /*
1824          * If regulator_disable can only put vcc_aux to sleep then there is
1825          * no off state.
1826          */
1827         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1828                 mmc_slot(host).no_off = 1;
1829
1830         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1831
1832         if (pdata->max_freq > 0)
1833                 mmc->f_max = pdata->max_freq;
1834         else
1835                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1836
1837         spin_lock_init(&host->irq_lock);
1838
1839         host->fclk = clk_get(&pdev->dev, "fck");
1840         if (IS_ERR(host->fclk)) {
1841                 ret = PTR_ERR(host->fclk);
1842                 host->fclk = NULL;
1843                 goto err1;
1844         }
1845
1846         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1847                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1848                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1849         }
1850
1851         pm_runtime_enable(host->dev);
1852         pm_runtime_get_sync(host->dev);
1853         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1854         pm_runtime_use_autosuspend(host->dev);
1855
1856         omap_hsmmc_context_save(host);
1857
1858         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1859         /*
1860          * MMC can still work without debounce clock.
1861          */
1862         if (IS_ERR(host->dbclk)) {
1863                 host->dbclk = NULL;
1864         } else if (clk_prepare_enable(host->dbclk) != 0) {
1865                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1866                 clk_put(host->dbclk);
1867                 host->dbclk = NULL;
1868         }
1869
1870         /* Since we do only SG emulation, we can have as many segs
1871          * as we want. */
1872         mmc->max_segs = 1024;
1873
1874         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1875         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1876         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1877         mmc->max_seg_size = mmc->max_req_size;
1878
1879         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1880                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1881
1882         mmc->caps |= mmc_slot(host).caps;
1883         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1884                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1885
1886         if (mmc_slot(host).nonremovable)
1887                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1888
1889         mmc->pm_caps = mmc_slot(host).pm_caps;
1890
1891         omap_hsmmc_conf_bus_power(host);
1892
1893         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1894         if (!res) {
1895                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1896                 ret = -ENXIO;
1897                 goto err_irq;
1898         }
1899         tx_req = res->start;
1900
1901         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1902         if (!res) {
1903                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1904                 ret = -ENXIO;
1905                 goto err_irq;
1906         }
1907         rx_req = res->start;
1908
1909         dma_cap_zero(mask);
1910         dma_cap_set(DMA_SLAVE, mask);
1911
1912         host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1913         if (!host->rx_chan) {
1914                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1915                 ret = -ENXIO;
1916                 goto err_irq;
1917         }
1918
1919         host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1920         if (!host->tx_chan) {
1921                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1922                 ret = -ENXIO;
1923                 goto err_irq;
1924         }
1925
1926         /* Request IRQ for MMC operations */
1927         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1928                         mmc_hostname(mmc), host);
1929         if (ret) {
1930                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1931                 goto err_irq;
1932         }
1933
1934         if (pdata->init != NULL) {
1935                 if (pdata->init(&pdev->dev) != 0) {
1936                         dev_dbg(mmc_dev(host->mmc),
1937                                 "Unable to configure MMC IRQs\n");
1938                         goto err_irq_cd_init;
1939                 }
1940         }
1941
1942         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1943                 ret = omap_hsmmc_reg_get(host);
1944                 if (ret)
1945                         goto err_reg;
1946                 host->use_reg = 1;
1947         }
1948
1949         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1950
1951         /* Request IRQ for card detect */
1952         if ((mmc_slot(host).card_detect_irq)) {
1953                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1954                                            NULL,
1955                                            omap_hsmmc_detect,
1956                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1957                                            mmc_hostname(mmc), host);
1958                 if (ret) {
1959                         dev_dbg(mmc_dev(host->mmc),
1960                                 "Unable to grab MMC CD IRQ\n");
1961                         goto err_irq_cd;
1962                 }
1963                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1964                 pdata->resume = omap_hsmmc_resume_cdirq;
1965         }
1966
1967         omap_hsmmc_disable_irq(host);
1968
1969         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1970         if (IS_ERR(pinctrl))
1971                 dev_warn(&pdev->dev,
1972                         "pins are not configured from the driver\n");
1973
1974         omap_hsmmc_protect_card(host);
1975
1976         mmc_add_host(mmc);
1977
1978         if (mmc_slot(host).name != NULL) {
1979                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1980                 if (ret < 0)
1981                         goto err_slot_name;
1982         }
1983         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1984                 ret = device_create_file(&mmc->class_dev,
1985                                         &dev_attr_cover_switch);
1986                 if (ret < 0)
1987                         goto err_slot_name;
1988         }
1989
1990         omap_hsmmc_debugfs(mmc);
1991         pm_runtime_mark_last_busy(host->dev);
1992         pm_runtime_put_autosuspend(host->dev);
1993
1994         return 0;
1995
1996 err_slot_name:
1997         mmc_remove_host(mmc);
1998         free_irq(mmc_slot(host).card_detect_irq, host);
1999 err_irq_cd:
2000         if (host->use_reg)
2001                 omap_hsmmc_reg_put(host);
2002 err_reg:
2003         if (host->pdata->cleanup)
2004                 host->pdata->cleanup(&pdev->dev);
2005 err_irq_cd_init:
2006         free_irq(host->irq, host);
2007 err_irq:
2008         if (host->tx_chan)
2009                 dma_release_channel(host->tx_chan);
2010         if (host->rx_chan)
2011                 dma_release_channel(host->rx_chan);
2012         pm_runtime_put_sync(host->dev);
2013         pm_runtime_disable(host->dev);
2014         clk_put(host->fclk);
2015         if (host->dbclk) {
2016                 clk_disable_unprepare(host->dbclk);
2017                 clk_put(host->dbclk);
2018         }
2019 err1:
2020         iounmap(host->base);
2021         platform_set_drvdata(pdev, NULL);
2022         mmc_free_host(mmc);
2023 err_alloc:
2024         omap_hsmmc_gpio_free(pdata);
2025 err:
2026         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2027         if (res)
2028                 release_mem_region(res->start, resource_size(res));
2029         return ret;
2030 }
2031
2032 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2033 {
2034         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2035         struct resource *res;
2036
2037         pm_runtime_get_sync(host->dev);
2038         mmc_remove_host(host->mmc);
2039         if (host->use_reg)
2040                 omap_hsmmc_reg_put(host);
2041         if (host->pdata->cleanup)
2042                 host->pdata->cleanup(&pdev->dev);
2043         free_irq(host->irq, host);
2044         if (mmc_slot(host).card_detect_irq)
2045                 free_irq(mmc_slot(host).card_detect_irq, host);
2046
2047         if (host->tx_chan)
2048                 dma_release_channel(host->tx_chan);
2049         if (host->rx_chan)
2050                 dma_release_channel(host->rx_chan);
2051
2052         pm_runtime_put_sync(host->dev);
2053         pm_runtime_disable(host->dev);
2054         clk_put(host->fclk);
2055         if (host->dbclk) {
2056                 clk_disable_unprepare(host->dbclk);
2057                 clk_put(host->dbclk);
2058         }
2059
2060         omap_hsmmc_gpio_free(host->pdata);
2061         iounmap(host->base);
2062         mmc_free_host(host->mmc);
2063
2064         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2065         if (res)
2066                 release_mem_region(res->start, resource_size(res));
2067         platform_set_drvdata(pdev, NULL);
2068
2069         return 0;
2070 }
2071
2072 #ifdef CONFIG_PM
2073 static int omap_hsmmc_prepare(struct device *dev)
2074 {
2075         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2076
2077         if (host->pdata->suspend)
2078                 return host->pdata->suspend(dev, host->slot_id);
2079
2080         return 0;
2081 }
2082
2083 static void omap_hsmmc_complete(struct device *dev)
2084 {
2085         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2086
2087         if (host->pdata->resume)
2088                 host->pdata->resume(dev, host->slot_id);
2089
2090 }
2091
2092 static int omap_hsmmc_suspend(struct device *dev)
2093 {
2094         int ret = 0;
2095         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2096
2097         if (!host)
2098                 return 0;
2099
2100         if (host && host->suspended)
2101                 return 0;
2102
2103         pm_runtime_get_sync(host->dev);
2104         host->suspended = 1;
2105         ret = mmc_suspend_host(host->mmc);
2106
2107         if (ret) {
2108                 host->suspended = 0;
2109                 goto err;
2110         }
2111
2112         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2113                 omap_hsmmc_disable_irq(host);
2114                 OMAP_HSMMC_WRITE(host->base, HCTL,
2115                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2116         }
2117
2118         if (host->dbclk)
2119                 clk_disable_unprepare(host->dbclk);
2120 err:
2121         pm_runtime_put_sync(host->dev);
2122         return ret;
2123 }
2124
2125 /* Routine to resume the MMC device */
2126 static int omap_hsmmc_resume(struct device *dev)
2127 {
2128         int ret = 0;
2129         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2130
2131         if (!host)
2132                 return 0;
2133
2134         if (host && !host->suspended)
2135                 return 0;
2136
2137         pm_runtime_get_sync(host->dev);
2138
2139         if (host->dbclk)
2140                 clk_prepare_enable(host->dbclk);
2141
2142         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2143                 omap_hsmmc_conf_bus_power(host);
2144
2145         omap_hsmmc_protect_card(host);
2146
2147         /* Notify the core to resume the host */
2148         ret = mmc_resume_host(host->mmc);
2149         if (ret == 0)
2150                 host->suspended = 0;
2151
2152         pm_runtime_mark_last_busy(host->dev);
2153         pm_runtime_put_autosuspend(host->dev);
2154
2155         return ret;
2156
2157 }
2158
2159 #else
2160 #define omap_hsmmc_prepare      NULL
2161 #define omap_hsmmc_complete     NULL
2162 #define omap_hsmmc_suspend      NULL
2163 #define omap_hsmmc_resume       NULL
2164 #endif
2165
2166 static int omap_hsmmc_runtime_suspend(struct device *dev)
2167 {
2168         struct omap_hsmmc_host *host;
2169
2170         host = platform_get_drvdata(to_platform_device(dev));
2171         omap_hsmmc_context_save(host);
2172         dev_dbg(dev, "disabled\n");
2173
2174         return 0;
2175 }
2176
2177 static int omap_hsmmc_runtime_resume(struct device *dev)
2178 {
2179         struct omap_hsmmc_host *host;
2180
2181         host = platform_get_drvdata(to_platform_device(dev));
2182         omap_hsmmc_context_restore(host);
2183         dev_dbg(dev, "enabled\n");
2184
2185         return 0;
2186 }
2187
2188 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2189         .suspend        = omap_hsmmc_suspend,
2190         .resume         = omap_hsmmc_resume,
2191         .prepare        = omap_hsmmc_prepare,
2192         .complete       = omap_hsmmc_complete,
2193         .runtime_suspend = omap_hsmmc_runtime_suspend,
2194         .runtime_resume = omap_hsmmc_runtime_resume,
2195 };
2196
2197 static struct platform_driver omap_hsmmc_driver = {
2198         .probe          = omap_hsmmc_probe,
2199         .remove         = __devexit_p(omap_hsmmc_remove),
2200         .driver         = {
2201                 .name = DRIVER_NAME,
2202                 .owner = THIS_MODULE,
2203                 .pm = &omap_hsmmc_dev_pm_ops,
2204                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2205         },
2206 };
2207
2208 module_platform_driver(omap_hsmmc_driver);
2209 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2210 MODULE_LICENSE("GPL");
2211 MODULE_ALIAS("platform:" DRIVER_NAME);
2212 MODULE_AUTHOR("Texas Instruments Inc");