2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
39 #include <linux/mmc/slot-gpio.h>
41 #include <linux/irq.h>
42 #include <linux/gpio.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/pinctrl/consumer.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/platform_data/hsmmc-omap.h>
48 /* OMAP HSMMC Host Controller Registers */
49 #define OMAP_HSMMC_SYSSTATUS 0x0014
50 #define OMAP_HSMMC_CON 0x002C
51 #define OMAP_HSMMC_SDMASA 0x0100
52 #define OMAP_HSMMC_BLK 0x0104
53 #define OMAP_HSMMC_ARG 0x0108
54 #define OMAP_HSMMC_CMD 0x010C
55 #define OMAP_HSMMC_RSP10 0x0110
56 #define OMAP_HSMMC_RSP32 0x0114
57 #define OMAP_HSMMC_RSP54 0x0118
58 #define OMAP_HSMMC_RSP76 0x011C
59 #define OMAP_HSMMC_DATA 0x0120
60 #define OMAP_HSMMC_PSTATE 0x0124
61 #define OMAP_HSMMC_HCTL 0x0128
62 #define OMAP_HSMMC_SYSCTL 0x012C
63 #define OMAP_HSMMC_STAT 0x0130
64 #define OMAP_HSMMC_IE 0x0134
65 #define OMAP_HSMMC_ISE 0x0138
66 #define OMAP_HSMMC_AC12 0x013C
67 #define OMAP_HSMMC_CAPA 0x0140
69 #define VS18 (1 << 26)
70 #define VS30 (1 << 25)
72 #define SDVS18 (0x5 << 9)
73 #define SDVS30 (0x6 << 9)
74 #define SDVS33 (0x7 << 9)
75 #define SDVS_MASK 0x00000E00
76 #define SDVSCLR 0xFFFFF1FF
77 #define SDVSDET 0x00000400
84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
85 #define CLKD_MASK 0x0000FFC0
87 #define DTO_MASK 0x000F0000
89 #define INIT_STREAM (1 << 1)
90 #define ACEN_ACMD23 (2 << 2)
91 #define DP_SELECT (1 << 21)
96 #define FOUR_BIT (1 << 1)
100 #define CLKEXTFREE (1 << 16)
101 #define CTPL (1 << 11)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
112 #define DLEV_DAT(x) (1 << (20 + (x)))
114 /* Interrupt masks for IE and ISE register */
115 #define CC_EN (1 << 0)
116 #define TC_EN (1 << 1)
117 #define BWR_EN (1 << 4)
118 #define BRR_EN (1 << 5)
119 #define CIRQ_EN (1 << 8)
120 #define ERR_EN (1 << 15)
121 #define CTO_EN (1 << 16)
122 #define CCRC_EN (1 << 17)
123 #define CEB_EN (1 << 18)
124 #define CIE_EN (1 << 19)
125 #define DTO_EN (1 << 20)
126 #define DCRC_EN (1 << 21)
127 #define DEB_EN (1 << 22)
128 #define ACE_EN (1 << 24)
129 #define CERR_EN (1 << 28)
130 #define BADA_EN (1 << 29)
132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
137 #define ACIE (1 << 4)
138 #define ACEB (1 << 3)
139 #define ACCE (1 << 2)
140 #define ACTO (1 << 1)
141 #define ACNE (1 << 0)
143 #define MMC_AUTOSUSPEND_DELAY 100
144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
146 #define OMAP_MMC_MIN_CLOCK 400000
147 #define OMAP_MMC_MAX_CLOCK 52000000
148 #define DRIVER_NAME "omap_hsmmc"
150 #define VDD_1V8 1800000 /* 180000 uV */
151 #define VDD_3V0 3000000 /* 300000 uV */
152 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
155 * One controller can have multiple slots, like on some omap boards using
156 * omap.c controller driver. Luckily this is not currently done on any known
157 * omap_hsmmc.c device.
159 #define mmc_pdata(host) host->pdata
162 * MMC Host controller read/write API's
164 #define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
167 #define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170 struct omap_hsmmc_next {
171 unsigned int dma_len;
175 struct omap_hsmmc_host {
177 struct mmc_host *mmc;
178 struct mmc_request *mrq;
179 struct mmc_command *cmd;
180 struct mmc_data *data;
184 * vcc == configured supply
185 * vcc_aux == optional
186 * - MMC1, supply for DAT4..DAT7
187 * - MMC2/MMC2, external level shifter voltage supply, for
188 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
190 struct regulator *vcc;
191 struct regulator *vcc_aux;
192 struct regulator *pbias;
195 resource_size_t mapbase;
196 spinlock_t irq_lock; /* Prevent races with irq handler */
197 unsigned int dma_len;
198 unsigned int dma_sg_idx;
199 unsigned char bus_mode;
200 unsigned char power_mode;
209 struct dma_chan *tx_chan;
210 struct dma_chan *rx_chan;
217 unsigned long clk_rate;
219 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
220 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
221 #define HSMMC_WAKE_IRQ_ENABLED (1 << 2)
222 struct omap_hsmmc_next next_data;
223 struct omap_hsmmc_platform_data *pdata;
225 /* return MMC cover switch state, can be NULL if not supported.
227 * possible return values:
231 int (*get_cover_state)(struct device *dev);
233 int (*card_detect)(struct device *dev);
236 struct omap_mmc_of_data {
241 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
243 static int omap_hsmmc_card_detect(struct device *dev)
245 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
247 return mmc_gpio_get_cd(host->mmc);
250 static int omap_hsmmc_get_cover_state(struct device *dev)
252 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
254 return mmc_gpio_get_cd(host->mmc);
257 #ifdef CONFIG_REGULATOR
259 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
261 struct omap_hsmmc_host *host =
262 platform_get_drvdata(to_platform_device(dev));
266 * If we don't see a Vcc regulator, assume it's a fixed
267 * voltage always-on regulator.
272 if (mmc_pdata(host)->before_set_reg)
273 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
276 if (host->pbias_enabled == 1) {
277 ret = regulator_disable(host->pbias);
279 host->pbias_enabled = 0;
281 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
285 * Assume Vcc regulator is used only to power the card ... OMAP
286 * VDDS is used to power the pins, optionally with a transceiver to
287 * support cards using voltages other than VDDS (1.8V nominal). When a
288 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 * In some cases this regulator won't support enable/disable;
291 * e.g. it's a fixed rail for a WLAN chip.
293 * In other cases vcc_aux switches interface power. Example, for
294 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
295 * chips/cards need an interface voltage rail too.
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0 && host->vcc)
304 ret = mmc_regulator_set_ocr(host->mmc,
308 /* Shut down the rail */
310 ret = regulator_disable(host->vcc_aux);
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
319 if (vdd <= VDD_165_195)
320 ret = regulator_set_voltage(host->pbias, VDD_1V8,
323 ret = regulator_set_voltage(host->pbias, VDD_3V0,
326 goto error_set_power;
328 if (host->pbias_enabled == 0) {
329 ret = regulator_enable(host->pbias);
331 host->pbias_enabled = 1;
335 if (mmc_pdata(host)->after_set_reg)
336 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
342 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
344 struct regulator *reg;
347 reg = devm_regulator_get(host->dev, "vmmc");
349 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
354 ocr_value = mmc_regulator_get_ocrmask(reg);
355 if (!mmc_pdata(host)->ocr_mask) {
356 mmc_pdata(host)->ocr_mask = ocr_value;
358 if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
359 dev_err(host->dev, "ocrmask %x is not supported\n",
360 mmc_pdata(host)->ocr_mask);
361 mmc_pdata(host)->ocr_mask = 0;
366 mmc_pdata(host)->set_power = omap_hsmmc_set_power;
368 /* Allow an aux regulator */
369 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
370 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
372 reg = devm_regulator_get_optional(host->dev, "pbias");
373 host->pbias = IS_ERR(reg) ? NULL : reg;
375 /* For eMMC do not power off when not in sleep state */
376 if (mmc_pdata(host)->no_regulator_off_init)
379 * To disable boot_on regulator, enable regulator
380 * to increase usecount and then disable it.
382 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
383 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
384 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
386 mmc_pdata(host)->set_power(host->dev, 1, vdd);
387 mmc_pdata(host)->set_power(host->dev, 0, 0);
393 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
395 mmc_pdata(host)->set_power = NULL;
398 static inline int omap_hsmmc_have_reg(void)
405 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
410 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
414 static inline int omap_hsmmc_have_reg(void)
421 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
423 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
424 struct omap_hsmmc_host *host,
425 struct omap_hsmmc_platform_data *pdata)
429 if (gpio_is_valid(pdata->gpio_cod)) {
430 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
434 host->get_cover_state = omap_hsmmc_get_cover_state;
435 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
436 } else if (gpio_is_valid(pdata->gpio_cd)) {
437 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
441 host->card_detect = omap_hsmmc_card_detect;
444 if (gpio_is_valid(pdata->gpio_wp)) {
445 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
454 * Start clock to the card
456 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
458 OMAP_HSMMC_WRITE(host->base, SYSCTL,
459 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
463 * Stop clock to the card
465 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
467 OMAP_HSMMC_WRITE(host->base, SYSCTL,
468 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
469 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
470 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
473 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
474 struct mmc_command *cmd)
476 u32 irq_mask = INT_EN_MASK;
480 irq_mask &= ~(BRR_EN | BWR_EN);
482 /* Disable timeout for erases */
483 if (cmd->opcode == MMC_ERASE)
486 spin_lock_irqsave(&host->irq_lock, flags);
487 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
488 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
490 /* latch pending CIRQ, but don't signal MMC core */
491 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
493 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
494 spin_unlock_irqrestore(&host->irq_lock, flags);
497 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
502 spin_lock_irqsave(&host->irq_lock, flags);
503 /* no transfer running but need to keep cirq if enabled */
504 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
506 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
507 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
508 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
509 spin_unlock_irqrestore(&host->irq_lock, flags);
512 /* Calculate divisor for the given clock frequency */
513 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
518 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
526 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
528 struct mmc_ios *ios = &host->mmc->ios;
529 unsigned long regval;
530 unsigned long timeout;
531 unsigned long clkdiv;
533 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
535 omap_hsmmc_stop_clock(host);
537 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
538 regval = regval & ~(CLKD_MASK | DTO_MASK);
539 clkdiv = calc_divisor(host, ios);
540 regval = regval | (clkdiv << 6) | (DTO << 16);
541 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
542 OMAP_HSMMC_WRITE(host->base, SYSCTL,
543 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
545 /* Wait till the ICS bit is set */
546 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
547 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
548 && time_before(jiffies, timeout))
552 * Enable High-Speed Support
554 * - Controller should support High-Speed-Enable Bit
555 * - Controller should not be using DDR Mode
556 * - Controller should advertise that it supports High Speed
557 * in capabilities register
558 * - MMC/SD clock coming out of controller > 25MHz
560 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
561 (ios->timing != MMC_TIMING_MMC_DDR52) &&
562 (ios->timing != MMC_TIMING_UHS_DDR50) &&
563 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
564 regval = OMAP_HSMMC_READ(host->base, HCTL);
565 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
570 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
573 omap_hsmmc_start_clock(host);
576 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
578 struct mmc_ios *ios = &host->mmc->ios;
581 con = OMAP_HSMMC_READ(host->base, CON);
582 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
583 ios->timing == MMC_TIMING_UHS_DDR50)
584 con |= DDR; /* configure in DDR mode */
587 switch (ios->bus_width) {
588 case MMC_BUS_WIDTH_8:
589 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
591 case MMC_BUS_WIDTH_4:
592 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
593 OMAP_HSMMC_WRITE(host->base, HCTL,
594 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
596 case MMC_BUS_WIDTH_1:
597 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
598 OMAP_HSMMC_WRITE(host->base, HCTL,
599 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
604 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
606 struct mmc_ios *ios = &host->mmc->ios;
609 con = OMAP_HSMMC_READ(host->base, CON);
610 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
611 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
613 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
619 * Restore the MMC host context, if it was lost as result of a
620 * power state change.
622 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
624 struct mmc_ios *ios = &host->mmc->ios;
626 unsigned long timeout;
628 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
629 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
630 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
631 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
634 host->context_loss++;
636 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
637 if (host->power_mode != MMC_POWER_OFF &&
638 (1 << ios->vdd) <= MMC_VDD_23_24)
648 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
651 OMAP_HSMMC_WRITE(host->base, HCTL,
652 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
654 OMAP_HSMMC_WRITE(host->base, CAPA,
655 OMAP_HSMMC_READ(host->base, CAPA) | capa);
657 OMAP_HSMMC_WRITE(host->base, HCTL,
658 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
660 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
661 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
662 && time_before(jiffies, timeout))
665 OMAP_HSMMC_WRITE(host->base, ISE, 0);
666 OMAP_HSMMC_WRITE(host->base, IE, 0);
667 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
669 /* Do not initialize card-specific things if the power is off */
670 if (host->power_mode == MMC_POWER_OFF)
673 omap_hsmmc_set_bus_width(host);
675 omap_hsmmc_set_clock(host);
677 omap_hsmmc_set_bus_mode(host);
680 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
686 * Save the MMC host context (store the number of power state changes so far).
688 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
690 host->con = OMAP_HSMMC_READ(host->base, CON);
691 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
692 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
693 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
698 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
703 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
710 * Send init stream sequence to card
711 * before sending IDLE command
713 static void send_init_stream(struct omap_hsmmc_host *host)
716 unsigned long timeout;
718 if (host->protect_card)
721 disable_irq(host->irq);
723 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
724 OMAP_HSMMC_WRITE(host->base, CON,
725 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
726 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
728 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
729 while ((reg != CC_EN) && time_before(jiffies, timeout))
730 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
732 OMAP_HSMMC_WRITE(host->base, CON,
733 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
735 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
736 OMAP_HSMMC_READ(host->base, STAT);
738 enable_irq(host->irq);
742 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
746 if (host->get_cover_state)
747 r = host->get_cover_state(host->dev);
752 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
755 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
756 struct omap_hsmmc_host *host = mmc_priv(mmc);
758 return sprintf(buf, "%s\n",
759 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
762 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
765 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
768 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
769 struct omap_hsmmc_host *host = mmc_priv(mmc);
771 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
774 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
777 * Configure the response type and send the cmd.
780 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
781 struct mmc_data *data)
783 int cmdreg = 0, resptype = 0, cmdtype = 0;
785 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
786 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
789 omap_hsmmc_enable_irq(host, cmd);
791 host->response_busy = 0;
792 if (cmd->flags & MMC_RSP_PRESENT) {
793 if (cmd->flags & MMC_RSP_136)
795 else if (cmd->flags & MMC_RSP_BUSY) {
797 host->response_busy = 1;
803 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
804 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
805 * a val of 0x3, rest 0x0.
807 if (cmd == host->mrq->stop)
810 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
812 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
814 cmdreg |= ACEN_ACMD23;
815 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
818 cmdreg |= DP_SELECT | MSBS | BCE;
819 if (data->flags & MMC_DATA_READ)
828 host->req_in_progress = 1;
830 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
831 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
835 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
837 if (data->flags & MMC_DATA_WRITE)
838 return DMA_TO_DEVICE;
840 return DMA_FROM_DEVICE;
843 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
844 struct mmc_data *data)
846 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
849 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
854 spin_lock_irqsave(&host->irq_lock, flags);
855 host->req_in_progress = 0;
856 dma_ch = host->dma_ch;
857 spin_unlock_irqrestore(&host->irq_lock, flags);
859 omap_hsmmc_disable_irq(host);
860 /* Do not complete the request if DMA is still in progress */
861 if (mrq->data && host->use_dma && dma_ch != -1)
864 mmc_request_done(host->mmc, mrq);
865 pm_runtime_mark_last_busy(host->dev);
866 pm_runtime_put_autosuspend(host->dev);
870 * Notify the transfer complete to MMC core
873 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
876 struct mmc_request *mrq = host->mrq;
878 /* TC before CC from CMD6 - don't know why, but it happens */
879 if (host->cmd && host->cmd->opcode == 6 &&
880 host->response_busy) {
881 host->response_busy = 0;
885 omap_hsmmc_request_done(host, mrq);
892 data->bytes_xfered += data->blocks * (data->blksz);
894 data->bytes_xfered = 0;
896 if (data->stop && (data->error || !host->mrq->sbc))
897 omap_hsmmc_start_command(host, data->stop, NULL);
899 omap_hsmmc_request_done(host, data->mrq);
903 * Notify the core about command completion
906 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
908 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
909 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
911 omap_hsmmc_start_dma_transfer(host);
912 omap_hsmmc_start_command(host, host->mrq->cmd,
919 if (cmd->flags & MMC_RSP_PRESENT) {
920 if (cmd->flags & MMC_RSP_136) {
921 /* response type 2 */
922 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
923 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
924 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
925 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
927 /* response types 1, 1b, 3, 4, 5, 6 */
928 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
931 if ((host->data == NULL && !host->response_busy) || cmd->error)
932 omap_hsmmc_request_done(host, host->mrq);
936 * DMA clean up for command errors
938 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
943 host->data->error = errno;
945 spin_lock_irqsave(&host->irq_lock, flags);
946 dma_ch = host->dma_ch;
948 spin_unlock_irqrestore(&host->irq_lock, flags);
950 if (host->use_dma && dma_ch != -1) {
951 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
953 dmaengine_terminate_all(chan);
954 dma_unmap_sg(chan->device->dev,
955 host->data->sg, host->data->sg_len,
956 omap_hsmmc_get_dma_dir(host, host->data));
958 host->data->host_cookie = 0;
964 * Readable error output
966 #ifdef CONFIG_MMC_DEBUG
967 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
969 /* --- means reserved bit without definition at documentation */
970 static const char *omap_hsmmc_status_bits[] = {
971 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
972 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
973 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
974 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
980 len = sprintf(buf, "MMC IRQ 0x%x :", status);
983 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
984 if (status & (1 << i)) {
985 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
989 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
992 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
996 #endif /* CONFIG_MMC_DEBUG */
999 * MMC controller internal state machines reset
1001 * Used to reset command or data internal state machines, using respectively
1002 * SRC or SRD bit of SYSCTL register
1003 * Can be called from interrupt context
1005 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1008 unsigned long i = 0;
1009 unsigned long limit = MMC_TIMEOUT_US;
1011 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1012 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1015 * OMAP4 ES2 and greater has an updated reset logic.
1016 * Monitor a 0->1 transition first
1018 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1019 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1025 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1029 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1030 dev_err(mmc_dev(host->mmc),
1031 "Timeout waiting on controller reset in %s\n",
1035 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1036 int err, int end_cmd)
1039 omap_hsmmc_reset_controller_fsm(host, SRC);
1041 host->cmd->error = err;
1045 omap_hsmmc_reset_controller_fsm(host, SRD);
1046 omap_hsmmc_dma_cleanup(host, err);
1047 } else if (host->mrq && host->mrq->cmd)
1048 host->mrq->cmd->error = err;
1051 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1053 struct mmc_data *data;
1054 int end_cmd = 0, end_trans = 0;
1058 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1060 if (status & ERR_EN) {
1061 omap_hsmmc_dbg_report_irq(host, status);
1063 if (status & (CTO_EN | CCRC_EN))
1065 if (status & (CTO_EN | DTO_EN))
1066 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1067 else if (status & (CCRC_EN | DCRC_EN))
1068 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1070 if (status & ACE_EN) {
1072 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1073 if (!(ac12 & ACNE) && host->mrq->sbc) {
1077 else if (ac12 & (ACCE | ACEB | ACIE))
1079 host->mrq->sbc->error = error;
1080 hsmmc_command_incomplete(host, error, end_cmd);
1082 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1084 if (host->data || host->response_busy) {
1085 end_trans = !end_cmd;
1086 host->response_busy = 0;
1090 OMAP_HSMMC_WRITE(host->base, STAT, status);
1091 if (end_cmd || ((status & CC_EN) && host->cmd))
1092 omap_hsmmc_cmd_done(host, host->cmd);
1093 if ((end_trans || (status & TC_EN)) && host->mrq)
1094 omap_hsmmc_xfer_done(host, data);
1098 * MMC controller IRQ handler
1100 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1102 struct omap_hsmmc_host *host = dev_id;
1105 status = OMAP_HSMMC_READ(host->base, STAT);
1106 while (status & (INT_EN_MASK | CIRQ_EN)) {
1107 if (host->req_in_progress)
1108 omap_hsmmc_do_irq(host, status);
1110 if (status & CIRQ_EN)
1111 mmc_signal_sdio_irq(host->mmc);
1113 /* Flush posted write */
1114 status = OMAP_HSMMC_READ(host->base, STAT);
1120 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1122 struct omap_hsmmc_host *host = dev_id;
1124 /* cirq is level triggered, disable to avoid infinite loop */
1125 spin_lock(&host->irq_lock);
1126 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1127 disable_irq_nosync(host->wake_irq);
1128 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1130 spin_unlock(&host->irq_lock);
1131 pm_request_resume(host->dev); /* no use counter */
1136 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1140 OMAP_HSMMC_WRITE(host->base, HCTL,
1141 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1142 for (i = 0; i < loops_per_jiffy; i++) {
1143 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1150 * Switch MMC interface voltage ... only relevant for MMC1.
1152 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1153 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1154 * Some chips, like eMMC ones, use internal transceivers.
1156 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1161 /* Disable the clocks */
1162 pm_runtime_put_sync(host->dev);
1164 clk_disable_unprepare(host->dbclk);
1166 /* Turn the power off */
1167 ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1169 /* Turn the power ON with given VDD 1.8 or 3.0v */
1171 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1172 pm_runtime_get_sync(host->dev);
1174 clk_prepare_enable(host->dbclk);
1179 OMAP_HSMMC_WRITE(host->base, HCTL,
1180 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1181 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1184 * If a MMC dual voltage card is detected, the set_ios fn calls
1185 * this fn with VDD bit set for 1.8V. Upon card removal from the
1186 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1188 * Cope with a bit of slop in the range ... per data sheets:
1189 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1190 * but recommended values are 1.71V to 1.89V
1191 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1192 * but recommended values are 2.7V to 3.3V
1194 * Board setup code shouldn't permit anything very out-of-range.
1195 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1196 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1198 if ((1 << vdd) <= MMC_VDD_23_24)
1203 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1204 set_sd_bus_power(host);
1208 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1212 /* Protect the card while the cover is open */
1213 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1215 if (!host->get_cover_state)
1218 host->reqs_blocked = 0;
1219 if (host->get_cover_state(host->dev)) {
1220 if (host->protect_card) {
1221 dev_info(host->dev, "%s: cover is closed, "
1222 "card is now accessible\n",
1223 mmc_hostname(host->mmc));
1224 host->protect_card = 0;
1227 if (!host->protect_card) {
1228 dev_info(host->dev, "%s: cover is open, "
1229 "card is now inaccessible\n",
1230 mmc_hostname(host->mmc));
1231 host->protect_card = 1;
1237 * irq handler when (cell-phone) cover is mounted/removed
1239 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1241 struct omap_hsmmc_host *host = dev_id;
1243 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1245 omap_hsmmc_protect_card(host);
1246 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1250 static void omap_hsmmc_dma_callback(void *param)
1252 struct omap_hsmmc_host *host = param;
1253 struct dma_chan *chan;
1254 struct mmc_data *data;
1255 int req_in_progress;
1257 spin_lock_irq(&host->irq_lock);
1258 if (host->dma_ch < 0) {
1259 spin_unlock_irq(&host->irq_lock);
1263 data = host->mrq->data;
1264 chan = omap_hsmmc_get_dma_chan(host, data);
1265 if (!data->host_cookie)
1266 dma_unmap_sg(chan->device->dev,
1267 data->sg, data->sg_len,
1268 omap_hsmmc_get_dma_dir(host, data));
1270 req_in_progress = host->req_in_progress;
1272 spin_unlock_irq(&host->irq_lock);
1274 /* If DMA has finished after TC, complete the request */
1275 if (!req_in_progress) {
1276 struct mmc_request *mrq = host->mrq;
1279 mmc_request_done(host->mmc, mrq);
1280 pm_runtime_mark_last_busy(host->dev);
1281 pm_runtime_put_autosuspend(host->dev);
1285 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1286 struct mmc_data *data,
1287 struct omap_hsmmc_next *next,
1288 struct dma_chan *chan)
1292 if (!next && data->host_cookie &&
1293 data->host_cookie != host->next_data.cookie) {
1294 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1295 " host->next_data.cookie %d\n",
1296 __func__, data->host_cookie, host->next_data.cookie);
1297 data->host_cookie = 0;
1300 /* Check if next job is already prepared */
1301 if (next || data->host_cookie != host->next_data.cookie) {
1302 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1303 omap_hsmmc_get_dma_dir(host, data));
1306 dma_len = host->next_data.dma_len;
1307 host->next_data.dma_len = 0;
1315 next->dma_len = dma_len;
1316 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1318 host->dma_len = dma_len;
1324 * Routine to configure and start DMA for the MMC card
1326 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1327 struct mmc_request *req)
1329 struct dma_slave_config cfg;
1330 struct dma_async_tx_descriptor *tx;
1332 struct mmc_data *data = req->data;
1333 struct dma_chan *chan;
1335 /* Sanity check: all the SG entries must be aligned by block size. */
1336 for (i = 0; i < data->sg_len; i++) {
1337 struct scatterlist *sgl;
1340 if (sgl->length % data->blksz)
1343 if ((data->blksz % 4) != 0)
1344 /* REVISIT: The MMC buffer increments only when MSB is written.
1345 * Return error for blksz which is non multiple of four.
1349 BUG_ON(host->dma_ch != -1);
1351 chan = omap_hsmmc_get_dma_chan(host, data);
1353 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1354 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1355 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1356 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1357 cfg.src_maxburst = data->blksz / 4;
1358 cfg.dst_maxburst = data->blksz / 4;
1360 ret = dmaengine_slave_config(chan, &cfg);
1364 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1368 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1369 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1372 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1373 /* FIXME: cleanup */
1377 tx->callback = omap_hsmmc_dma_callback;
1378 tx->callback_param = host;
1381 dmaengine_submit(tx);
1388 static void set_data_timeout(struct omap_hsmmc_host *host,
1389 unsigned int timeout_ns,
1390 unsigned int timeout_clks)
1392 unsigned int timeout, cycle_ns;
1393 uint32_t reg, clkd, dto = 0;
1395 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1396 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1400 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1401 timeout = timeout_ns / cycle_ns;
1402 timeout += timeout_clks;
1404 while ((timeout & 0x80000000) == 0) {
1421 reg |= dto << DTO_SHIFT;
1422 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1425 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1427 struct mmc_request *req = host->mrq;
1428 struct dma_chan *chan;
1432 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1433 | (req->data->blocks << 16));
1434 set_data_timeout(host, req->data->timeout_ns,
1435 req->data->timeout_clks);
1436 chan = omap_hsmmc_get_dma_chan(host, req->data);
1437 dma_async_issue_pending(chan);
1441 * Configure block length for MMC/SD cards and initiate the transfer.
1444 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1447 host->data = req->data;
1449 if (req->data == NULL) {
1450 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1452 * Set an arbitrary 100ms data timeout for commands with
1455 if (req->cmd->flags & MMC_RSP_BUSY)
1456 set_data_timeout(host, 100000000U, 0);
1460 if (host->use_dma) {
1461 ret = omap_hsmmc_setup_dma_transfer(host, req);
1463 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1470 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1473 struct omap_hsmmc_host *host = mmc_priv(mmc);
1474 struct mmc_data *data = mrq->data;
1476 if (host->use_dma && data->host_cookie) {
1477 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1479 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1480 omap_hsmmc_get_dma_dir(host, data));
1481 data->host_cookie = 0;
1485 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1488 struct omap_hsmmc_host *host = mmc_priv(mmc);
1490 if (mrq->data->host_cookie) {
1491 mrq->data->host_cookie = 0;
1495 if (host->use_dma) {
1496 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1498 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1499 &host->next_data, c))
1500 mrq->data->host_cookie = 0;
1505 * Request function. for read/write operation
1507 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1512 BUG_ON(host->req_in_progress);
1513 BUG_ON(host->dma_ch != -1);
1514 pm_runtime_get_sync(host->dev);
1515 if (host->protect_card) {
1516 if (host->reqs_blocked < 3) {
1518 * Ensure the controller is left in a consistent
1519 * state by resetting the command and data state
1522 omap_hsmmc_reset_controller_fsm(host, SRD);
1523 omap_hsmmc_reset_controller_fsm(host, SRC);
1524 host->reqs_blocked += 1;
1526 req->cmd->error = -EBADF;
1528 req->data->error = -EBADF;
1529 req->cmd->retries = 0;
1530 mmc_request_done(mmc, req);
1531 pm_runtime_mark_last_busy(host->dev);
1532 pm_runtime_put_autosuspend(host->dev);
1534 } else if (host->reqs_blocked)
1535 host->reqs_blocked = 0;
1536 WARN_ON(host->mrq != NULL);
1538 host->clk_rate = clk_get_rate(host->fclk);
1539 err = omap_hsmmc_prepare_data(host, req);
1541 req->cmd->error = err;
1543 req->data->error = err;
1545 mmc_request_done(mmc, req);
1546 pm_runtime_mark_last_busy(host->dev);
1547 pm_runtime_put_autosuspend(host->dev);
1550 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1551 omap_hsmmc_start_command(host, req->sbc, NULL);
1555 omap_hsmmc_start_dma_transfer(host);
1556 omap_hsmmc_start_command(host, req->cmd, req->data);
1559 /* Routine to configure clock values. Exposed API to core */
1560 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
1563 int do_send_init_stream = 0;
1565 pm_runtime_get_sync(host->dev);
1567 if (ios->power_mode != host->power_mode) {
1568 switch (ios->power_mode) {
1570 mmc_pdata(host)->set_power(host->dev, 0, 0);
1573 mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1576 do_send_init_stream = 1;
1579 host->power_mode = ios->power_mode;
1582 /* FIXME: set registers based only on changes to ios */
1584 omap_hsmmc_set_bus_width(host);
1586 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1587 /* Only MMC1 can interface at 3V without some flavor
1588 * of external transceiver; but they all handle 1.8V.
1590 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1591 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1593 * The mmc_select_voltage fn of the core does
1594 * not seem to set the power_mode to
1595 * MMC_POWER_UP upon recalculating the voltage.
1598 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1599 dev_dbg(mmc_dev(host->mmc),
1600 "Switch operation failed\n");
1604 omap_hsmmc_set_clock(host);
1606 if (do_send_init_stream)
1607 send_init_stream(host);
1609 omap_hsmmc_set_bus_mode(host);
1611 pm_runtime_put_autosuspend(host->dev);
1614 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1616 struct omap_hsmmc_host *host = mmc_priv(mmc);
1618 if (!host->card_detect)
1620 return host->card_detect(host->dev);
1623 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1625 struct omap_hsmmc_host *host = mmc_priv(mmc);
1627 if (mmc_pdata(host)->init_card)
1628 mmc_pdata(host)->init_card(card);
1631 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1633 struct omap_hsmmc_host *host = mmc_priv(mmc);
1635 unsigned long flags;
1637 spin_lock_irqsave(&host->irq_lock, flags);
1639 con = OMAP_HSMMC_READ(host->base, CON);
1640 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1642 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1643 irq_mask |= CIRQ_EN;
1644 con |= CTPL | CLKEXTFREE;
1646 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1647 irq_mask &= ~CIRQ_EN;
1648 con &= ~(CTPL | CLKEXTFREE);
1650 OMAP_HSMMC_WRITE(host->base, CON, con);
1651 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1654 * if enable, piggy back detection on current request
1655 * but always disable immediately
1657 if (!host->req_in_progress || !enable)
1658 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1660 /* flush posted write */
1661 OMAP_HSMMC_READ(host->base, IE);
1663 spin_unlock_irqrestore(&host->irq_lock, flags);
1666 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1668 struct mmc_host *mmc = host->mmc;
1672 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1673 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1674 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1675 * with functional clock disabled.
1677 if (!host->dev->of_node || !host->wake_irq)
1680 /* Prevent auto-enabling of IRQ */
1681 irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1682 ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1683 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1684 mmc_hostname(mmc), host);
1686 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1691 * Some omaps don't have wake-up path from deeper idle states
1692 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1694 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1695 struct pinctrl *p = devm_pinctrl_get(host->dev);
1700 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1701 dev_info(host->dev, "missing default pinctrl state\n");
1702 devm_pinctrl_put(p);
1707 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1708 dev_info(host->dev, "missing idle pinctrl state\n");
1709 devm_pinctrl_put(p);
1713 devm_pinctrl_put(p);
1716 OMAP_HSMMC_WRITE(host->base, HCTL,
1717 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1721 devm_free_irq(host->dev, host->wake_irq, host);
1723 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1728 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1730 u32 hctl, capa, value;
1732 /* Only MMC1 supports 3.0V */
1733 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1741 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1742 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1744 value = OMAP_HSMMC_READ(host->base, CAPA);
1745 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1747 /* Set SD bus power bit */
1748 set_sd_bus_power(host);
1751 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1752 unsigned int direction, int blk_size)
1754 /* This controller can't do multiblock reads due to hw bugs */
1755 if (direction == MMC_DATA_READ)
1761 static struct mmc_host_ops omap_hsmmc_ops = {
1762 .post_req = omap_hsmmc_post_req,
1763 .pre_req = omap_hsmmc_pre_req,
1764 .request = omap_hsmmc_request,
1765 .set_ios = omap_hsmmc_set_ios,
1766 .get_cd = omap_hsmmc_get_cd,
1767 .get_ro = mmc_gpio_get_ro,
1768 .init_card = omap_hsmmc_init_card,
1769 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1772 #ifdef CONFIG_DEBUG_FS
1774 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1776 struct mmc_host *mmc = s->private;
1777 struct omap_hsmmc_host *host = mmc_priv(mmc);
1779 seq_printf(s, "mmc%d:\n", mmc->index);
1780 seq_printf(s, "sdio irq mode\t%s\n",
1781 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1783 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1784 seq_printf(s, "sdio irq \t%s\n",
1785 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1788 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1790 pm_runtime_get_sync(host->dev);
1791 seq_puts(s, "\nregs:\n");
1792 seq_printf(s, "CON:\t\t0x%08x\n",
1793 OMAP_HSMMC_READ(host->base, CON));
1794 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1795 OMAP_HSMMC_READ(host->base, PSTATE));
1796 seq_printf(s, "HCTL:\t\t0x%08x\n",
1797 OMAP_HSMMC_READ(host->base, HCTL));
1798 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1799 OMAP_HSMMC_READ(host->base, SYSCTL));
1800 seq_printf(s, "IE:\t\t0x%08x\n",
1801 OMAP_HSMMC_READ(host->base, IE));
1802 seq_printf(s, "ISE:\t\t0x%08x\n",
1803 OMAP_HSMMC_READ(host->base, ISE));
1804 seq_printf(s, "CAPA:\t\t0x%08x\n",
1805 OMAP_HSMMC_READ(host->base, CAPA));
1807 pm_runtime_mark_last_busy(host->dev);
1808 pm_runtime_put_autosuspend(host->dev);
1813 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1815 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1818 static const struct file_operations mmc_regs_fops = {
1819 .open = omap_hsmmc_regs_open,
1821 .llseek = seq_lseek,
1822 .release = single_release,
1825 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1827 if (mmc->debugfs_root)
1828 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1829 mmc, &mmc_regs_fops);
1834 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1841 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1842 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1843 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1846 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1847 .reg_offset = 0x100,
1849 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1850 .reg_offset = 0x100,
1851 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1854 static const struct of_device_id omap_mmc_of_match[] = {
1856 .compatible = "ti,omap2-hsmmc",
1859 .compatible = "ti,omap3-pre-es3-hsmmc",
1860 .data = &omap3_pre_es3_mmc_of_data,
1863 .compatible = "ti,omap3-hsmmc",
1866 .compatible = "ti,omap4-hsmmc",
1867 .data = &omap4_mmc_of_data,
1870 .compatible = "ti,am33xx-hsmmc",
1871 .data = &am33xx_mmc_of_data,
1875 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1877 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1879 struct omap_hsmmc_platform_data *pdata;
1880 struct device_node *np = dev->of_node;
1882 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1884 return ERR_PTR(-ENOMEM); /* out of memory */
1886 if (of_find_property(np, "ti,dual-volt", NULL))
1887 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1889 pdata->gpio_cd = -EINVAL;
1890 pdata->gpio_cod = -EINVAL;
1891 pdata->gpio_wp = -EINVAL;
1893 if (of_find_property(np, "ti,non-removable", NULL)) {
1894 pdata->nonremovable = true;
1895 pdata->no_regulator_off_init = true;
1898 if (of_find_property(np, "ti,needs-special-reset", NULL))
1899 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1901 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1902 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1907 static inline struct omap_hsmmc_platform_data
1908 *of_get_hsmmc_pdata(struct device *dev)
1910 return ERR_PTR(-EINVAL);
1914 static int omap_hsmmc_probe(struct platform_device *pdev)
1916 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1917 struct mmc_host *mmc;
1918 struct omap_hsmmc_host *host = NULL;
1919 struct resource *res;
1921 const struct of_device_id *match;
1922 dma_cap_mask_t mask;
1923 unsigned tx_req, rx_req;
1924 const struct omap_mmc_of_data *data;
1927 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1929 pdata = of_get_hsmmc_pdata(&pdev->dev);
1932 return PTR_ERR(pdata);
1936 pdata->reg_offset = data->reg_offset;
1937 pdata->controller_flags |= data->controller_flags;
1941 if (pdata == NULL) {
1942 dev_err(&pdev->dev, "Platform Data is missing\n");
1946 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1947 irq = platform_get_irq(pdev, 0);
1948 if (res == NULL || irq < 0)
1951 base = devm_ioremap_resource(&pdev->dev, res);
1953 return PTR_ERR(base);
1955 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1961 ret = mmc_of_parse(mmc);
1965 host = mmc_priv(mmc);
1967 host->pdata = pdata;
1968 host->dev = &pdev->dev;
1972 host->mapbase = res->start + pdata->reg_offset;
1973 host->base = base + pdata->reg_offset;
1974 host->power_mode = MMC_POWER_OFF;
1975 host->next_data.cookie = 1;
1976 host->pbias_enabled = 0;
1978 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1982 platform_set_drvdata(pdev, host);
1984 if (pdev->dev.of_node)
1985 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1987 mmc->ops = &omap_hsmmc_ops;
1989 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1991 if (pdata->max_freq > 0)
1992 mmc->f_max = pdata->max_freq;
1993 else if (mmc->f_max == 0)
1994 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1996 spin_lock_init(&host->irq_lock);
1998 host->fclk = devm_clk_get(&pdev->dev, "fck");
1999 if (IS_ERR(host->fclk)) {
2000 ret = PTR_ERR(host->fclk);
2005 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2006 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2007 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2010 pm_runtime_enable(host->dev);
2011 pm_runtime_get_sync(host->dev);
2012 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2013 pm_runtime_use_autosuspend(host->dev);
2015 omap_hsmmc_context_save(host);
2017 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2019 * MMC can still work without debounce clock.
2021 if (IS_ERR(host->dbclk)) {
2023 } else if (clk_prepare_enable(host->dbclk) != 0) {
2024 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2028 /* Since we do only SG emulation, we can have as many segs
2030 mmc->max_segs = 1024;
2032 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2033 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2034 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2035 mmc->max_seg_size = mmc->max_req_size;
2037 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2038 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2040 mmc->caps |= mmc_pdata(host)->caps;
2041 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2042 mmc->caps |= MMC_CAP_4_BIT_DATA;
2044 if (mmc_pdata(host)->nonremovable)
2045 mmc->caps |= MMC_CAP_NONREMOVABLE;
2047 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2049 omap_hsmmc_conf_bus_power(host);
2051 if (!pdev->dev.of_node) {
2052 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2054 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2058 tx_req = res->start;
2060 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2062 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2066 rx_req = res->start;
2070 dma_cap_set(DMA_SLAVE, mask);
2073 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2074 &rx_req, &pdev->dev, "rx");
2076 if (!host->rx_chan) {
2077 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2083 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2084 &tx_req, &pdev->dev, "tx");
2086 if (!host->tx_chan) {
2087 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2092 /* Request IRQ for MMC operations */
2093 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2094 mmc_hostname(mmc), host);
2096 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2100 if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2101 ret = omap_hsmmc_reg_get(host);
2107 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2109 omap_hsmmc_disable_irq(host);
2112 * For now, only support SDIO interrupt if we have a separate
2113 * wake-up interrupt configured from device tree. This is because
2114 * the wake-up interrupt is needed for idle state and some
2115 * platforms need special quirks. And we don't want to add new
2116 * legacy mux platform init code callbacks any longer as we
2117 * are moving to DT based booting anyways.
2119 ret = omap_hsmmc_configure_wake_irq(host);
2121 mmc->caps |= MMC_CAP_SDIO_IRQ;
2123 omap_hsmmc_protect_card(host);
2127 if (mmc_pdata(host)->name != NULL) {
2128 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2132 if (host->get_cover_state) {
2133 ret = device_create_file(&mmc->class_dev,
2134 &dev_attr_cover_switch);
2139 omap_hsmmc_debugfs(mmc);
2140 pm_runtime_mark_last_busy(host->dev);
2141 pm_runtime_put_autosuspend(host->dev);
2146 mmc_remove_host(mmc);
2148 omap_hsmmc_reg_put(host);
2151 dma_release_channel(host->tx_chan);
2153 dma_release_channel(host->rx_chan);
2154 pm_runtime_put_sync(host->dev);
2155 pm_runtime_disable(host->dev);
2157 clk_disable_unprepare(host->dbclk);
2165 static int omap_hsmmc_remove(struct platform_device *pdev)
2167 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2169 pm_runtime_get_sync(host->dev);
2170 mmc_remove_host(host->mmc);
2172 omap_hsmmc_reg_put(host);
2175 dma_release_channel(host->tx_chan);
2177 dma_release_channel(host->rx_chan);
2179 pm_runtime_put_sync(host->dev);
2180 pm_runtime_disable(host->dev);
2182 clk_disable_unprepare(host->dbclk);
2184 mmc_free_host(host->mmc);
2189 #ifdef CONFIG_PM_SLEEP
2190 static int omap_hsmmc_suspend(struct device *dev)
2192 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2197 pm_runtime_get_sync(host->dev);
2199 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2200 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2201 OMAP_HSMMC_WRITE(host->base, IE, 0);
2202 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2203 OMAP_HSMMC_WRITE(host->base, HCTL,
2204 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2207 /* do not wake up due to sdio irq */
2208 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2209 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2210 disable_irq(host->wake_irq);
2213 clk_disable_unprepare(host->dbclk);
2215 pm_runtime_put_sync(host->dev);
2219 /* Routine to resume the MMC device */
2220 static int omap_hsmmc_resume(struct device *dev)
2222 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2227 pm_runtime_get_sync(host->dev);
2230 clk_prepare_enable(host->dbclk);
2232 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2233 omap_hsmmc_conf_bus_power(host);
2235 omap_hsmmc_protect_card(host);
2237 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2238 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2239 enable_irq(host->wake_irq);
2241 pm_runtime_mark_last_busy(host->dev);
2242 pm_runtime_put_autosuspend(host->dev);
2247 static int omap_hsmmc_runtime_suspend(struct device *dev)
2249 struct omap_hsmmc_host *host;
2250 unsigned long flags;
2253 host = platform_get_drvdata(to_platform_device(dev));
2254 omap_hsmmc_context_save(host);
2255 dev_dbg(dev, "disabled\n");
2257 spin_lock_irqsave(&host->irq_lock, flags);
2258 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2259 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2260 /* disable sdio irq handling to prevent race */
2261 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2262 OMAP_HSMMC_WRITE(host->base, IE, 0);
2264 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2266 * dat1 line low, pending sdio irq
2267 * race condition: possible irq handler running on
2270 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2271 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2272 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2273 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2274 pm_runtime_mark_last_busy(dev);
2279 pinctrl_pm_select_idle_state(dev);
2281 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2282 enable_irq(host->wake_irq);
2283 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2285 pinctrl_pm_select_idle_state(dev);
2289 spin_unlock_irqrestore(&host->irq_lock, flags);
2293 static int omap_hsmmc_runtime_resume(struct device *dev)
2295 struct omap_hsmmc_host *host;
2296 unsigned long flags;
2298 host = platform_get_drvdata(to_platform_device(dev));
2299 omap_hsmmc_context_restore(host);
2300 dev_dbg(dev, "enabled\n");
2302 spin_lock_irqsave(&host->irq_lock, flags);
2303 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2304 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2305 /* sdio irq flag can't change while in runtime suspend */
2306 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2307 disable_irq_nosync(host->wake_irq);
2308 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2311 pinctrl_pm_select_default_state(host->dev);
2313 /* irq lost, if pinmux incorrect */
2314 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2315 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2316 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2318 pinctrl_pm_select_default_state(host->dev);
2320 spin_unlock_irqrestore(&host->irq_lock, flags);
2324 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2325 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2326 .runtime_suspend = omap_hsmmc_runtime_suspend,
2327 .runtime_resume = omap_hsmmc_runtime_resume,
2330 static struct platform_driver omap_hsmmc_driver = {
2331 .probe = omap_hsmmc_probe,
2332 .remove = omap_hsmmc_remove,
2334 .name = DRIVER_NAME,
2335 .pm = &omap_hsmmc_dev_pm_ops,
2336 .of_match_table = of_match_ptr(omap_mmc_of_match),
2340 module_platform_driver(omap_hsmmc_driver);
2341 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2342 MODULE_LICENSE("GPL");
2343 MODULE_ALIAS("platform:" DRIVER_NAME);
2344 MODULE_AUTHOR("Texas Instruments Inc");