1 /* drivers/mmc/host/rk29_sdmmc.c
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/blkdev.h>
17 #include <linux/clk.h>
18 #include <linux/debugfs.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/scatterlist.h>
28 #include <linux/seq_file.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/mmc.h>
35 #include <mach/board.h>
36 #include <mach/rk29_iomap.h>
37 #include <mach/gpio.h>
39 #include <mach/rk29-dma-pl330.h>
40 #include <asm/scatterlist.h>
42 #include "rk2818-sdmmc.h"
44 #define RK29_SDMMC_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | SDMMC_INT_HTO | SDMMC_INT_SBE | SDMMC_INT_EBE)
45 #define RK29_SDMMC_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | SDMMC_INT_RE | SDMMC_INT_HLE)
46 #define RK29_SDMMC_ERROR_FLAGS (RK29_SDMMC_DATA_ERROR_FLAGS | RK29_SDMMC_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47 #define RK29_SDMMC_SEND_STATUS 1
48 #define RK29_SDMMC_RECV_STATUS 2
49 #define RK29_SDMMC_DMA_THRESHOLD 16
52 EVENT_CMD_COMPLETE = 0,
59 enum rk29_sdmmc_state {
68 static struct rk29_dma_client rk29_dma_sdmmc0_client = {
69 .name = "rk29-dma-sdmmc0",
72 static struct rk29_dma_client rk29_dma_sdio1_client = {
73 .name = "rk29-dma-sdio1",
80 struct scatterlist *sg;
81 unsigned int pio_offset;
82 struct mmc_request *mrq;
83 struct mmc_request *curr_mrq;
84 struct mmc_command *cmd;
85 struct mmc_data *data;
88 //dma_sg_ll_t *sg_cpu;
89 unsigned int use_dma:1;
95 struct tasklet_struct tasklet;
96 unsigned long pending_events;
97 unsigned long completed_events;
98 enum rk29_sdmmc_state state;
99 struct list_head queue;
102 struct platform_device *pdev;
103 struct mmc_host *mmc;
105 struct list_head queue_node;
108 #define RK29_SDMMC_CARD_PRESENT 0
109 #define RK29_SDMMC_CARD_NEED_INIT 1
110 #define RK29_SDMMC_SHUTDOWN 2
113 struct timer_list detect_timer;
114 unsigned int oldstatus;
117 #define rk29_sdmmc_test_and_clear_pending(host, event) \
118 test_and_clear_bit(event, &host->pending_events)
119 #define rk29_sdmmc_set_completed(host, event) \
120 set_bit(event, &host->completed_events)
122 #define rk29_sdmmc_set_pending(host, event) \
123 set_bit(event, &host->pending_events)
125 static void rk29_sdmmc_write(unsigned char __iomem *regbase, unsigned int regOff,unsigned int val)
127 __raw_writel(val,regbase + regOff);
130 static unsigned int rk29_sdmmc_read(unsigned char __iomem *regbase, unsigned int regOff)
132 return __raw_readl(regbase + regOff);
136 #if defined (CONFIG_DEBUG_FS)
138 * The debugfs stuff below is mostly optimized away when
139 * CONFIG_DEBUG_FS is not set.
141 static int rk29_sdmmc_req_show(struct seq_file *s, void *v)
143 struct rk29_sdmmc *host = s->private;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_command *stop;
147 struct mmc_data *data;
149 /* Make sure we get a consistent snapshot */
150 spin_lock(&host->lock);
160 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
161 cmd->opcode, cmd->arg, cmd->flags,
162 cmd->resp[0], cmd->resp[1], cmd->resp[2],
163 cmd->resp[2], cmd->error);
165 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
166 data->bytes_xfered, data->blocks,
167 data->blksz, data->flags, data->error);
170 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
171 stop->opcode, stop->arg, stop->flags,
172 stop->resp[0], stop->resp[1], stop->resp[2],
173 stop->resp[2], stop->error);
176 spin_unlock(&host->lock);
181 static int rk29_sdmmc_req_open(struct inode *inode, struct file *file)
183 return single_open(file, rk29_sdmmc_req_show, inode->i_private);
186 static const struct file_operations rk29_sdmmc_req_fops = {
187 .owner = THIS_MODULE,
188 .open = rk29_sdmmc_req_open,
191 .release = single_release,
194 static int rk29_sdmmc_regs_show(struct seq_file *s, void *v)
196 struct rk29_sdmmc *host = s->private;
198 seq_printf(s, "SDMMC_CTRL: \t0x%08x\n", SDMMC_CTRL);
199 seq_printf(s, "SDMMC_PWREN: \t0x%08x\n", SDMMC_PWREN);
200 seq_printf(s, "SDMMC_CLKDIV: \t0x%08x\n", SDMMC_CLKDIV);
201 seq_printf(s, "SDMMC_CLKSRC: \t0x%08x\n", SDMMC_CLKSRC);
202 seq_printf(s, "SDMMC_CLKENA: \t0x%08x\n", SDMMC_CLKENA);
203 seq_printf(s, "SDMMC_TMOUT: \t0x%08x\n", SDMMC_TMOUT);
204 seq_printf(s, "SDMMC_CTYPE: \t0x%08x\n", SDMMC_CTYPE);
205 seq_printf(s, "SDMMC_BLKSIZ: \t0x%08x\n", SDMMC_BLKSIZ);
206 seq_printf(s, "SDMMC_BYTCNT: \t0x%08x\n", SDMMC_BYTCNT);
207 seq_printf(s, "SDMMC_INTMASK:\t0x%08x\n", SDMMC_INTMASK);
208 seq_printf(s, "SDMMC_CMDARG: \t0x%08x\n", SDMMC_CMDARG);
209 seq_printf(s, "SDMMC_CMD: \t0x%08x\n", SDMMC_CMD);
210 seq_printf(s, "SDMMC_RESP0: \t0x%08x\n", SDMMC_RESP0);
211 seq_printf(s, "SDMMC_RESP1: \t0x%08x\n", SDMMC_RESP1);
212 seq_printf(s, "SDMMC_RESP2: \t0x%08x\n", SDMMC_RESP2);
213 seq_printf(s, "SDMMC_RESP3: \t0x%08x\n", SDMMC_RESP3);
214 seq_printf(s, "SDMMC_MINTSTS:\t0x%08x\n", SDMMC_MINTSTS);
215 seq_printf(s, "SDMMC_RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
216 seq_printf(s, "SDMMC_STATUS: \t0x%08x\n", SDMMC_STATUS);
217 seq_printf(s, "SDMMC_FIFOTH: \t0x%08x\n", SDMMC_FIFOTH);
218 seq_printf(s, "SDMMC_CDETECT:\t0x%08x\n", SDMMC_CDETECT);
219 seq_printf(s, "SDMMC_WRTPRT: \t0x%08x\n", SDMMC_WRTPRT);
220 seq_printf(s, "SDMMC_TCBCNT: \t0x%08x\n", SDMMC_TCBCNT);
221 seq_printf(s, "SDMMC_TBBCNT: \t0x%08x\n", SDMMC_TBBCNT);
222 seq_printf(s, "SDMMC_DEBNCE: \t0x%08x\n", SDMMC_DEBNCE);
227 static int rk29_sdmmc_regs_open(struct inode *inode, struct file *file)
229 return single_open(file, rk29_sdmmc_regs_show, inode->i_private);
232 static const struct file_operations rk29_sdmmc_regs_fops = {
233 .owner = THIS_MODULE,
234 .open = rk29_sdmmc_regs_open,
237 .release = single_release,
240 static void rk29_sdmmc_init_debugfs(struct rk29_sdmmc *host)
242 struct mmc_host *mmc = host->mmc;
246 root = mmc->debugfs_root;
250 node = debugfs_create_file("regs", S_IRUSR, root, host,
251 &rk29_sdmmc_regs_fops);
257 node = debugfs_create_file("req", S_IRUSR, root, host, &rk29_sdmmc_req_fops);
261 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
265 node = debugfs_create_x32("pending_events", S_IRUSR, root,
266 (u32 *)&host->pending_events);
270 node = debugfs_create_x32("completed_events", S_IRUSR, root,
271 (u32 *)&host->completed_events);
278 dev_err(&mmc->class_dev, "failed to initialize debugfs for host\n");
282 static inline unsigned ns_to_clocks(unsigned clkrate, unsigned ns)
285 if (clkrate > 1000000)
286 clks = (ns * (clkrate / 1000000) + 999) / 1000;
288 clks = ((ns/1000) * (clkrate / 1000) + 999) / 1000;
293 static void rk29_sdmmc_set_timeout(struct rk29_sdmmc *host,struct mmc_data *data)
297 timeout = ns_to_clocks(host->clock, data->timeout_ns) + data->timeout_clks;
298 rk29_sdmmc_write(host->regs, SDMMC_TMOUT, 0xffffffff);
299 ///rk29_sdmmc_write(host->regs, SDMMC_TMOUT, (timeout << 8) | (70));
302 static u32 rk29_sdmmc_prepare_command(struct mmc_host *mmc,
303 struct mmc_command *cmd)
305 struct mmc_data *data;
308 cmd->error = -EINPROGRESS;
312 cmdr |= SDMMC_CMD_STOP;
314 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
316 if (cmd->flags & MMC_RSP_PRESENT) {
317 cmdr |= SDMMC_CMD_RESP_EXP; // expect the respond, need to set this bit
318 if (cmd->flags & MMC_RSP_136)
319 cmdr |= SDMMC_CMD_RESP_LONG; // expect long respond
321 if(cmd->flags & MMC_RSP_CRC)
322 cmdr |= SDMMC_CMD_RESP_CRC;
327 cmdr |= SDMMC_CMD_DAT_EXP;
328 if (data->flags & MMC_DATA_STREAM)
329 cmdr |= SDMMC_CMD_STRM_MODE; // set stream mode
330 if (data->flags & MMC_DATA_WRITE)
331 cmdr |= SDMMC_CMD_DAT_WR;
337 static void rk29_sdmmc_start_command(struct rk29_sdmmc *host,
338 struct mmc_command *cmd, u32 cmd_flags)
342 dev_vdbg(&host->pdev->dev,
343 "start cmd:%d ARGR=0x%08x CMDR=0x%08x\n",
344 cmd->opcode, cmd->arg, cmd_flags);
345 rk29_sdmmc_write(host->regs, SDMMC_CMDARG, cmd->arg); // write to SDMMC_CMDARG register
346 rk29_sdmmc_write(host->regs, SDMMC_CMD, cmd_flags | SDMMC_CMD_START); // write to SDMMC_CMD register
348 /* wait until CIU accepts the command */
349 while (--tmo && (rk29_sdmmc_read(host->regs, SDMMC_CMD) & SDMMC_CMD_START))
352 printk("Enter:%s %d start tmo err!!\n",__FUNCTION__,__LINE__);
356 static void send_stop_cmd(struct rk29_sdmmc *host, struct mmc_data *data)
358 int time_out=100, time_out2=3;
361 /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/
362 while(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) {
367 local_irq_save(flags);
368 rk29_sdmmc_write( host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
369 /* wait till resets clear */
370 while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
371 local_irq_restore(flags);
378 /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/
379 if(!(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) {
380 local_irq_save(flags);
381 rk29_sdmmc_write(host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
382 /* wait till resets clear */
383 while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
384 local_irq_restore(flags);
386 rk29_sdmmc_start_command(host, data->stop, host->stop_cmdr);
389 static void rk29_sdmmc_dma_cleanup(struct rk29_sdmmc *host)
391 struct mmc_data *data = host->data;
393 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
394 ((data->flags & MMC_DATA_WRITE)
395 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
398 static void rk29_sdmmc_stop_dma(struct rk29_sdmmc *host)
400 if(host->use_dma == 0)
402 if (host->dma_chn > 0) {
403 //dma_stop_channel(host->dma_chn);
404 rk29_dma_ctrl(host->dma_chn,RK29_DMAOP_STOP);
405 rk29_sdmmc_dma_cleanup(host);
407 /* Data transfer was stopped by the interrupt handler */
408 rk29_sdmmc_set_pending(host, EVENT_XFER_COMPLETE);
412 /* This function is called by the DMA driver from tasklet context. */
413 static void rk29_sdmmc_dma_complete(void *arg, int size, enum rk29_dma_buffresult result) ///(int chn, dma_irq_type_t type, void *arg)
415 struct rk29_sdmmc *host = arg;
416 struct mmc_data *data = host->data;
418 if(host->use_dma == 0)
420 dev_vdbg(&host->pdev->dev, "DMA complete\n");
422 spin_lock(&host->lock);
423 rk29_sdmmc_dma_cleanup(host);
425 * If the card was removed, data will be NULL. No point trying
426 * to send the stop command or waiting for NBUSY in this case.
429 rk29_sdmmc_set_pending(host, EVENT_XFER_COMPLETE);
430 tasklet_schedule(&host->tasklet);
432 spin_unlock(&host->lock);
433 if(result != RK29_RES_OK){
434 rk29_dma_ctrl(host->dma_chn,RK29_DMAOP_STOP);
435 rk29_dma_ctrl(host->dma_chn,RK29_DMAOP_FLUSH);
436 rk29_sdmmc_write(host->regs, SDMMC_CTRL, (rk29_sdmmc_read(host->regs, SDMMC_CTRL))&(~SDMMC_CTRL_DMA_ENABLE));
437 printk("%s: sdio dma complete err\n",__FUNCTION__);
441 static int rk29_sdmmc_submit_data_dma(struct rk29_sdmmc *host, struct mmc_data *data)
443 struct scatterlist *sg;
444 unsigned int i,direction;
447 if(host->use_dma == 0)
449 /* If we don't have a channel, we can't do DMA */
450 if (host->dma_chn < 0)
454 * We don't do DMA on "complex" transfers, i.e. with
455 * non-word-aligned buffers or lengths. Also, we don't bother
456 * with all the DMA setup overhead for short transfers.
459 if (data->blocks * data->blksz < RK29_SDMMC_DMA_THRESHOLD)
464 for_each_sg(data->sg, sg, data->sg_len, i) {
465 if (sg->offset & 3 || sg->length & 3)
468 if (data->flags & MMC_DATA_READ)
469 direction = RK29_DMASRC_HW;
471 direction = RK29_DMASRC_MEM;
472 rk29_dma_devconfig(host->dma_chn, direction, (unsigned long )(host->dma_addr));
473 dma_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
474 (data->flags & MMC_DATA_READ)? DMA_FROM_DEVICE : DMA_TO_DEVICE);
475 for (i = 0; i < dma_len; i++)
476 rk29_dma_enqueue(host->dma_chn, host, sg_dma_address(&data->sg[i]),sg_dma_len(&data->sg[i])); // data->sg->dma_address, data->sg->length);
477 rk29_sdmmc_write(host->regs, SDMMC_CTRL, (rk29_sdmmc_read(host->regs, SDMMC_CTRL))|SDMMC_CTRL_DMA_ENABLE);// enable dma
478 rk29_dma_ctrl(host->dma_chn, RK29_DMAOP_START);
482 static void rk29_sdmmc_submit_data(struct rk29_sdmmc *host, struct mmc_data *data)
484 data->error = -EINPROGRESS;
490 if (rk29_sdmmc_submit_data_dma(host, data)) {
492 host->pio_offset = 0;
493 if (data->flags & MMC_DATA_READ)
494 host->dir_status = RK29_SDMMC_RECV_STATUS;
496 host->dir_status = RK29_SDMMC_SEND_STATUS;
498 rk29_sdmmc_write(host->regs, SDMMC_CTRL, (rk29_sdmmc_read(host->regs, SDMMC_CTRL))&(~SDMMC_CTRL_DMA_ENABLE));
503 static void sdmmc_send_cmd(struct rk29_sdmmc *host, unsigned int cmd, int arg)
507 rk29_sdmmc_write(host->regs, SDMMC_CMDARG, arg);
508 rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_START | cmd);
509 while (--tmo && readl(host->regs + SDMMC_CMD) & SDMMC_CMD_START);
511 printk("%s %d set cmd register timeout error!!!\n",__FUNCTION__,__LINE__);
515 void rk29_sdmmc_setup_bus(struct rk29_sdmmc *host)
519 if (host->clock != host->current_speed) {
520 div = (((host->bus_hz + (host->bus_hz / 5)) / host->clock)) >> 1;
522 /* store the actual clock for calculations */
523 host->clock = (host->bus_hz / div) >> 1;
525 rk29_sdmmc_write(host->regs, SDMMC_CLKENA, 0);
526 rk29_sdmmc_write(host->regs, SDMMC_CLKSRC,0);
528 sdmmc_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
529 /* set clock to desired speed */
530 rk29_sdmmc_write(host->regs, SDMMC_CLKDIV, div);
532 sdmmc_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
534 rk29_sdmmc_write(host->regs, SDMMC_CLKENA, SDMMC_CLKEN_ENABLE);
536 sdmmc_send_cmd(host, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
538 host->current_speed = host->clock;
541 /* Set the current bus width */
542 rk29_sdmmc_write(host->regs, SDMMC_CTYPE, host->ctype);
545 static void rk29_sdmmc_start_request(struct rk29_sdmmc *host)
547 struct mmc_request *mrq;
548 struct mmc_command *cmd;
549 struct mmc_data *data;
551 int time_out=100, time_out2=3;
555 /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/
556 while(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) {
561 local_irq_save(flags);
562 rk29_sdmmc_write( host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
563 /* wait till resets clear */
564 while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
565 local_irq_restore(flags);
572 /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/
573 if(!(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) {
574 local_irq_save(flags);
575 rk29_sdmmc_write(host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
576 /* wait till resets clear */
577 while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
578 local_irq_restore(flags);
580 /* Slot specific timing and width adjustment */
581 rk29_sdmmc_setup_bus(host);
582 host->curr_mrq = mrq;
583 host->pending_events = 0;
584 host->completed_events = 0;
585 host->data_status = 0;
588 rk29_sdmmc_set_timeout(host,data);
589 rk29_sdmmc_write(host->regs, SDMMC_BYTCNT,data->blksz*data->blocks);
590 rk29_sdmmc_write(host->regs, SDMMC_BLKSIZ,data->blksz);
593 cmdflags = rk29_sdmmc_prepare_command(host->mmc, cmd);
594 if (unlikely(test_and_clear_bit(RK29_SDMMC_CARD_NEED_INIT, &host->flags)))
595 cmdflags |= SDMMC_CMD_INIT; //this is the first command, let set send the initializtion clock
597 if (data) //we may need to move this code to mci_start_command
598 rk29_sdmmc_submit_data(host, data);
600 rk29_sdmmc_start_command(host, cmd, cmdflags);
603 host->stop_cmdr = rk29_sdmmc_prepare_command(host->mmc, mrq->stop);
607 static void rk29_sdmmc_queue_request(struct rk29_sdmmc *host,struct mmc_request *mrq)
609 spin_lock(&host->lock);
611 if (host->state == STATE_IDLE) {
612 host->state = STATE_SENDING_CMD;
613 rk29_sdmmc_start_request(host);
615 list_add_tail(&host->queue_node, &host->queue);
617 spin_unlock(&host->lock);
620 static void rk29_sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
622 struct rk29_sdmmc *host = mmc_priv(mmc);
626 if (!test_bit(RK29_SDMMC_CARD_PRESENT, &host->flags)) {
627 mrq->cmd->error = -ENOMEDIUM;
628 mmc_request_done(mmc, mrq);
632 rk29_sdmmc_queue_request(host,mrq);
635 static void rk29_sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
637 struct rk29_sdmmc *host = mmc_priv(mmc);;
639 host->ctype = 0; // set default 1 bit mode
641 switch (ios->bus_width) {
642 case MMC_BUS_WIDTH_1:
645 case MMC_BUS_WIDTH_4:
646 host->ctype = SDMMC_CTYPE_4BIT;
650 spin_lock(&host->lock);
652 * Use mirror of ios->clock to prevent race with mmc
653 * core ios update when finding the minimum.
655 host->clock = ios->clock;
657 spin_unlock(&host->lock);
659 spin_lock(&host->lock);
661 spin_unlock(&host->lock);
663 switch (ios->power_mode) {
665 set_bit(RK29_SDMMC_CARD_NEED_INIT, &host->flags);
666 rk29_sdmmc_write(host->regs, SDMMC_PWREN, 1);
673 static int rk29_sdmmc_get_ro(struct mmc_host *mmc)
675 struct rk29_sdmmc *host = mmc_priv(mmc);
676 u32 wrtprt = rk29_sdmmc_read(host->regs, SDMMC_WRTPRT);
678 return (wrtprt & SDMMC_WRITE_PROTECT)?1:0;
682 static int rk29_sdmmc_get_cd(struct mmc_host *mmc)
684 struct rk29_sdmmc *host = mmc_priv(mmc);
685 u32 cdetect = rk29_sdmmc_read(host->regs, SDMMC_CDETECT);
686 return (cdetect & SDMMC_CARD_DETECT_N)?0:1;
689 static void rk29_sdmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
693 struct rk29_sdmmc *host = mmc_priv(mmc);
695 spin_lock_irqsave(&host->lock, flags);
696 intmask = rk29_sdmmc_read(host->regs, SDMMC_INTMASK);
698 rk29_sdmmc_write(host->regs, SDMMC_INTMASK, intmask | SDMMC_INT_SDIO);
700 rk29_sdmmc_write(host->regs, SDMMC_INTMASK, intmask & ~SDMMC_INT_SDIO);
701 spin_unlock_irqrestore(&host->lock, flags);
704 static const struct mmc_host_ops rk29_sdmmc_ops[] = {
706 .request = rk29_sdmmc_request,
707 .set_ios = rk29_sdmmc_set_ios,
708 .get_ro = rk29_sdmmc_get_ro,
709 .get_cd = rk29_sdmmc_get_cd,
712 .request = rk29_sdmmc_request,
713 .set_ios = rk29_sdmmc_set_ios,
714 .enable_sdio_irq = rk29_sdmmc_enable_sdio_irq,
718 static void rk29_sdmmc_request_end(struct rk29_sdmmc *host, struct mmc_request *mrq)
719 __releases(&host->lock)
720 __acquires(&host->lock)
722 struct mmc_host *prev_mmc = host->mmc;
724 int time_out=100, time_out2=3;
726 WARN_ON(host->cmd || host->data);
727 host->curr_mrq = NULL;
729 /*µÈ´ýÇ°Ãæ´«Êä´¦ÀíÍê³É*/
730 while(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & (SDMMC_STAUTS_DATA_BUSY)) {
735 local_irq_save(flags);
736 rk29_sdmmc_write( host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
737 /* wait till resets clear */
738 while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
739 local_irq_restore(flags);
745 /*¼ì²éFIFO,Èç¹û²»Îª¿Õ£¬Çå¿Õ*/
746 if(!(rk29_sdmmc_read(host->regs, SDMMC_STATUS) & SDMMC_STAUTS_FIFO_EMPTY)) {
747 local_irq_save(flags);
748 rk29_sdmmc_write(host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | ( SDMMC_CTRL_FIFO_RESET ));
749 /* wait till resets clear */
750 while (readl(host->regs + SDMMC_CTRL) & ( SDMMC_CTRL_FIFO_RESET));
751 local_irq_restore(flags);
753 if (!list_empty(&host->queue)) {
754 host = list_entry(host->queue.next,
755 struct rk29_sdmmc, queue_node);
756 list_del(&host->queue_node);
757 host->state = STATE_SENDING_CMD;
758 rk29_sdmmc_start_request(host);
760 dev_vdbg(&host->pdev->dev, "list empty\n");
761 host->state = STATE_IDLE;
764 spin_unlock(&host->lock);
765 mmc_request_done(prev_mmc, mrq);
767 spin_lock(&host->lock);
770 static void rk29_sdmmc_command_complete(struct rk29_sdmmc *host,
771 struct mmc_command *cmd)
773 u32 status = host->cmd_status;
775 host->cmd_status = 0;
777 if(cmd->flags & MMC_RSP_PRESENT) {
779 if(cmd->flags & MMC_RSP_136) {
781 /* Read the response from the card (up to 16 bytes).
782 * RK29 SDMMC controller saves bits 127-96 in SDMMC_RESP3
783 * for easy parsing. But the UNSTUFF_BITS macro in core/mmc.c
784 * core/sd.c expect those bits be in resp[0]. Hence
785 * reverse the response word order.
787 cmd->resp[3] = rk29_sdmmc_read(host->regs, SDMMC_RESP0);
788 cmd->resp[2] = rk29_sdmmc_read(host->regs, SDMMC_RESP1);
789 cmd->resp[1] = rk29_sdmmc_read(host->regs, SDMMC_RESP2);
790 cmd->resp[0] = rk29_sdmmc_read(host->regs, SDMMC_RESP3);
792 cmd->resp[0] = rk29_sdmmc_read(host->regs, SDMMC_RESP0);
799 if (status & SDMMC_INT_RTO)
800 cmd->error = -ETIMEDOUT;
801 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
802 cmd->error = -EILSEQ;
803 else if (status & SDMMC_INT_RE)
809 dev_vdbg(&host->pdev->dev,
810 "command error: status=0x%08x resp=0x%08x\n"
811 "cmd=0x%08x arg=0x%08x flg=0x%08x err=%d\n",
812 status, cmd->resp[0],
813 cmd->opcode, cmd->arg, cmd->flags, cmd->error);
817 rk29_sdmmc_stop_dma(host);
822 static void rk29_sdmmc_tasklet_func(unsigned long priv)
824 struct rk29_sdmmc *host = (struct rk29_sdmmc *)priv;
825 struct mmc_request *mrq = host->curr_mrq;
826 struct mmc_data *data = host->data;
827 struct mmc_command *cmd = host->cmd;
828 enum rk29_sdmmc_state state = host->state;
829 enum rk29_sdmmc_state prev_state;
832 spin_lock(&host->lock);
843 case STATE_SENDING_CMD:
844 if (!rk29_sdmmc_test_and_clear_pending(host,
849 rk29_sdmmc_set_completed(host, EVENT_CMD_COMPLETE);
850 rk29_sdmmc_command_complete(host, mrq->cmd);
851 if (!mrq->data || cmd->error) {
852 rk29_sdmmc_request_end(host, host->curr_mrq);
856 prev_state = state = STATE_SENDING_DATA;
859 case STATE_SENDING_DATA:
860 if (rk29_sdmmc_test_and_clear_pending(host,
862 rk29_sdmmc_stop_dma(host);
864 send_stop_cmd(host, data);
865 state = STATE_DATA_ERROR;
869 if (!rk29_sdmmc_test_and_clear_pending(host,
870 EVENT_XFER_COMPLETE))
873 rk29_sdmmc_set_completed(host, EVENT_XFER_COMPLETE);
874 prev_state = state = STATE_DATA_BUSY;
877 case STATE_DATA_BUSY:
878 if (!rk29_sdmmc_test_and_clear_pending(host,
879 EVENT_DATA_COMPLETE))
882 rk29_sdmmc_set_completed(host, EVENT_DATA_COMPLETE);
883 status = host->data_status;
884 if (unlikely(status & RK29_SDMMC_DATA_ERROR_FLAGS)) {
885 if (status & SDMMC_INT_DRTO) {
886 dev_err(&host->pdev->dev,
887 "data timeout error\n");
888 data->error = -ETIMEDOUT;
889 } else if (status & SDMMC_INT_DCRC) {
890 dev_err(&host->pdev->dev,
892 data->error = -EILSEQ;
894 dev_err(&host->pdev->dev,
895 "data FIFO error (status=%08x)\n",
901 data->bytes_xfered = data->blocks * data->blksz;
906 rk29_sdmmc_request_end(host, host->curr_mrq);
910 prev_state = state = STATE_SENDING_STOP;
912 send_stop_cmd(host, data);
915 case STATE_SENDING_STOP:
916 if (!rk29_sdmmc_test_and_clear_pending(host,
921 rk29_sdmmc_command_complete(host, mrq->stop);
922 rk29_sdmmc_request_end(host, host->curr_mrq);
924 case STATE_DATA_ERROR:
925 if (!rk29_sdmmc_test_and_clear_pending(host,
926 EVENT_XFER_COMPLETE))
929 state = STATE_DATA_BUSY;
932 } while (state != prev_state);
937 spin_unlock(&host->lock);
943 inline static void rk29_sdmmc_push_data(struct rk29_sdmmc *host, void *buf,int cnt)
945 u32* pData = (u32*)buf;
952 rk29_sdmmc_write(host->regs, SDMMC_DATA,*pData++);
957 inline static void rk29_sdmmc_pull_data(struct rk29_sdmmc *host,void *buf,int cnt)
959 u32* pData = (u32*)buf;
966 *pData++ = rk29_sdmmc_read(host->regs, SDMMC_DATA);
971 static void rk29_sdmmc_read_data_pio(struct rk29_sdmmc *host)
973 struct scatterlist *sg = host->sg;
974 void *buf = sg_virt(sg);
975 unsigned int offset = host->pio_offset;
976 struct mmc_data *data = host->data;
978 unsigned int nbytes = 0,len,old_len,count =0;
981 len = SDMMC_GET_FCNT(rk29_sdmmc_read(host->regs, SDMMC_STATUS)) << 2;
984 if (likely(offset + len <= sg->length)) {
985 rk29_sdmmc_pull_data(host, (void *)(buf + offset),len);
990 if (offset == sg->length) {
991 flush_dcache_page(sg_page(sg));
992 host->sg = sg = sg_next(sg);
999 unsigned int remaining = sg->length - offset;
1000 rk29_sdmmc_pull_data(host, (void *)(buf + offset),remaining);
1001 nbytes += remaining;
1003 flush_dcache_page(sg_page(sg));
1004 host->sg = sg = sg_next(sg);
1007 offset = len - remaining;
1009 rk29_sdmmc_pull_data(host, buf,offset);
1013 status = rk29_sdmmc_read(host->regs, SDMMC_MINTSTS);
1014 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_RXDR); // clear RXDR interrupt
1015 if (status & RK29_SDMMC_DATA_ERROR_FLAGS) {
1016 host->data_status = status;
1017 data->bytes_xfered += nbytes;
1019 rk29_sdmmc_set_pending(host, EVENT_DATA_ERROR);
1020 tasklet_schedule(&host->tasklet);
1024 } while (status & SDMMC_INT_RXDR); // if the RXDR is ready let read again
1025 len = SDMMC_GET_FCNT(rk29_sdmmc_read(host->regs, SDMMC_STATUS));
1026 host->pio_offset = offset;
1027 data->bytes_xfered += nbytes;
1031 data->bytes_xfered += nbytes;
1033 rk29_sdmmc_set_pending(host, EVENT_XFER_COMPLETE);
1036 static void rk29_sdmmc_write_data_pio(struct rk29_sdmmc *host)
1038 struct scatterlist *sg = host->sg;
1039 void *buf = sg_virt(sg);
1040 unsigned int offset = host->pio_offset;
1041 struct mmc_data *data = host->data;
1043 unsigned int nbytes = 0,len;
1047 len = SDMMC_FIFO_SZ - (SDMMC_GET_FCNT(rk29_sdmmc_read(host->regs, SDMMC_STATUS)) << 2);
1048 if (likely(offset + len <= sg->length)) {
1049 rk29_sdmmc_push_data(host, (void *)(buf + offset),len);
1053 if (offset == sg->length) {
1054 host->sg = sg = sg_next(sg);
1062 unsigned int remaining = sg->length - offset;
1063 rk29_sdmmc_push_data(host, (void *)(buf + offset), remaining);
1064 nbytes += remaining;
1066 host->sg = sg = sg_next(sg);
1071 offset = len - remaining;
1073 rk29_sdmmc_push_data(host, (void *)buf, offset);
1077 status = rk29_sdmmc_read(host->regs, SDMMC_MINTSTS);
1078 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_TXDR); // clear RXDR interrupt
1079 if (status & RK29_SDMMC_DATA_ERROR_FLAGS) {
1080 host->data_status = status;
1081 data->bytes_xfered += nbytes;
1083 rk29_sdmmc_set_pending(host, EVENT_DATA_ERROR);
1084 tasklet_schedule(&host->tasklet);
1087 } while (status & SDMMC_INT_TXDR); // if TXDR, let write again
1089 host->pio_offset = offset;
1090 data->bytes_xfered += nbytes;
1095 data->bytes_xfered += nbytes;
1097 rk29_sdmmc_set_pending(host, EVENT_XFER_COMPLETE);
1100 static void rk29_sdmmc_cmd_interrupt(struct rk29_sdmmc *host, u32 status)
1102 if(!host->cmd_status)
1103 host->cmd_status = status;
1106 rk29_sdmmc_set_pending(host, EVENT_CMD_COMPLETE);
1107 tasklet_schedule(&host->tasklet);
1111 static int rk29_sdmmc1_card_get_cd(struct mmc_host *mmc)
1113 struct rk29_sdmmc *host = mmc_priv(mmc);
1114 struct rk29_sdmmc_platform_data *pdata = host->pdev->dev.platform_data;
1115 return gpio_get_value(pdata->detect_irq);
1118 static int rk29_sdmmc1_card_change_cd_trigger_type(struct mmc_host *mmc, unsigned int type)
1120 struct rk29_sdmmc *host = mmc_priv(mmc);
1121 struct rk29_sdmmc_platform_data *pdata = host->pdev->dev.platform_data;
1122 return set_irq_type(gpio_to_irq(pdata->detect_irq), type);
1126 static irqreturn_t rk29_sdmmc1_card_detect_interrupt(int irq, void *dev_id)
1128 struct rk29_sdmmc *host = dev_id;
1129 bool present, present_old;
1131 present = rk29_sdmmc1_card_get_cd(host->mmc);
1132 present_old = test_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1133 if (present != present_old) {
1135 set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1137 clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1139 mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(200));
1141 rk29_sdmmc1_card_change_cd_trigger_type(host->mmc, (present ? IRQF_TRIGGER_FALLING: IRQF_TRIGGER_RISING));
1148 static irqreturn_t rk29_sdmmc_interrupt(int irq, void *dev_id)
1150 struct rk29_sdmmc *host = dev_id;
1151 u32 status, pending;
1152 unsigned int pass_count = 0;
1156 spin_lock(&host->lock);
1158 status = rk29_sdmmc_read(host->regs, SDMMC_RINTSTS);
1159 pending = rk29_sdmmc_read(host->regs, SDMMC_MINTSTS);// read only mask reg
1162 if(pending & SDMMC_INT_CD) {
1163 writel(SDMMC_INT_CD, host->regs + SDMMC_RINTSTS); // clear sd detect int
1164 present = rk29_sdmmc_get_cd(host->mmc);
1165 present_old = test_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1166 if(present != present_old) {
1168 set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1170 clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1172 mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
1175 if(pending & RK29_SDMMC_CMD_ERROR_FLAGS) {
1176 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,RK29_SDMMC_CMD_ERROR_FLAGS); // clear interrupt
1177 host->cmd_status = status;
1179 rk29_sdmmc_set_pending(host, EVENT_CMD_COMPLETE);
1180 tasklet_schedule(&host->tasklet);
1183 if (pending & RK29_SDMMC_DATA_ERROR_FLAGS) { // if there is an error, let report DATA_ERROR
1184 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,RK29_SDMMC_DATA_ERROR_FLAGS); // clear interrupt
1185 host->data_status = status;
1187 rk29_sdmmc_set_pending(host, EVENT_DATA_ERROR);
1188 tasklet_schedule(&host->tasklet);
1192 if(pending & SDMMC_INT_DTO) {
1193 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_DTO); // clear interrupt
1194 if (!host->data_status)
1195 host->data_status = status;
1197 if(host->dir_status == RK29_SDMMC_RECV_STATUS) {
1198 if(host->sg != NULL)
1199 rk29_sdmmc_read_data_pio(host);
1201 rk29_sdmmc_set_pending(host, EVENT_DATA_COMPLETE);
1202 tasklet_schedule(&host->tasklet);
1205 if (pending & SDMMC_INT_RXDR) {
1206 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_RXDR); // clear interrupt
1208 rk29_sdmmc_read_data_pio(host);
1211 if (pending & SDMMC_INT_TXDR) {
1212 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_TXDR); // clear interrupt
1214 rk29_sdmmc_write_data_pio(host);
1218 if (pending & SDMMC_INT_CMD_DONE) {
1219 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_CMD_DONE); // clear interrupt
1220 rk29_sdmmc_cmd_interrupt(host, status);
1222 if(pending & SDMMC_INT_SDIO) {
1223 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS,SDMMC_INT_SDIO);
1224 mmc_signal_sdio_irq(host->mmc);
1226 } while (pass_count++ < 5);
1227 spin_unlock(&host->lock);
1228 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1233 * MMC card detect thread, kicked off from detect interrupt, 1 timer
1236 static void rk29_sdmmc_detect_change(unsigned long data)
1238 struct mmc_request *mrq;
1239 struct rk29_sdmmc *host = (struct rk29_sdmmc *)data;;
1242 if (test_bit(RK29_SDMMC_SHUTDOWN, &host->flags))
1244 spin_lock(&host->lock);
1245 /* Clean up queue if present */
1248 if (mrq == host->curr_mrq) {
1249 /* reset all blocks */
1250 rk29_sdmmc_write(host->regs, SDMMC_CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
1251 /* wait till resets clear */
1252 while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
1253 /* FIFO threshold settings */
1254 rk29_sdmmc_write(host->regs, SDMMC_FIFOTH, ((0x3 << 28) | (0x0f << 16) | (0x10 << 0))); // RXMark = 15, TXMark = 16, DMA Size = 16
1255 rk29_sdmmc_write(host->regs, SDMMC_PWREN, 1);
1256 rk29_sdmmc_write(host->regs, SDMMC_CTRL, rk29_sdmmc_read(host->regs, SDMMC_CTRL) | SDMMC_CTRL_INT_ENABLE);
1260 switch (host->state) {
1263 case STATE_SENDING_CMD:
1264 mrq->cmd->error = -ENOMEDIUM;
1268 case STATE_SENDING_DATA:
1269 mrq->data->error = -ENOMEDIUM;
1270 rk29_sdmmc_stop_dma(host);
1272 case STATE_DATA_BUSY:
1273 case STATE_DATA_ERROR:
1274 if (mrq->data->error == -EINPROGRESS)
1275 mrq->data->error = -ENOMEDIUM;
1279 case STATE_SENDING_STOP:
1280 mrq->stop->error = -ENOMEDIUM;
1284 rk29_sdmmc_request_end(host, mrq);
1286 list_del(&host->queue_node);
1287 mrq->cmd->error = -ENOMEDIUM;
1289 mrq->data->error = -ENOMEDIUM;
1291 mrq->stop->error = -ENOMEDIUM;
1292 spin_unlock(&host->lock);
1293 mmc_request_done(host->mmc, mrq);
1294 spin_lock(&host->lock);
1297 spin_unlock(&host->lock);
1298 mmc_detect_change(host->mmc, 0);
1301 static void rk29_sdmmc1_check_status(unsigned long data)
1303 struct rk29_sdmmc *host = (struct rk29_sdmmc *)data;
1304 struct rk29_sdmmc_platform_data *pdata = host->pdev->dev.platform_data;
1305 unsigned int status;
1307 status = pdata->status(mmc_dev(host->mmc));
1309 if (status ^ host->oldstatus)
1311 pr_info("%s: slot status change detected(%d-%d)\n",mmc_hostname(host->mmc), host->oldstatus, status);
1313 set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1314 mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(200));
1317 clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1318 rk29_sdmmc_detect_change((unsigned long)host);
1322 host->oldstatus = status;
1325 static void rk29_sdmmc1_status_notify_cb(int card_present, void *dev_id)
1327 struct rk29_sdmmc *host = dev_id;
1328 printk(KERN_INFO "%s, card_present %d\n", mmc_hostname(host->mmc), card_present);
1329 rk29_sdmmc1_check_status((unsigned long)host);
1332 static int rk29_sdmmc_probe(struct platform_device *pdev)
1334 struct mmc_host *mmc;
1335 struct rk29_sdmmc *host;
1336 struct resource *regs;
1337 struct rk29_sdmmc_platform_data *pdata;
1341 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1345 irq = platform_get_irq(pdev, 0);
1348 mmc = mmc_alloc_host(sizeof(struct rk29_sdmmc), &pdev->dev);
1351 host = mmc_priv(mmc);
1354 pdata = pdev->dev.platform_data;
1356 dev_err(&pdev->dev, "Platform data missing\n");
1362 spin_lock_init(&host->lock);
1363 INIT_LIST_HEAD(&host->queue);
1365 host->regs = ioremap(regs->start, regs->end - regs->start);
1368 memcpy(host->dma_name, pdata->dma_name, 8);
1369 host->use_dma = pdata->use_dma;
1371 if(strncmp(host->dma_name, "sdio", strlen("sdio")) == 0){
1372 rk29_dma_request(DMACH_SDIO, &rk29_dma_sdio1_client, NULL);
1373 host->dma_chn = DMACH_SDIO;
1375 if(strncmp(host->dma_name, "sd_mmc", strlen("sd_mmc")) == 0){
1376 rk29_dma_request(DMACH_SDMMC, &rk29_dma_sdmmc0_client, NULL);
1377 host->dma_chn = DMACH_SDMMC;
1379 rk29_dma_config(host->dma_chn, 16);
1380 rk29_dma_set_buffdone_fn(host->dma_chn, rk29_sdmmc_dma_complete);
1381 host->dma_addr = regs->start + SDMMC_DATA;
1383 host->clk = clk_get(&pdev->dev, "sdmmc");
1384 clk_set_rate(host->clk,52000000);
1385 clk_enable(host->clk);
1386 clk_enable(clk_get(&pdev->dev, "sdmmc_ahb"));
1387 host->bus_hz = clk_get_rate(host->clk); ///40000000; ////cgu_get_clk_freq(CGU_SB_SD_MMC_CCLK_IN_ID);
1389 /* reset all blocks */
1390 rk29_sdmmc_write(host->regs, SDMMC_CTRL,(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
1391 /* wait till resets clear */
1392 while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
1393 /* Clear the interrupts for the host controller */
1394 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS, 0xFFFFFFFF);
1395 rk29_sdmmc_write(host->regs, SDMMC_INTMASK, 0); // disable all mmc interrupt first
1396 /* Put in max timeout */
1397 rk29_sdmmc_write(host->regs, SDMMC_TMOUT, 0xFFFFFFFF);
1399 /* FIFO threshold settings */
1400 rk29_sdmmc_write(host->regs, SDMMC_FIFOTH, ((0x3 << 28) | (0x0f << 16) | (0x10 << 0))); // RXMark = 15, TXMark = 16, DMA Size = 16
1401 /* disable clock to CIU */
1402 rk29_sdmmc_write(host->regs, SDMMC_CLKENA,0);
1403 rk29_sdmmc_write(host->regs, SDMMC_CLKSRC,0);
1404 rk29_sdmmc_write(host->regs, SDMMC_PWREN, 1);
1405 tasklet_init(&host->tasklet, rk29_sdmmc_tasklet_func, (unsigned long)host);
1406 ret = request_irq(irq, rk29_sdmmc_interrupt, 0, dev_name(&pdev->dev), host);
1411 /* register sdmmc1 card detect interrupt route */
1412 if ((pdev->id == 1) && (pdata->detect_irq != 0)) {
1413 irq = gpio_to_irq(pdata->detect_irq);
1415 printk("%s: request gpio irq failed\n", __FUNCTION__);
1419 ret = request_irq(irq, rk29_sdmmc1_card_detect_interrupt, IRQF_TRIGGER_RISING, dev_name(&pdev->dev), host);
1421 printk("%s: sdmmc1 request detect interrupt failed\n", __FUNCTION__);
1427 /* setup sdmmc1 wifi card detect change */
1428 if (pdata->register_status_notify) {
1429 pdata->register_status_notify(rk29_sdmmc1_status_notify_cb, host);
1432 /* Assume card is present initially */
1433 if(rk29_sdmmc_get_cd(host->mmc))
1434 set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1436 clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1438 /* sdmmc1 wifi card slot status initially */
1439 if (pdata->status) {
1440 host->oldstatus = pdata->status(mmc_dev(host->mmc));
1441 if (host->oldstatus) {
1442 set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1444 clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
1448 platform_set_drvdata(pdev, host);
1449 mmc->ops = &rk29_sdmmc_ops[pdev->id];
1450 mmc->f_min = host->bus_hz/510;
1451 mmc->f_max = host->bus_hz/2; //2; ///20; //max f is clock to mmc_clk/2
1452 mmc->ocr_avail = pdata->host_ocr_avail;
1453 mmc->caps = pdata->host_caps;
1454 mmc->max_phys_segs = 64;
1455 mmc->max_hw_segs = 64;
1456 mmc->max_blk_size = 4095; //65536; /* SDMMC_BLKSIZ is 16 bits*/
1457 mmc->max_blk_count = 65535; ///512;
1458 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1459 mmc->max_seg_size = mmc->max_req_size;
1462 #if defined (CONFIG_DEBUG_FS)
1463 rk29_sdmmc_init_debugfs(host);
1465 /* Create card detect handler thread */
1466 setup_timer(&host->detect_timer, rk29_sdmmc_detect_change,(unsigned long)host);
1467 // enable interrupt for command done, data over, data empty, receive ready and error such as transmit, receive timeout, crc error
1468 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS, 0xFFFFFFFF);
1470 rk29_sdmmc_write(host->regs, SDMMC_INTMASK,SDMMC_INT_CMD_DONE | SDMMC_INT_DTO | RK29_SDMMC_ERROR_FLAGS | SDMMC_INT_CD);
1472 rk29_sdmmc_write(host->regs, SDMMC_INTMASK,SDMMC_INT_CMD_DONE | SDMMC_INT_DTO | SDMMC_INT_TXDR | SDMMC_INT_RXDR | RK29_SDMMC_ERROR_FLAGS | SDMMC_INT_CD);
1473 rk29_sdmmc_write(host->regs, SDMMC_CTRL,SDMMC_CTRL_INT_ENABLE); // enable mci interrupt
1474 rk29_sdmmc_write(host->regs, SDMMC_CLKENA,1);
1475 dev_info(&pdev->dev, "RK29 SDMMC controller at irq %d\n", irq);
1479 if(strncmp(host->dma_name, "sdio", strlen("sdio")) == 0)
1480 rk29_dma_free(DMACH_SDIO, &rk29_dma_sdio1_client);
1481 if(strncmp(host->dma_name, "sd_mmc", strlen("sd_mmc")) == 0)
1482 rk29_dma_free(DMACH_SDMMC, &rk29_dma_sdmmc0_client);
1485 iounmap(host->regs);
1493 static int __exit rk29_sdmmc_remove(struct platform_device *pdev)
1495 struct rk29_sdmmc *host = platform_get_drvdata(pdev);
1497 rk29_sdmmc_write(host->regs, SDMMC_RINTSTS, 0xFFFFFFFF);
1498 rk29_sdmmc_write(host->regs, SDMMC_INTMASK, 0); // disable all mmc interrupt first
1500 /* Shutdown detect IRQ and kill detect thread */
1501 del_timer_sync(&host->detect_timer);
1503 /* Debugfs stuff is cleaned up by mmc core */
1504 set_bit(RK29_SDMMC_SHUTDOWN, &host->flags);
1506 mmc_remove_host(host->mmc);
1507 mmc_free_host(host->mmc);
1509 /* disable clock to CIU */
1510 rk29_sdmmc_write(host->regs, SDMMC_CLKENA,0);
1511 rk29_sdmmc_write(host->regs, SDMMC_CLKSRC,0);
1513 free_irq(platform_get_irq(pdev, 0), host);
1515 if(strncmp(host->dma_name, "sdio", strlen("sdio")) == 0)
1516 rk29_dma_free(DMACH_SDIO, &rk29_dma_sdio1_client);
1517 if(strncmp(host->dma_name, "sd_mmc", strlen("sd_mmc")) == 0)
1518 rk29_dma_free(DMACH_SDMMC, &rk29_dma_sdmmc0_client);
1520 iounmap(host->regs);
1526 static int rk29_sdmmc_suspend(struct platform_device *pdev, pm_message_t state)
1529 struct rk29_sdmmc *host = platform_get_drvdata(pdev);
1530 rk29_sdmmc_write(host->regs, SDMMC_CLKENA, 0);
1531 clk_disable(host->clk);
1536 static int rk29_sdmmc_resume(struct platform_device *pdev)
1539 struct rk29_sdmmc *host = platform_get_drvdata(pdev);
1540 clk_enable(host->clk);
1545 static struct platform_driver rk29_sdmmc_driver = {
1546 .suspend = rk29_sdmmc_suspend,
1547 .resume = rk29_sdmmc_resume,
1548 .remove = __exit_p(rk29_sdmmc_remove),
1550 .name = "rk29_sdmmc",
1554 static int __init rk29_sdmmc_init(void)
1556 return platform_driver_probe(&rk29_sdmmc_driver, rk29_sdmmc_probe);
1559 static void __exit rk29_sdmmc_exit(void)
1561 platform_driver_unregister(&rk29_sdmmc_driver);
1564 module_init(rk29_sdmmc_init);
1565 module_exit(rk29_sdmmc_exit);
1567 MODULE_DESCRIPTION("Rk29 Multimedia Card Interface driver");
1568 MODULE_AUTHOR("Rockchips");
1569 MODULE_LICENSE("GPL v2");