2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * Copyright (C) 2014 - 2015 Fuzhou Rockchip Electronics Co.Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/blkdev.h>
17 #include <linux/clk.h>
18 #include <linux/debugfs.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmaengine.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <linux/stat.h>
31 #include <linux/delay.h>
32 #include <linux/irq.h>
33 #include <linux/suspend.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/mmc.h>
36 #include <linux/mmc/sd.h>
37 #include <linux/mmc/card.h>
38 #include <linux/mmc/sdio.h>
39 #include <linux/mmc/rk_mmc.h>
40 #include <linux/bitops.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/workqueue.h>
44 #include <linux/of_gpio.h>
45 #include <linux/mmc/slot-gpio.h>
46 #include <linux/clk-private.h>
47 #include <linux/rockchip/cpu.h>
48 #include <linux/rfkill-wlan.h>
49 #include <linux/mfd/syscon.h>
50 #include <linux/regmap.h>
51 #include <linux/log2.h>
53 #include "rk_sdmmc_dbg.h"
54 #include <linux/regulator/rockchip_io_vol_domain.h>
55 #include "../../clk/rockchip/clk-ops.h"
57 #define RK_SDMMC_DRIVER_VERSION "Ver 2.00 2015-06-10"
59 /* Common flag combinations */
60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
63 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
65 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
66 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
67 #define DW_MCI_SEND_STATUS 1
68 #define DW_MCI_RECV_STATUS 2
69 #define DW_MCI_DMA_THRESHOLD 16
70 #define DW_MCI_FREQ_MAX 50000000 /* unit: HZ */
71 #define DW_MCI_FREQ_MIN 300000 /* unit: HZ */
73 /* Max is 250ms showed in Spec */
74 #define SDMMC_DATA_TIMEOUT_SD 500
75 #define SDMMC_DATA_TIMEOUT_SDIO 250
76 #define SDMMC_DATA_TIMEOUT_EMMC 2500
77 #define SDMMC_CMD_RTO_MAX_HOLD 200
78 #define SDMMC_WAIT_FOR_UNBUSY 2500
80 #define DW_REGS_SIZE (0x0098 + 4)
81 #define DW_REGS_NUM (0x0098 / 4)
83 #ifdef CONFIG_MMC_DW_IDMAC
84 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
85 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
86 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
90 u32 des0; /* Control Descriptor */
91 #define IDMAC_DES0_DIC BIT(1)
92 #define IDMAC_DES0_LD BIT(2)
93 #define IDMAC_DES0_FD BIT(3)
94 #define IDMAC_DES0_CH BIT(4)
95 #define IDMAC_DES0_ER BIT(5)
96 #define IDMAC_DES0_CES BIT(30)
97 #define IDMAC_DES0_OWN BIT(31)
99 u32 des1; /* Buffer sizes */
100 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
101 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
103 u32 des2; /* buffer 1 physical address */
105 u32 des3; /* buffer 2 physical address */
107 #endif /* CONFIG_MMC_DW_IDMAC */
110 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
111 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
112 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
113 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
114 extern void rk_send_wakeup_key(void);
116 #if defined(CONFIG_DEBUG_FS)
117 static int dw_mci_req_show(struct seq_file *s, void *v)
119 struct dw_mci_slot *slot = s->private;
120 struct mmc_request *mrq;
121 struct mmc_command *cmd;
122 struct mmc_command *stop;
123 struct mmc_data *data;
125 /* Make sure we get a consistent snapshot */
126 spin_lock_bh(&slot->host->lock);
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 cmd->opcode, cmd->arg, cmd->flags,
138 cmd->resp[0], cmd->resp[1], cmd->resp[2],
139 cmd->resp[2], cmd->error);
141 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
142 data->bytes_xfered, data->blocks,
143 data->blksz, data->flags, data->error);
146 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
147 stop->opcode, stop->arg, stop->flags,
148 stop->resp[0], stop->resp[1], stop->resp[2],
149 stop->resp[2], stop->error);
152 spin_unlock_bh(&slot->host->lock);
157 static int dw_mci_req_open(struct inode *inode, struct file *file)
159 return single_open(file, dw_mci_req_show, inode->i_private);
162 static const struct file_operations dw_mci_req_fops = {
163 .owner = THIS_MODULE,
164 .open = dw_mci_req_open,
167 .release = single_release,
170 static int dw_mci_regs_show(struct seq_file *s, void *v)
172 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
173 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
174 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
175 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
176 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
177 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
184 return single_open(file, dw_mci_regs_show, inode->i_private);
187 static const struct file_operations dw_mci_regs_fops = {
188 .owner = THIS_MODULE,
189 .open = dw_mci_regs_open,
192 .release = single_release,
195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
197 struct mmc_host *mmc = slot->mmc;
198 struct dw_mci *host = slot->host;
202 root = mmc->debugfs_root;
206 node = debugfs_create_file("regs", S_IRUSR, root, host,
211 node = debugfs_create_file("req", S_IRUSR, root, slot,
216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
220 node = debugfs_create_x32("pending_events", S_IRUSR, root,
221 (u32 *)&host->pending_events);
225 node = debugfs_create_x32("completed_events", S_IRUSR, root,
226 (u32 *)&host->completed_events);
233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
235 #endif /* defined(CONFIG_DEBUG_FS) */
237 static void dw_mci_set_timeout(struct dw_mci *host)
239 /* timeout (maximum) */
240 mci_writel(host, TMOUT, 0xffffffff);
243 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
245 struct mmc_data *data;
246 struct dw_mci_slot *slot = mmc_priv(mmc);
247 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
249 cmd->error = -EINPROGRESS;
253 if (cmdr == MMC_STOP_TRANSMISSION)
254 cmdr |= SDMMC_CMD_STOP;
256 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
258 if (cmd->flags & MMC_RSP_PRESENT) {
259 /* We expect a response, so set this bit */
260 cmdr |= SDMMC_CMD_RESP_EXP;
261 if (cmd->flags & MMC_RSP_136)
262 cmdr |= SDMMC_CMD_RESP_LONG;
265 if (cmd->flags & MMC_RSP_CRC)
266 cmdr |= SDMMC_CMD_RESP_CRC;
270 cmdr |= SDMMC_CMD_DAT_EXP;
271 if (data->flags & MMC_DATA_STREAM)
272 cmdr |= SDMMC_CMD_STRM_MODE;
273 if (data->flags & MMC_DATA_WRITE)
274 cmdr |= SDMMC_CMD_DAT_WR;
277 if (drv_data && drv_data->prepare_command)
278 drv_data->prepare_command(slot->host, &cmdr);
283 static void dw_mci_start_command(struct dw_mci *host,
284 struct mmc_command *cmd, u32 cmd_flags)
286 struct dw_mci_slot *slot = host->slot[0];
288 host->pre_cmd = host->cmd;
291 "start command: ARGR=0x%08x CMDR=0x%08x\n",
292 cmd->arg, cmd_flags);
294 if(SD_SWITCH_VOLTAGE == cmd->opcode){
295 /*confirm non-low-power mode*/
296 mci_writel(host, CMDARG, 0);
297 dw_mci_disable_low_power(slot);
299 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
300 __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
302 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
305 mci_writel(host, CMDARG, cmd->arg);
308 /* Fix the value to 1 in current soc */
309 if(host->mmc->hold_reg_flag)
310 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
312 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
316 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
318 dw_mci_start_command(host, data->stop, host->stop_cmdr);
321 /* DMA interface functions */
322 static void dw_mci_stop_dma(struct dw_mci *host)
324 if (host->using_dma) {
325 /* Fixme: No need to terminate edma, may cause flush op */
326 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
327 host->dma_ops->stop(host);
328 host->dma_ops->cleanup(host);
331 /* Data transfer was stopped by the interrupt handler */
332 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
335 static int dw_mci_get_dma_dir(struct mmc_data *data)
337 if (data->flags & MMC_DATA_WRITE)
338 return DMA_TO_DEVICE;
340 return DMA_FROM_DEVICE;
343 #ifdef CONFIG_MMC_DW_IDMAC
344 static void dw_mci_dma_cleanup(struct dw_mci *host)
346 struct mmc_data *data = host->data;
349 if (!data->host_cookie)
350 dma_unmap_sg(host->dev,
353 dw_mci_get_dma_dir(data));
356 static void dw_mci_idmac_reset(struct dw_mci *host)
358 u32 bmod = mci_readl(host, BMOD);
359 /* Software reset of DMA */
360 bmod |= SDMMC_IDMAC_SWRESET;
361 mci_writel(host, BMOD, bmod);
364 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
368 /* Disable and reset the IDMAC interface */
369 temp = mci_readl(host, CTRL);
370 temp &= ~SDMMC_CTRL_USE_IDMAC;
371 temp |= SDMMC_CTRL_DMA_RESET;
372 mci_writel(host, CTRL, temp);
374 /* Stop the IDMAC running */
375 temp = mci_readl(host, BMOD);
376 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
377 temp |= SDMMC_IDMAC_SWRESET;
378 mci_writel(host, BMOD, temp);
381 static void dw_mci_idmac_complete_dma(void *arg)
383 struct dw_mci *host = arg;
384 struct mmc_data *data = host->data;
386 dev_vdbg(host->dev, "DMA complete\n");
388 host->dma_ops->cleanup(host);
391 * If the card was removed, data will be NULL. No point in trying to
392 * send the stop command or waiting for NBUSY in this case.
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
396 tasklet_schedule(&host->tasklet);
400 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
404 struct idmac_desc *desc = host->sg_cpu;
406 for (i = 0; i < sg_len; i++, desc++) {
407 unsigned int length = sg_dma_len(&data->sg[i]);
408 u32 mem_addr = sg_dma_address(&data->sg[i]);
410 /* Set the OWN bit and disable interrupts for this descriptor */
411 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
414 IDMAC_SET_BUFFER1_SIZE(desc, length);
416 /* Physical address to DMA to/from */
417 desc->des2 = mem_addr;
420 /* Set first descriptor */
422 desc->des0 |= IDMAC_DES0_FD;
424 /* Set last descriptor */
425 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
426 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
427 desc->des0 |= IDMAC_DES0_LD;
432 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
436 dw_mci_translate_sglist(host, host->data, sg_len);
438 /* Select IDMAC interface */
439 temp = mci_readl(host, CTRL);
440 temp |= SDMMC_CTRL_USE_IDMAC;
441 mci_writel(host, CTRL, temp);
445 /* Enable the IDMAC */
446 temp = mci_readl(host, BMOD);
447 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
448 mci_writel(host, BMOD, temp);
450 /* Start it running */
451 mci_writel(host, PLDMND, 1);
454 static int dw_mci_idmac_init(struct dw_mci *host)
456 struct idmac_desc *p;
459 /* Number of descriptors in the ring buffer */
460 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
462 /* Forward link the descriptor list */
463 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
464 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
467 /* Set the last descriptor as the end-of-ring descriptor */
468 p->des3 = host->sg_dma;
469 p->des0 = IDMAC_DES0_ER;
471 dw_mci_idmac_reset(host);
473 /* Mask out interrupts - get Tx & Rx complete only */
474 mci_writel(host, IDSTS, IDMAC_INT_CLR);
475 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
478 /* Set the descriptor base address */
479 mci_writel(host, DBADDR, host->sg_dma);
483 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
484 .init = dw_mci_idmac_init,
485 .start = dw_mci_idmac_start_dma,
486 .stop = dw_mci_idmac_stop_dma,
487 .complete = dw_mci_idmac_complete_dma,
488 .cleanup = dw_mci_dma_cleanup,
492 static void dw_mci_edma_cleanup(struct dw_mci *host)
494 struct mmc_data *data = host->data;
497 if (!data->host_cookie)
498 dma_unmap_sg(host->dev,
499 data->sg, data->sg_len,
500 dw_mci_get_dma_dir(data));
503 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
505 dmaengine_terminate_all(host->dms->ch);
508 static void dw_mci_edmac_complete_dma(void *arg)
510 struct dw_mci *host = arg;
511 struct mmc_data *data = host->data;
513 dev_vdbg(host->dev, "DMA complete\n");
516 if(data->flags & MMC_DATA_READ)
517 /* Invalidate cache after read */
518 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
519 data->sg_len, DMA_FROM_DEVICE);
521 host->dma_ops->cleanup(host);
524 * If the card was removed, data will be NULL. No point in trying to
525 * send the stop command or waiting for NBUSY in this case.
528 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
529 tasklet_schedule(&host->tasklet);
533 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
535 struct dma_slave_config slave_config;
536 struct dma_async_tx_descriptor *desc = NULL;
537 struct scatterlist *sgl = host->data->sg;
538 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
539 u32 sg_elems = host->data->sg_len;
540 u32 fifoth_val, mburst;
542 u32 idx, rx_wmark, tx_wmark;
545 /* Set external dma config: burst size, burst width*/
546 slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
547 slave_config.src_addr = slave_config.dst_addr;
548 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
549 slave_config.src_addr_width = slave_config.dst_addr_width;
551 /* Match FIFO dma burst MSIZE with external dma config*/
552 fifoth_val = mci_readl(host, FIFOTH);
553 mburst = mszs[(fifoth_val >> 28) & 0x7];
555 /* Edmac limit burst to 16, but work around for rk3036 to 8 */
556 if (unlikely(cpu_is_rk3036()))
561 if (mburst > burst_limit) {
562 mburst = burst_limit;
563 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
565 rx_wmark = mszs[idx] - 1;
566 tx_wmark = (host->fifo_depth) / 2;
567 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
569 mci_writel(host, FIFOTH, fifoth_val);
572 slave_config.dst_maxburst = mburst;
573 slave_config.src_maxburst = slave_config.dst_maxburst;
575 if(host->data->flags & MMC_DATA_WRITE){
576 slave_config.direction = DMA_MEM_TO_DEV;
577 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
580 "Error in dw_mci edmac write configuration.\n");
584 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
585 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
588 "Cannot prepare slave write sg the dw_mci edmac!\n");
592 /* Set dw_mci_edmac_complete_dma as callback */
593 desc->callback = dw_mci_edmac_complete_dma;
594 desc->callback_param = (void *)host;
595 dmaengine_submit(desc);
597 /* Flush cache before write */
598 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
599 sg_elems, DMA_TO_DEVICE);
600 dma_async_issue_pending(host->dms->ch);
603 slave_config.direction = DMA_DEV_TO_MEM;
604 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
607 "Error in dw_mci edmac read configuration.\n");
610 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
611 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
614 "Cannot prepare slave read sg for the dw_mci edmac!\n");
617 /* set dw_mci_edmac_complete_dma as callback */
618 desc->callback = dw_mci_edmac_complete_dma;
619 desc->callback_param = (void *)host;
620 dmaengine_submit(desc);
621 dma_async_issue_pending(host->dms->ch);
625 static int dw_mci_edmac_init(struct dw_mci *host)
629 /* Request external dma channel, SHOULD decide chn in dts */
631 host->dms = (struct dw_mci_dma_slave *)kzalloc
632 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
633 if (NULL == host->dms) {
634 dev_err(host->dev, "No enough memory to alloc dms.\n");
638 host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
639 if (!host->dms->ch) {
641 "Failed to get external DMA channel %d\n",
642 host->dms->ch->chan_id);
651 static void dw_mci_edmac_exit(struct dw_mci *host)
653 if (NULL != host->dms) {
654 if (NULL != host->dms->ch) {
655 dma_release_channel(host->dms->ch);
656 host->dms->ch = NULL;
663 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
664 .init = dw_mci_edmac_init,
665 .exit = dw_mci_edmac_exit,
666 .start = dw_mci_edmac_start_dma,
667 .stop = dw_mci_edmac_stop_dma,
668 .complete = dw_mci_edmac_complete_dma,
669 .cleanup = dw_mci_edma_cleanup,
671 #endif /* CONFIG_MMC_DW_IDMAC */
673 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
674 struct mmc_data *data,
677 struct scatterlist *sg;
678 unsigned int i, sg_len;
680 if (!next && data->host_cookie)
681 return data->host_cookie;
684 * We don't do DMA on "complex" transfers, i.e. with
685 * non-word-aligned buffers or lengths. Also, we don't bother
686 * with all the DMA setup overhead for short transfers.
688 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
694 for_each_sg(data->sg, sg, data->sg_len, i) {
695 if (sg->offset & 3 || sg->length & 3)
699 sg_len = dma_map_sg(host->dev,
702 dw_mci_get_dma_dir(data));
707 data->host_cookie = sg_len;
712 static void dw_mci_pre_req(struct mmc_host *mmc,
713 struct mmc_request *mrq,
716 struct dw_mci_slot *slot = mmc_priv(mmc);
717 struct mmc_data *data = mrq->data;
719 if (!slot->host->use_dma || !data)
722 if (data->host_cookie) {
723 data->host_cookie = 0;
727 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
728 data->host_cookie = 0;
731 static void dw_mci_post_req(struct mmc_host *mmc,
732 struct mmc_request *mrq,
735 struct dw_mci_slot *slot = mmc_priv(mmc);
736 struct mmc_data *data = mrq->data;
738 if (!slot->host->use_dma || !data)
741 if (data->host_cookie)
742 dma_unmap_sg(slot->host->dev,
745 dw_mci_get_dma_dir(data));
746 data->host_cookie = 0;
749 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
751 #ifdef CONFIG_MMC_DW_IDMAC
752 unsigned int blksz = data->blksz;
753 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
754 u32 fifo_width = 1 << host->data_shift;
755 u32 blksz_depth = blksz / fifo_width, fifoth_val;
756 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
757 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
759 tx_wmark = (host->fifo_depth) / 2;
760 tx_wmark_invers = host->fifo_depth - tx_wmark;
764 * if blksz is not a multiple of the FIFO width
766 if (blksz % fifo_width) {
773 if (!((blksz_depth % mszs[idx]) ||
774 (tx_wmark_invers % mszs[idx]))) {
776 rx_wmark = mszs[idx] - 1;
781 * If idx is '0', it won't be tried
782 * Thus, initial values are uesed
785 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
786 mci_writel(host, FIFOTH, fifoth_val);
791 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
793 unsigned int blksz = data->blksz;
794 u32 blksz_depth, fifo_depth;
797 WARN_ON(!(data->flags & MMC_DATA_READ));
799 if (host->timing != MMC_TIMING_MMC_HS200 &&
800 host->timing != MMC_TIMING_UHS_SDR104)
803 blksz_depth = blksz / (1 << host->data_shift);
804 fifo_depth = host->fifo_depth;
806 if (blksz_depth > fifo_depth)
810 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
811 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
812 * Currently just choose blksz.
815 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
819 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
822 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
830 /* If we don't have a channel, we can't do DMA */
834 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
836 /* Fixme: No need terminate edma, may cause flush op */
837 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
838 host->dma_ops->stop(host);
845 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
846 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
850 * Decide the MSIZE and RX/TX Watermark.
851 * If current block size is same with previous size,
852 * no need to update fifoth.
854 if (host->prev_blksz != data->blksz)
855 dw_mci_adjust_fifoth(host, data);
858 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
860 /* Enable the DMA interface */
861 temp = mci_readl(host, CTRL);
862 temp |= SDMMC_CTRL_DMA_ENABLE;
863 mci_writel(host, CTRL, temp);
865 /* Disable RX/TX IRQs, let DMA handle it */
866 spin_lock_irqsave(&host->slock, flags);
867 temp = mci_readl(host, INTMASK);
868 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
869 mci_writel(host, INTMASK, temp);
870 spin_unlock_irqrestore(&host->slock, flags);
872 host->dma_ops->start(host, sg_len);
877 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
882 data->error = -EINPROGRESS;
884 //WARN_ON(host->data);
889 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
891 if (data->flags & MMC_DATA_READ) {
892 host->dir_status = DW_MCI_RECV_STATUS;
893 dw_mci_ctrl_rd_thld(host, data);
895 host->dir_status = DW_MCI_SEND_STATUS;
898 MMC_DBG_INFO_FUNC(host->mmc,
899 "Dw_mci_submit_data, blocks = %d, blksz = %d [%s]",
900 data->blocks, data->blksz, mmc_hostname(host->mmc));
902 if (dw_mci_submit_data_dma(host, data)) {
903 int flags = SG_MITER_ATOMIC;
904 if (host->data->flags & MMC_DATA_READ)
905 flags |= SG_MITER_TO_SG;
907 flags |= SG_MITER_FROM_SG;
909 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
911 host->part_buf_start = 0;
912 host->part_buf_count = 0;
914 spin_lock_irqsave(&host->slock, flag);
915 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
916 temp = mci_readl(host, INTMASK);
917 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
918 mci_writel(host, INTMASK, temp);
919 spin_unlock_irqrestore(&host->slock, flag);
921 temp = mci_readl(host, CTRL);
922 temp &= ~SDMMC_CTRL_DMA_ENABLE;
923 mci_writel(host, CTRL, temp);
926 * Use the initial fifoth_val for PIO mode.
927 * If next issued data may be transfered by DMA mode,
928 * prev_blksz should be invalidated.
930 mci_writel(host, FIFOTH, host->fifoth_val);
931 host->prev_blksz = 0;
934 * Keep the current block size.
935 * It will be used to decide whether to update
936 * fifoth register next time.
938 host->prev_blksz = data->blksz;
942 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
944 struct dw_mci *host = slot->host;
945 unsigned long timeout = jiffies + msecs_to_jiffies(500);
946 unsigned int cmd_status = 0;
948 #ifdef SDMMC_WAIT_FOR_UNBUSY
950 timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
952 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
954 ret = time_before(jiffies, timeout);
955 cmd_status = mci_readl(host, STATUS);
957 (SDMMC_STAUTS_DATA_BUSY |
958 SDMMC_STAUTS_MC_BUSY)))
963 MMC_DBG_ERR_FUNC(host->mmc,
964 "mci_send_cmd: wait for unbusy timeout! [%s]",
965 mmc_hostname(host->mmc));
969 mci_writel(host, CMDARG, arg);
971 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
972 if(cmd & SDMMC_CMD_UPD_CLK)
973 timeout = jiffies + msecs_to_jiffies(50);
975 timeout = jiffies + msecs_to_jiffies(500);
977 while (time_before(jiffies, timeout)) {
978 cmd_status = mci_readl(host, CMD);
979 if (!(cmd_status & SDMMC_CMD_START))
983 dev_err(&slot->mmc->class_dev,
984 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
985 cmd, arg, cmd_status);
988 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
990 struct dw_mci *host = slot->host;
991 unsigned int tempck,clock = slot->clock;
996 MMC_DBG_INFO_FUNC(host->mmc,
997 "%s: clock=%d, current_speed=%d, bus_hz=%d, forc=%d[%s]\n",
998 __FUNCTION__, clock, host->current_speed, host->bus_hz,
999 force_clkinit, mmc_hostname(host->mmc));
1002 mci_writel(host, CLKENA, 0);
1003 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1004 if(host->svi_flags == 0)
1005 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1007 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1009 } else if (clock != host->current_speed || force_clkinit) {
1010 div = host->bus_hz / clock;
1011 if (host->bus_hz % clock && host->bus_hz > clock)
1013 * move the + 1 after the divide to prevent
1014 * over-clocking the card.
1018 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1020 if ((clock << div) != slot->__clk_old || force_clkinit) {
1021 tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1022 dev_info(&slot->mmc->class_dev,
1023 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1024 slot->id, host->bus_hz, clock,
1027 host->set_speed = tempck;
1028 host->set_div = div;
1032 mci_writel(host, CLKENA, 0);
1033 mci_writel(host, CLKSRC, 0);
1037 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1039 if(clock <= 400*1000){
1040 MMC_DBG_BOOT_FUNC(host->mmc,
1041 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1042 clock * 2, mmc_hostname(host->mmc));
1043 /* clk_mmc will change parents to 24MHz xtal*/
1044 clk_set_rate(host->clk_mmc, clock * 2);
1047 host->set_div = div;
1051 MMC_DBG_BOOT_FUNC(host->mmc,
1052 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1053 mmc_hostname(host->mmc));
1056 MMC_DBG_ERR_FUNC(host->mmc,
1057 "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1058 mmc_hostname(host->mmc));
1060 host->set_div = div;
1061 host->bus_hz = host->set_speed * 2;
1062 MMC_DBG_BOOT_FUNC(host->mmc,
1063 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1064 div, host->bus_hz, mmc_hostname(host->mmc));
1066 /* BUG may be here, come on, Linux BSP engineer looks!
1067 FIXME: HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1068 WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1069 some oops happened like that:
1070 mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1071 rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1072 rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1073 mmc0: new high speed DDR MMC card at address 0001
1074 mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1076 mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1077 mmcblk0: retrying using single block read
1078 mmcblk0: error -110 sending status command, retrying
1080 We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1083 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1084 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1087 host->set_div = div;
1088 host->bus_hz = host->set_speed * 2;
1089 MMC_DBG_BOOT_FUNC(host->mmc,
1090 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1091 div, host->bus_hz, mmc_hostname(host->mmc));
1094 if (host->verid < DW_MMC_240A)
1095 clk_set_rate(host->clk_mmc,(host->bus_hz));
1097 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1103 /* set clock to desired speed */
1104 mci_writel(host, CLKDIV, div);
1108 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1110 /* enable clock; only low power if no SDIO */
1111 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1113 if (host->verid < DW_MMC_240A)
1114 sdio_int = SDMMC_INT_SDIO(slot->id);
1116 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1118 if (!(mci_readl(host, INTMASK) & sdio_int))
1119 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1120 mci_writel(host, CLKENA, clk_en_a);
1124 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1125 /* keep the clock with reflecting clock dividor */
1126 slot->__clk_old = clock << div;
1129 host->current_speed = clock;
1131 if(slot->ctype != slot->pre_ctype)
1132 MMC_DBG_BOOT_FUNC(host->mmc,
1133 "Bus speed=%dHz,Bus width=%s.[%s]",
1135 (slot->ctype == SDMMC_CTYPE_4BIT) ? "4bits" : "8bits",
1136 mmc_hostname(host->mmc));
1138 slot->pre_ctype = slot->ctype;
1140 /* Set the current slot bus width */
1141 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1144 extern struct mmc_card *this_card;
1145 static void dw_mci_wait_unbusy(struct dw_mci *host)
1147 unsigned int timeout = SDMMC_DATA_TIMEOUT_SDIO;
1148 unsigned long time_loop;
1149 unsigned int status;
1150 unsigned int tmo = 300000;
1151 /* Secure erase flag */
1154 MMC_DBG_INFO_FUNC(host->mmc,
1155 "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1157 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1158 if (host->cmd && (host->cmd->opcode == MMC_ERASE) && this_card) {
1159 /* Special care for (secure)erase timeout calculation */
1160 if ((host->cmd->arg & (0x1 << 31)) == 1)
1163 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1165 (timeout = (this_card->ext_csd.hc_erase_timeout) *
1166 tmo * (this_card->ext_csd.sec_erase_mult)) :
1167 (timeout = (this_card->ext_csd.hc_erase_timeout) * tmo);
1170 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1171 timeout = SDMMC_DATA_TIMEOUT_EMMC;
1172 } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1173 timeout = SDMMC_DATA_TIMEOUT_SD;
1176 time_loop = jiffies + msecs_to_jiffies(timeout);
1178 status = mci_readl(host, STATUS);
1179 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1181 } while (time_before(jiffies, time_loop));
1184 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1187 * 0--status is busy.
1188 * 1--status is unbusy.
1190 int dw_mci_card_busy(struct mmc_host *mmc)
1192 struct dw_mci_slot *slot = mmc_priv(mmc);
1193 struct dw_mci *host = slot->host;
1195 MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1196 host->svi_flags, mmc_hostname(host->mmc));
1199 if(host->svi_flags == 0){
1201 host->svi_flags = 1;
1202 return host->svi_flags;
1205 host->svi_flags = 0;
1206 return host->svi_flags;
1212 static void __dw_mci_start_request(struct dw_mci *host,
1213 struct dw_mci_slot *slot,
1214 struct mmc_command *cmd)
1216 struct mmc_request *mrq;
1217 struct mmc_data *data;
1221 if (host->pdata->select_slot)
1222 host->pdata->select_slot(slot->id);
1224 host->cur_slot = slot;
1227 dw_mci_wait_unbusy(host);
1229 host->pending_events = 0;
1230 host->completed_events = 0;
1231 host->data_status = 0;
1235 dw_mci_set_timeout(host);
1236 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1237 mci_writel(host, BLKSIZ, data->blksz);
1240 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1242 /* this is the first command, send the initialization clock */
1243 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1244 cmdflags |= SDMMC_CMD_INIT;
1247 dw_mci_submit_data(host, data);
1251 dw_mci_start_command(host, cmd, cmdflags);
1254 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1257 static void dw_mci_start_request(struct dw_mci *host,
1258 struct dw_mci_slot *slot)
1260 struct mmc_request *mrq = slot->mrq;
1261 struct mmc_command *cmd;
1263 MMC_DBG_INFO_FUNC(host->mmc,
1264 " Begin to start the new request. cmd=%d(arg=0x%x)[%s]",
1265 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1267 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1268 __dw_mci_start_request(host, slot, cmd);
1271 /* must be called with host->lock held */
1272 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1273 struct mmc_request *mrq)
1275 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1280 if (host->state == STATE_IDLE) {
1281 host->state = STATE_SENDING_CMD;
1282 dw_mci_start_request(host, slot);
1284 list_add_tail(&slot->queue_node, &host->queue);
1288 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1290 struct dw_mci_slot *slot = mmc_priv(mmc);
1291 struct dw_mci *host = slot->host;
1296 * The check for card presence and queueing of the request must be
1297 * atomic, otherwise the card could be removed in between and the
1298 * request wouldn't fail until another card was inserted.
1300 spin_lock_bh(&host->lock);
1302 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1303 spin_unlock_bh(&host->lock);
1304 mrq->cmd->error = -ENOMEDIUM;
1305 MMC_DBG_CMD_FUNC(host->mmc, "%s: no card,so reqeuest done, cmd=%d [%s]",
1306 __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1308 mmc_request_done(mmc, mrq);
1312 MMC_DBG_CMD_FUNC(host->mmc,
1313 "======>\n pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]",
1314 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1316 dw_mci_queue_request(host, slot, mrq);
1318 spin_unlock_bh(&host->lock);
1321 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1323 struct dw_mci_slot *slot = mmc_priv(mmc);
1324 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1325 struct dw_mci *host = slot->host;
1327 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1330 #ifdef SDMMC_WAIT_FOR_UNBUSY
1331 unsigned long time_loop;
1334 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1335 if(host->svi_flags == 1)
1336 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1338 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1340 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1343 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1344 printk("%d..%s: no card. [%s]\n", \
1345 __LINE__, __FUNCTION__, mmc_hostname(mmc));
1350 ret = time_before(jiffies, time_loop);
1351 regs = mci_readl(slot->host, STATUS);
1352 if (!(regs & (SDMMC_STAUTS_DATA_BUSY |
1353 SDMMC_STAUTS_MC_BUSY)))
1359 printk("slot->flags = %lu ", slot->flags);
1360 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1361 if(host->svi_flags != 1)
1364 printk("%s: wait for unbusy timeout....... STATUS = 0x%x [%s]\n",
1365 __FUNCTION__, regs, mmc_hostname(mmc));
1369 switch (ios->bus_width) {
1370 case MMC_BUS_WIDTH_4:
1371 slot->ctype = SDMMC_CTYPE_4BIT;
1373 case MMC_BUS_WIDTH_8:
1374 slot->ctype = SDMMC_CTYPE_8BIT;
1377 /* set default 1 bit mode */
1378 slot->ctype = SDMMC_CTYPE_1BIT;
1379 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1382 regs = mci_readl(slot->host, UHS_REG);
1385 if (ios->timing == MMC_TIMING_UHS_DDR50)
1386 regs |= ((0x1 << slot->id) << 16);
1388 regs &= ~((0x1 << slot->id) << 16);
1390 mci_writel(slot->host, UHS_REG, regs);
1391 slot->host->timing = ios->timing;
1394 * Use mirror of ios->clock to prevent race with mmc
1395 * core ios update when finding the minimum.
1397 slot->clock = ios->clock;
1399 if (drv_data && drv_data->set_ios)
1400 drv_data->set_ios(slot->host, ios);
1402 /* Slot specific timing and width adjustment */
1403 dw_mci_setup_bus(slot, false);
1407 switch (ios->power_mode) {
1410 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1411 if (slot->host->pdata->setpower)
1412 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1413 regs = mci_readl(slot->host, PWREN);
1414 regs |= (1 << slot->id);
1415 mci_writel(slot->host, PWREN, regs);
1418 /* Power down slot */
1419 if(slot->host->pdata->setpower)
1420 slot->host->pdata->setpower(slot->id, 0);
1421 regs = mci_readl(slot->host, PWREN);
1422 regs &= ~(1 << slot->id);
1423 mci_writel(slot->host, PWREN, regs);
1430 static int dw_mci_get_ro(struct mmc_host *mmc)
1433 struct dw_mci_slot *slot = mmc_priv(mmc);
1434 struct dw_mci_board *brd = slot->host->pdata;
1436 /* Use platform get_ro function, else try on board write protect */
1437 if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1439 else if(brd->get_ro)
1440 read_only = brd->get_ro(slot->id);
1441 else if(gpio_is_valid(slot->wp_gpio))
1442 read_only = gpio_get_value(slot->wp_gpio);
1445 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1447 dev_dbg(&mmc->class_dev, "card is %s\n",
1448 read_only ? "read-only" : "read-write");
1453 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1455 struct dw_mci_slot *slot = mmc_priv(mmc);
1456 struct dw_mci *host = slot->host;
1458 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1461 spin_lock_bh(&host->lock);
1464 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1466 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1468 spin_unlock_bh(&host->lock);
1470 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1471 if (__clk_is_enabled(host->hclk_mmc) == false)
1472 clk_prepare_enable(host->hclk_mmc);
1473 if (__clk_is_enabled(host->clk_mmc) == false)
1474 clk_prepare_enable(host->clk_mmc);
1476 if (__clk_is_enabled(host->clk_mmc) == true)
1477 clk_disable_unprepare(slot->host->clk_mmc);
1478 if (__clk_is_enabled(host->hclk_mmc) == true)
1479 clk_disable_unprepare(slot->host->hclk_mmc);
1482 mmc_detect_change(slot->mmc, 20);
1488 static int dw_mci_get_cd(struct mmc_host *mmc)
1491 struct dw_mci_slot *slot = mmc_priv(mmc);
1492 struct dw_mci_board *brd = slot->host->pdata;
1493 struct dw_mci *host = slot->host;
1494 int gpio_cd = mmc_gpio_get_cd(mmc);
1495 int force_jtag_bit, force_jtag_reg;
1499 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1500 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1501 gpio_cd = slot->cd_gpio;
1502 irq = gpio_to_irq(gpio_cd);
1503 if (gpio_is_valid(gpio_cd)) {
1504 gpio_val = gpio_get_value(gpio_cd);
1505 if (soc_is_rk3036()) {
1506 force_jtag_bit = 11;
1507 force_jtag_reg = RK312X_GRF_SOC_CON0;
1508 } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1509 force_jtag_reg = RK312X_GRF_SOC_CON0;
1513 if (gpio_val == gpio_get_value(gpio_cd)) {
1514 gpio_cd = (gpio_val == 0 ? 1 : 0);
1516 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1517 /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1518 grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1520 dw_mci_ctrl_all_reset(host);
1522 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1523 /* Really card detected: SHOULD disable force_jtag */
1524 grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1529 gpio_val = gpio_get_value(gpio_cd);
1531 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
1532 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1533 return slot->last_detect_state;
1536 dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1540 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1541 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1543 /* Use platform get_cd function, else try onboard card detect */
1544 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1546 else if (brd->get_cd)
1547 present = !brd->get_cd(slot->id);
1548 else if (!IS_ERR_VALUE(gpio_cd))
1551 present = ((mci_readl(slot->host, CDETECT) & (1 << slot->id))
1554 spin_lock_bh(&host->lock);
1556 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1557 dev_dbg(&mmc->class_dev, "card is present\n");
1559 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1560 dev_dbg(&mmc->class_dev, "card is not present\n");
1562 spin_unlock_bh(&host->lock);
1569 * Dts Should caps emmc controller with poll-hw-reset
1571 static void dw_mci_hw_reset(struct mmc_host *mmc)
1573 struct dw_mci_slot *slot = mmc_priv(mmc);
1574 struct dw_mci *host = slot->host;
1579 unsigned long timeout;
1582 /* (1) CMD12 to end any transfer in process */
1583 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1584 | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1586 if(host->mmc->hold_reg_flag)
1587 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1588 mci_writel(host, CMDARG, 0);
1590 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1592 timeout = jiffies + msecs_to_jiffies(500);
1594 ret = time_before(jiffies, timeout);
1595 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1600 MMC_DBG_ERR_FUNC(host->mmc,
1601 "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1602 __func__, mmc_hostname(host->mmc));
1604 /* (2) wait DTO, even if no response is sent back by card */
1606 timeout = jiffies + msecs_to_jiffies(5);
1608 ret = time_before(jiffies, timeout);
1609 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1610 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1616 /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1618 /* Software reset - BMOD[0] for IDMA only */
1619 regs = mci_readl(host, BMOD);
1620 regs |= SDMMC_IDMAC_SWRESET;
1621 mci_writel(host, BMOD, regs);
1622 udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1623 regs = mci_readl(host, BMOD);
1624 if(regs & SDMMC_IDMAC_SWRESET)
1625 MMC_DBG_WARN_FUNC(host->mmc,
1626 "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1627 __func__, mmc_hostname(host->mmc));
1629 /* DMA reset - CTRL[2] */
1630 regs = mci_readl(host, CTRL);
1631 regs |= SDMMC_CTRL_DMA_RESET;
1632 mci_writel(host, CTRL, regs);
1633 udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1634 regs = mci_readl(host, CTRL);
1635 if(regs & SDMMC_CTRL_DMA_RESET)
1636 MMC_DBG_WARN_FUNC(host->mmc,
1637 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1638 __func__, mmc_hostname(host->mmc));
1640 /* FIFO reset - CTRL[1] */
1641 regs = mci_readl(host, CTRL);
1642 regs |= SDMMC_CTRL_FIFO_RESET;
1643 mci_writel(host, CTRL, regs);
1644 mdelay(1); /* no timing limited, 1ms is random value */
1645 regs = mci_readl(host, CTRL);
1646 if(regs & SDMMC_CTRL_FIFO_RESET)
1647 MMC_DBG_WARN_FUNC(host->mmc,
1648 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1649 __func__, mmc_hostname(host->mmc));
1652 According to eMMC spec
1653 tRstW >= 1us ; RST_n pulse width
1654 tRSCA >= 200us ; RST_n to Command time
1655 tRSTH >= 1us ; RST_n high period
1657 mci_writel(slot->host, PWREN, 0x0);
1658 mci_writel(slot->host, RST_N, 0x0);
1660 udelay(10); /* 10us for bad quality eMMc. */
1662 mci_writel(slot->host, PWREN, 0x1);
1663 mci_writel(slot->host, RST_N, 0x1);
1665 usleep_range(500, 1000); /* at least 500(> 200us) */
1669 * Disable lower power mode.
1671 * Low power mode will stop the card clock when idle. According to the
1672 * description of the CLKENA register we should disable low power mode
1673 * for SDIO cards if we need SDIO interrupts to work.
1675 * This function is fast if low power mode is already disabled.
1677 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1679 struct dw_mci *host = slot->host;
1681 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1683 clk_en_a = mci_readl(host, CLKENA);
1685 if (clk_en_a & clken_low_pwr) {
1686 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1687 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1688 SDMMC_CMD_PRV_DAT_WAIT, 0);
1692 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1694 struct dw_mci_slot *slot = mmc_priv(mmc);
1695 struct dw_mci *host = slot->host;
1696 unsigned long flags;
1700 spin_lock_irqsave(&host->slock, flags);
1702 /* Enable/disable Slot Specific SDIO interrupt */
1703 int_mask = mci_readl(host, INTMASK);
1705 if (host->verid < DW_MMC_240A)
1706 sdio_int = SDMMC_INT_SDIO(slot->id);
1708 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1712 * Turn off low power mode if it was enabled. This is a bit of
1713 * a heavy operation and we disable / enable IRQs a lot, so
1714 * we'll leave low power mode disabled and it will get
1715 * re-enabled again in dw_mci_setup_bus().
1717 dw_mci_disable_low_power(slot);
1719 mci_writel(host, INTMASK,
1720 (int_mask | sdio_int));
1722 mci_writel(host, INTMASK,
1723 (int_mask & ~sdio_int));
1726 spin_unlock_irqrestore(&host->slock, flags);
1729 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1731 IO_DOMAIN_12 = 1200,
1732 IO_DOMAIN_18 = 1800,
1733 IO_DOMAIN_33 = 3300,
1735 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1745 MMC_DBG_ERR_FUNC(host->mmc,
1746 "%s : Not support io domain voltage [%s]\n",
1747 __FUNCTION__, mmc_hostname(host->mmc));
1750 MMC_DBG_ERR_FUNC(host->mmc,
1751 "%s : Err io domain voltage [%s]\n",
1752 __FUNCTION__, mmc_hostname(host->mmc));
1756 if (cpu_is_rk3288()) {
1757 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1758 grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1761 } else if (host->cid == DW_MCI_TYPE_RK3368) {
1762 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1763 regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1767 MMC_DBG_ERR_FUNC(host->mmc,
1768 "%s : unknown chip [%s]\n",
1769 __FUNCTION__, mmc_hostname(host->mmc));
1773 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1774 struct mmc_ios *ios)
1777 unsigned int value,uhs_reg;
1780 * Signal Voltage Switching is only applicable for Host Controllers
1783 if (host->verid < DW_MMC_240A)
1786 uhs_reg = mci_readl(host, UHS_REG);
1787 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: vol=%d.[%s]\n",
1788 __FUNCTION__, ios->signal_voltage, mmc_hostname(host->mmc));
1790 switch (ios->signal_voltage) {
1791 case MMC_SIGNAL_VOLTAGE_330:
1792 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1794 if (cpu_is_rk3288())
1795 ret = io_domain_regulator_set_voltage(
1796 host->vmmc, 3300000, 3300000);
1798 ret = regulator_set_voltage(host->vmmc,
1801 /* regulator_put(host->vmmc); */
1802 MMC_DBG_SW_VOL_FUNC(host->mmc,"%s =%dmV set 3.3 end, ret = %d\n",
1803 __func__, regulator_get_voltage(host->vmmc), ret);
1805 MMC_DBG_SW_VOL_FUNC(host->mmc,
1806 "%s: Switching to 3.3V signalling voltage "
1807 " failed\n", mmc_hostname(host->mmc));
1810 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1813 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: [%s]\n",
1814 __FUNCTION__, mmc_hostname(host->mmc));
1816 /* set High-power mode */
1817 value = mci_readl(host, CLKENA);
1818 value &= ~SDMMC_CLKEN_LOW_PWR;
1819 mci_writel(host,CLKENA , value);
1821 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1822 mci_writel(host,UHS_REG , uhs_reg);
1825 usleep_range(5000, 5500);
1827 /* 3.3V regulator output should be stable within 5 ms */
1828 uhs_reg = mci_readl(host, UHS_REG);
1829 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1832 MMC_DBG_SW_VOL_FUNC(host->mmc,
1833 "%s: 3.3V regulator output did not became stable\n",
1834 mmc_hostname(host->mmc));
1837 case MMC_SIGNAL_VOLTAGE_180:
1839 if (cpu_is_rk3288())
1840 ret = io_domain_regulator_set_voltage(
1841 host->vmmc, 1800000, 1800000);
1843 ret = regulator_set_voltage(
1844 host->vmmc, 1800000, 1800000);
1845 /* regulator_put(host->vmmc); */
1846 MMC_DBG_SW_VOL_FUNC(host->mmc,
1847 "%s =%dmV set 1.8end, ret=%d . \n",
1848 __func__, regulator_get_voltage(host->vmmc), ret);
1850 MMC_DBG_SW_VOL_FUNC(host->mmc,
1851 "%s: Switching to 1.8V signalling voltage "
1852 " failed\n", mmc_hostname(host->mmc));
1855 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1859 * Enable 1.8V Signal Enable in the Host Control2
1862 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1865 usleep_range(5000, 5500);
1866 MMC_DBG_SW_VOL_FUNC(host->mmc, "%d..%s: .[%s]\n",__LINE__,
1867 __FUNCTION__, mmc_hostname(host->mmc));
1869 /* 1.8V regulator output should be stable within 5 ms */
1870 uhs_reg = mci_readl(host, UHS_REG);
1871 if (uhs_reg & SDMMC_UHS_VOLT_REG_18)
1874 MMC_DBG_SW_VOL_FUNC(host->mmc,
1875 "%s: 1.8V regulator output did not became stable\n",
1876 mmc_hostname(host->mmc));
1879 case MMC_SIGNAL_VOLTAGE_120:
1881 if (cpu_is_rk3288())
1882 ret = io_domain_regulator_set_voltage(
1883 host->vmmc, 1200000, 1200000);
1885 ret = regulator_set_voltage(host->vmmc,
1888 MMC_DBG_SW_VOL_FUNC(host->mmc,
1889 "%s: Switching to 1.2V signalling voltage "
1890 " failed\n", mmc_hostname(host->mmc));
1896 /* No signal voltage switch required */
1902 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1903 struct mmc_ios *ios)
1905 struct dw_mci_slot *slot = mmc_priv(mmc);
1906 struct dw_mci *host = slot->host;
1909 if (host->verid < DW_MMC_240A)
1912 err = dw_mci_do_start_signal_voltage_switch(host, ios);
1918 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1920 struct dw_mci_slot *slot = mmc_priv(mmc);
1921 struct dw_mci *host = slot->host;
1922 const struct dw_mci_drv_data *drv_data = host->drv_data;
1923 struct dw_mci_tuning_data tuning_data;
1926 /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1927 if(cpu_is_rk3036() || cpu_is_rk312x())
1930 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1931 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1932 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1933 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1934 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1935 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1936 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1940 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1941 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1942 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1945 "Undefined command(%d) for tuning\n", opcode);
1949 if (drv_data && drv_data->execute_tuning)
1950 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1955 static void dw_mci_post_tmo(struct mmc_host *mmc)
1957 struct dw_mci_slot *slot = mmc_priv(mmc);
1958 struct dw_mci *host = slot->host;
1959 struct mmc_data *data;
1960 u32 ret, i, regs, cmd_flags;
1962 unsigned long timeout = 0;
1963 bool ret_timeout = true;
1965 host->cur_slot->mrq = NULL;
1967 host->state = STATE_IDLE;
1971 printk("[%s] -- Timeout recovery procedure start --\n",
1972 mmc_hostname(host->mmc));
1974 if (data && (data->stop)) {
1975 send_stop_cmd(host, data);
1977 mci_writel(host, CMDARG, 0);
1979 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
1980 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1982 if (host->mmc->hold_reg_flag)
1983 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1985 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1987 timeout = jiffies + msecs_to_jiffies(500);
1989 while(ret_timeout) {
1990 ret_timeout = time_before(jiffies, timeout);
1991 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1995 if (false == ret_timeout)
1996 MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
1997 mmc_hostname(host->mmc));
2000 if (!dw_mci_ctrl_all_reset(host)) {
2005 #ifdef CONFIG_MMC_DW_IDMAC
2006 if (host->use_dma && host->dma_ops->init)
2007 host->dma_ops->init(host);
2011 * Restore the initial value at FIFOTH register
2012 * And Invalidate the prev_blksz with zero
2014 mci_writel(host, FIFOTH, host->fifoth_val);
2015 host->prev_blksz = 0;
2016 mci_writel(host, TMOUT, 0xFFFFFFFF);
2017 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2018 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
2019 | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
2020 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2021 regs |= SDMMC_INT_CD;
2023 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2024 if (host->verid < DW_MMC_240A)
2025 sdio_int = SDMMC_INT_SDIO(0);
2027 sdio_int = SDMMC_INT_SDIO(8);
2029 if (mci_readl(host, INTMASK) & sdio_int)
2033 mci_writel(host, INTMASK, regs);
2034 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2035 for (i = 0; i < host->num_slots; i++) {
2036 struct dw_mci_slot *slot = host->slot[i];
2039 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2040 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2041 dw_mci_setup_bus(slot, true);
2044 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2046 printk("[%s] -- Timeout recovery procedure finished --\n",
2047 mmc_hostname(host->mmc));
2050 static const struct mmc_host_ops dw_mci_ops = {
2051 .request = dw_mci_request,
2052 .pre_req = dw_mci_pre_req,
2053 .post_req = dw_mci_post_req,
2054 .set_ios = dw_mci_set_ios,
2055 .get_ro = dw_mci_get_ro,
2056 .get_cd = dw_mci_get_cd,
2057 .set_sdio_status = dw_mci_set_sdio_status,
2058 .hw_reset = dw_mci_hw_reset,
2059 .enable_sdio_irq = dw_mci_enable_sdio_irq,
2060 .execute_tuning = dw_mci_execute_tuning,
2061 .post_tmo = dw_mci_post_tmo,
2062 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2063 .start_signal_voltage_switch
2064 = dw_mci_start_signal_voltage_switch,
2065 .card_busy = dw_mci_card_busy,
2069 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2070 __releases(&host->lock)
2071 __acquires(&host->lock)
2073 if (DW_MCI_SEND_STATUS == host->dir_status){
2074 dw_mci_wait_unbusy(host);
2078 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2079 __releases(&host->lock)
2080 __acquires(&host->lock)
2082 struct dw_mci_slot *slot;
2083 struct mmc_host *prev_mmc = host->cur_slot->mmc;
2085 //WARN_ON(host->cmd || host->data);
2087 dw_mci_deal_data_end(host, mrq);
2090 MMC_DBG_CMD_FUNC(host->mmc,
2091 " reqeust end--reqeuest done, cmd=%d, "
2092 "cmderr=%d, host->state=%d [%s]",
2093 mrq->cmd->opcode, mrq->cmd->error,
2094 host->state,mmc_hostname(host->mmc));
2096 MMC_DBG_CMD_FUNC(host->mmc,
2097 " reqeust end--reqeuest done, cmd=%d, "
2098 "dataerr=%d, host->state=%d [%s]",
2099 mrq->cmd->opcode,mrq->data->error,
2100 host->state, mmc_hostname(host->mmc));
2102 host->cur_slot->mrq = NULL;
2104 if (!list_empty(&host->queue)) {
2105 slot = list_entry(host->queue.next,
2106 struct dw_mci_slot, queue_node);
2107 list_del(&slot->queue_node);
2108 dev_vdbg(host->dev, "list not empty: %s is next\n",
2109 mmc_hostname(slot->mmc));
2110 host->state = STATE_SENDING_CMD;
2111 MMC_DBG_CMD_FUNC(host->mmc,
2112 " list is not empty. run the request in list. [%s]",
2113 mmc_hostname(host->mmc));
2114 dw_mci_start_request(host, slot);
2116 dev_vdbg(host->dev, "list empty\n");
2117 host->state = STATE_IDLE;
2120 spin_unlock(&host->lock);
2121 mmc_request_done(prev_mmc, mrq);
2122 spin_lock(&host->lock);
2125 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2127 u32 status = host->cmd_status;
2129 host->cmd_status = 0;
2131 /* Read the response from the card (up to 16 bytes) */
2132 if (cmd->flags & MMC_RSP_PRESENT) {
2133 if (cmd->flags & MMC_RSP_136) {
2134 cmd->resp[3] = mci_readl(host, RESP0);
2135 cmd->resp[2] = mci_readl(host, RESP1);
2136 cmd->resp[1] = mci_readl(host, RESP2);
2137 cmd->resp[0] = mci_readl(host, RESP3);
2139 MMC_DBG_INFO_FUNC(host->mmc,
2140 "Command complete cmd=%d, "
2141 "resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]",
2142 cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0],
2143 mmc_hostname(host->mmc));
2145 cmd->resp[0] = mci_readl(host, RESP0);
2149 MMC_DBG_INFO_FUNC(host->mmc,
2150 "Command complete cmd=%d,resp[0]=0x%x. [%s]",
2151 cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2155 if (status & SDMMC_INT_RTO)
2157 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2160 cmd->error = -ETIMEDOUT;
2161 }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2162 cmd->error = -EILSEQ;
2163 }else if (status & SDMMC_INT_RESP_ERR){
2169 MMC_DBG_CMD_FUNC(host->mmc,
2170 "Command complete, cmd=%d,cmdError=%d [%s]",
2171 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2174 if(MMC_SEND_STATUS != cmd->opcode)
2175 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2176 MMC_DBG_CMD_FUNC(host->mmc,
2177 "Command complete, cmd=%d,cmdError=%d [%s]",
2178 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2182 /* newer ip versions need a delay between retries */
2183 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2188 static void dw_mci_tasklet_func(unsigned long priv)
2190 struct dw_mci *host = (struct dw_mci *)priv;
2191 struct dw_mci_slot *slot = mmc_priv(host->mmc);
2192 struct mmc_data *data;
2193 struct mmc_command *cmd;
2194 enum dw_mci_state state;
2195 enum dw_mci_state prev_state;
2196 u32 status, cmd_flags;
2197 unsigned long timeout = 0;
2200 spin_lock(&host->lock);
2202 state = host->state;
2212 case STATE_SENDING_CMD:
2213 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2214 &host->pending_events))
2219 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2220 dw_mci_command_complete(host, cmd);
2221 if (cmd == host->mrq->sbc && !cmd->error) {
2222 prev_state = state = STATE_SENDING_CMD;
2223 __dw_mci_start_request(host, host->cur_slot,
2228 if (cmd->data && cmd->error) {
2229 dw_mci_stop_dma(host);
2232 send_stop_cmd(host, data);
2233 state = STATE_SENDING_STOP;
2236 /* host->data = NULL; */
2239 send_stop_abort(host, data);
2240 state = STATE_SENDING_STOP;
2243 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2246 if (!host->mrq->data || cmd->error) {
2247 dw_mci_request_end(host, host->mrq);
2251 prev_state = state = STATE_SENDING_DATA;
2254 case STATE_SENDING_DATA:
2255 if (test_and_clear_bit(EVENT_DATA_ERROR,
2256 &host->pending_events)) {
2257 dw_mci_stop_dma(host);
2260 send_stop_cmd(host, data);
2262 /*single block read/write, send stop cmd
2263 manually to prevent host controller halt*/
2264 MMC_DBG_INFO_FUNC(host->mmc,
2265 "%s status 1 0x%08x [%s]\n",
2266 __func__, mci_readl(host, STATUS),
2267 mmc_hostname(host->mmc));
2269 mci_writel(host, CMDARG, 0);
2271 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2272 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2274 if(host->mmc->hold_reg_flag)
2275 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2277 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2279 timeout = jiffies + msecs_to_jiffies(500);
2282 ret = time_before(jiffies, timeout);
2283 if (!(mci_readl(host, CMD) & SDMMC_CMD_START))
2287 MMC_DBG_ERR_FUNC(host->mmc,
2288 "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2289 __func__, mmc_hostname(host->mmc));
2292 send_stop_abort(host, data);
2294 state = STATE_DATA_ERROR;
2298 MMC_DBG_CMD_FUNC(host->mmc,
2299 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2300 "wait for EVENT_XFER_COMPLETE.[%s]",
2301 prev_state, state, mmc_hostname(host->mmc));
2303 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2304 &host->pending_events))
2306 MMC_DBG_INFO_FUNC(host->mmc,
2307 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2308 "wait for EVENT_DATA_COMPLETE. [%s]",
2309 prev_state, state, mmc_hostname(host->mmc));
2311 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2312 prev_state = state = STATE_DATA_BUSY;
2315 case STATE_DATA_BUSY:
2316 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2317 &host->pending_events))
2320 dw_mci_deal_data_end(host, host->mrq);
2321 MMC_DBG_INFO_FUNC(host->mmc,
2322 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, "
2323 "after EVENT_DATA_COMPLETE. [%s]",
2324 prev_state, state, mmc_hostname(host->mmc));
2326 /* host->data = NULL; */
2327 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2328 status = host->data_status;
2330 if (status & DW_MCI_DATA_ERROR_FLAGS) {
2331 if((SDMMC_CTYPE_1BIT != slot->ctype) &&
2332 (MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2333 MMC_DBG_ERR_FUNC(host->mmc,
2334 "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,"
2335 "datastatus=0x%x [%s]",
2336 prev_state, state, status, mmc_hostname(host->mmc));
2338 if (status & SDMMC_INT_DRTO) {
2339 data->error = -ETIMEDOUT;
2340 } else if (status & SDMMC_INT_DCRC) {
2341 data->error = -EILSEQ;
2342 } else if (status & SDMMC_INT_EBE &&
2343 host->dir_status == DW_MCI_SEND_STATUS){
2345 * No data CRC status was returned.
2346 * The number of bytes transferred will
2347 * be exaggerated in PIO mode.
2349 data->bytes_xfered = 0;
2350 data->error = -ETIMEDOUT;
2359 * After an error, there may be data lingering
2360 * in the FIFO, so reset it - doing so
2361 * generates a block interrupt, hence setting
2362 * the scatter-gather pointer to NULL.
2364 dw_mci_fifo_reset(host);
2366 data->bytes_xfered = data->blocks * data->blksz;
2371 MMC_DBG_CMD_FUNC(host->mmc,
2372 "Pre-state[%d]-->NowState[%d]: "
2373 "no stop and no dataerr, exit [%s]",
2374 prev_state, state, mmc_hostname(host->mmc));
2375 dw_mci_request_end(host, host->mrq);
2378 MMC_DBG_CMD_FUNC(host->mmc,
2379 "Pre-state[%d]-->NowState[%d]: begin to stop [%s]",
2380 prev_state, state, mmc_hostname(host->mmc));
2382 if (host->mrq->sbc && !data->error) {
2383 data->stop->error = 0;
2385 MMC_DBG_CMD_FUNC(host->mmc,
2386 "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit [%s]",
2387 prev_state,state,mmc_hostname(host->mmc));
2389 dw_mci_request_end(host, host->mrq);
2393 prev_state = state = STATE_SENDING_STOP;
2395 send_stop_cmd(host, data);
2397 MMC_DBG_CMD_FUNC(host->mmc,
2398 "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP [%s]",
2399 prev_state, state, mmc_hostname(host->mmc));
2401 case STATE_SENDING_STOP:
2402 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2403 &host->pending_events))
2406 MMC_DBG_CMD_FUNC(host->mmc,
2407 "Pre-state[%d]-->NowState[%d]: begin to send cmd12 [%s]",
2408 prev_state, state, mmc_hostname(host->mmc));
2410 /* CMD error in data command */
2411 if (host->mrq->cmd->error && host->mrq->data) {
2412 dw_mci_fifo_reset(host);
2420 dw_mci_command_complete(host, host->mrq->stop);
2422 if (host->mrq->stop)
2423 dw_mci_command_complete(host, host->mrq->stop);
2425 host->cmd_status = 0;
2428 dw_mci_request_end(host, host->mrq);
2431 case STATE_DATA_ERROR:
2432 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2433 &host->pending_events))
2436 state = STATE_DATA_BUSY;
2439 } while (state != prev_state);
2441 host->state = state;
2443 spin_unlock(&host->lock);
2446 /* push final bytes to part_buf, only use during push */
2447 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2449 memcpy((void *)&host->part_buf, buf, cnt);
2450 host->part_buf_count = cnt;
2453 /* append bytes to part_buf, only use during push */
2454 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2456 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2457 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2458 host->part_buf_count += cnt;
2462 /* pull first bytes from part_buf, only use during pull */
2463 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2465 cnt = min(cnt, (int)host->part_buf_count);
2467 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2469 host->part_buf_count -= cnt;
2470 host->part_buf_start += cnt;
2475 /* pull final bytes from the part_buf, assuming it's just been filled */
2476 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2478 memcpy(buf, &host->part_buf, cnt);
2479 host->part_buf_start = cnt;
2480 host->part_buf_count = (1 << host->data_shift) - cnt;
2483 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2485 struct mmc_data *data = host->data;
2488 /* try and push anything in the part_buf */
2489 if (unlikely(host->part_buf_count)) {
2490 int len = dw_mci_push_part_bytes(host, buf, cnt);
2493 if (host->part_buf_count == 2) {
2494 mci_writew(host, DATA(host->data_offset),
2496 host->part_buf_count = 0;
2499 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2500 if (unlikely((unsigned long)buf & 0x1)) {
2502 u16 aligned_buf[64];
2503 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2504 int items = len >> 1;
2506 /* memcpy from input buffer into aligned buffer */
2507 memcpy(aligned_buf, buf, len);
2510 /* push data from aligned buffer into fifo */
2511 for (i = 0; i < items; ++i)
2512 mci_writew(host, DATA(host->data_offset),
2519 for (; cnt >= 2; cnt -= 2)
2520 mci_writew(host, DATA(host->data_offset), *pdata++);
2523 /* put anything remaining in the part_buf */
2525 dw_mci_set_part_bytes(host, buf, cnt);
2526 /* Push data if we have reached the expected data length */
2527 if ((data->bytes_xfered + init_cnt) ==
2528 (data->blksz * data->blocks))
2529 mci_writew(host, DATA(host->data_offset),
2534 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2536 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2537 if (unlikely((unsigned long)buf & 0x1)) {
2539 /* pull data from fifo into aligned buffer */
2540 u16 aligned_buf[64];
2541 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2542 int items = len >> 1;
2544 for (i = 0; i < items; ++i)
2545 aligned_buf[i] = mci_readw(host,
2546 DATA(host->data_offset));
2547 /* memcpy from aligned buffer into output buffer */
2548 memcpy(buf, aligned_buf, len);
2556 for (; cnt >= 2; cnt -= 2)
2557 *pdata++ = mci_readw(host, DATA(host->data_offset));
2561 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2562 dw_mci_pull_final_bytes(host, buf, cnt);
2566 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2568 struct mmc_data *data = host->data;
2571 /* try and push anything in the part_buf */
2572 if (unlikely(host->part_buf_count)) {
2573 int len = dw_mci_push_part_bytes(host, buf, cnt);
2576 if (host->part_buf_count == 4) {
2577 mci_writel(host, DATA(host->data_offset),
2579 host->part_buf_count = 0;
2582 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2583 if (unlikely((unsigned long)buf & 0x3)) {
2585 u32 aligned_buf[32];
2586 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2587 int items = len >> 2;
2589 /* memcpy from input buffer into aligned buffer */
2590 memcpy(aligned_buf, buf, len);
2593 /* push data from aligned buffer into fifo */
2594 for (i = 0; i < items; ++i)
2595 mci_writel(host, DATA(host->data_offset),
2602 for (; cnt >= 4; cnt -= 4)
2603 mci_writel(host, DATA(host->data_offset), *pdata++);
2606 /* put anything remaining in the part_buf */
2608 dw_mci_set_part_bytes(host, buf, cnt);
2609 /* Push data if we have reached the expected data length */
2610 if ((data->bytes_xfered + init_cnt) ==
2611 (data->blksz * data->blocks))
2612 mci_writel(host, DATA(host->data_offset),
2617 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2619 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2620 if (unlikely((unsigned long)buf & 0x3)) {
2622 /* pull data from fifo into aligned buffer */
2623 u32 aligned_buf[32];
2624 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2625 int items = len >> 2;
2627 for (i = 0; i < items; ++i)
2628 aligned_buf[i] = mci_readl(host,
2629 DATA(host->data_offset));
2630 /* memcpy from aligned buffer into output buffer */
2631 memcpy(buf, aligned_buf, len);
2639 for (; cnt >= 4; cnt -= 4)
2640 *pdata++ = mci_readl(host, DATA(host->data_offset));
2644 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2645 dw_mci_pull_final_bytes(host, buf, cnt);
2649 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2651 struct mmc_data *data = host->data;
2654 /* try and push anything in the part_buf */
2655 if (unlikely(host->part_buf_count)) {
2656 int len = dw_mci_push_part_bytes(host, buf, cnt);
2660 if (host->part_buf_count == 8) {
2661 mci_writeq(host, DATA(host->data_offset),
2663 host->part_buf_count = 0;
2666 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2667 if (unlikely((unsigned long)buf & 0x7)) {
2669 u64 aligned_buf[16];
2670 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2671 int items = len >> 3;
2673 /* memcpy from input buffer into aligned buffer */
2674 memcpy(aligned_buf, buf, len);
2677 /* push data from aligned buffer into fifo */
2678 for (i = 0; i < items; ++i)
2679 mci_writeq(host, DATA(host->data_offset),
2686 for (; cnt >= 8; cnt -= 8)
2687 mci_writeq(host, DATA(host->data_offset), *pdata++);
2690 /* put anything remaining in the part_buf */
2692 dw_mci_set_part_bytes(host, buf, cnt);
2693 /* Push data if we have reached the expected data length */
2694 if ((data->bytes_xfered + init_cnt) ==
2695 (data->blksz * data->blocks))
2696 mci_writeq(host, DATA(host->data_offset),
2701 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2703 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2704 if (unlikely((unsigned long)buf & 0x7)) {
2706 /* pull data from fifo into aligned buffer */
2707 u64 aligned_buf[16];
2708 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2709 int items = len >> 3;
2711 for (i = 0; i < items; ++i)
2712 aligned_buf[i] = mci_readq(host,
2713 DATA(host->data_offset));
2714 /* memcpy from aligned buffer into output buffer */
2715 memcpy(buf, aligned_buf, len);
2723 for (; cnt >= 8; cnt -= 8)
2724 *pdata++ = mci_readq(host, DATA(host->data_offset));
2728 host->part_buf = mci_readq(host, DATA(host->data_offset));
2729 dw_mci_pull_final_bytes(host, buf, cnt);
2733 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2737 /* get remaining partial bytes */
2738 len = dw_mci_pull_part_bytes(host, buf, cnt);
2739 if (unlikely(len == cnt))
2744 /* get the rest of the data */
2745 host->pull_data(host, buf, cnt);
2748 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2750 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2752 unsigned int offset;
2753 struct mmc_data *data = host->data;
2754 int shift = host->data_shift;
2757 unsigned int remain, fcnt;
2759 if(!host->mmc->bus_refs){
2760 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2764 if (!sg_miter_next(sg_miter))
2767 host->sg = sg_miter->piter.sg;
2768 buf = sg_miter->addr;
2769 remain = sg_miter->length;
2773 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2774 << shift) + host->part_buf_count;
2775 len = min(remain, fcnt);
2778 dw_mci_pull_data(host, (void *)(buf + offset), len);
2779 data->bytes_xfered += len;
2784 sg_miter->consumed = offset;
2785 status = mci_readl(host, MINTSTS);
2786 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2787 /* if the RXDR is ready read again */
2788 } while ((status & SDMMC_INT_RXDR) ||
2789 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2792 if (!sg_miter_next(sg_miter))
2794 sg_miter->consumed = 0;
2796 sg_miter_stop(sg_miter);
2800 sg_miter_stop(sg_miter);
2804 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2807 static void dw_mci_write_data_pio(struct dw_mci *host)
2809 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2811 unsigned int offset;
2812 struct mmc_data *data = host->data;
2813 int shift = host->data_shift;
2816 unsigned int fifo_depth = host->fifo_depth;
2817 unsigned int remain, fcnt;
2819 if (!host->mmc->bus_refs){
2820 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2825 if (!sg_miter_next(sg_miter))
2828 host->sg = sg_miter->piter.sg;
2829 buf = sg_miter->addr;
2830 remain = sg_miter->length;
2834 fcnt = ((fifo_depth -
2835 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2836 << shift) - host->part_buf_count;
2837 len = min(remain, fcnt);
2840 host->push_data(host, (void *)(buf + offset), len);
2841 data->bytes_xfered += len;
2846 sg_miter->consumed = offset;
2847 status = mci_readl(host, MINTSTS);
2848 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2849 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2852 if (!sg_miter_next(sg_miter))
2854 sg_miter->consumed = 0;
2856 sg_miter_stop(sg_miter);
2860 sg_miter_stop(sg_miter);
2864 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2867 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2869 if (!host->cmd_status)
2870 host->cmd_status = status;
2877 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2878 tasklet_schedule(&host->tasklet);
2881 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2883 struct dw_mci *host = dev_id;
2884 u32 pending, sdio_int;
2887 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2890 * DTO fix - version 2.10a and below, and only if internal DMA
2893 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2895 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2896 pending |= SDMMC_INT_DATA_OVER;
2900 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2901 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2902 host->cmd_status = pending;
2904 MMC_DBG_INFO_FUNC(host->mmc,
2905 "%s cmd_status INT=0x%x,[%s]",
2906 __FUNCTION__, host->cmd_status,
2907 mmc_hostname(host->mmc));
2909 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2912 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2913 /* if there is an error report DATA_ERROR */
2914 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2915 host->data_status = pending;
2917 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2919 MMC_DBG_INFO_FUNC(host->mmc,
2920 "%s data_status INT=0x%x,[%s]",
2921 __FUNCTION__, host->data_status,
2922 mmc_hostname(host->mmc));
2923 tasklet_schedule(&host->tasklet);
2926 if (pending & SDMMC_INT_DATA_OVER) {
2927 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2928 MMC_DBG_CMD_FUNC(host->mmc,
2929 "SDMMC_INT_DATA_OVER, INT-pending=0x%x [%s]",
2930 pending, mmc_hostname(host->mmc));
2931 if (!host->data_status)
2932 host->data_status = pending;
2934 if (host->dir_status == DW_MCI_RECV_STATUS) {
2935 if (host->sg != NULL)
2936 dw_mci_read_data_pio(host, true);
2938 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2939 tasklet_schedule(&host->tasklet);
2942 if (pending & SDMMC_INT_RXDR) {
2943 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2944 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2945 dw_mci_read_data_pio(host, false);
2948 if (pending & SDMMC_INT_TXDR) {
2949 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2950 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2951 dw_mci_write_data_pio(host);
2954 if (pending & SDMMC_INT_VSI) {
2955 MMC_DBG_SW_VOL_FUNC(host->mmc,
2956 "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",
2957 pending, mmc_hostname(host->mmc));
2958 mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2959 dw_mci_cmd_interrupt(host, pending);
2962 if (pending & SDMMC_INT_CMD_DONE) {
2963 MMC_DBG_CMD_FUNC(host->mmc,
2964 "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",
2965 mci_readl(host, CMD), pending, mmc_hostname(host->mmc));
2966 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2967 dw_mci_cmd_interrupt(host, pending);
2970 if (pending & SDMMC_INT_CD) {
2971 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2972 MMC_DBG_INFO_FUNC(host->mmc,
2973 "SDMMC_INT_CD, INT-pending=0x%x. [%s]",
2974 pending, mmc_hostname(host->mmc));
2975 wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2976 queue_work(host->card_workqueue, &host->card_work);
2979 if (pending & SDMMC_INT_HLE) {
2980 mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2981 MMC_DBG_CMD_FUNC(host->mmc,
2982 "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",
2983 pending, mmc_hostname(host->mmc));
2987 /* Handle SDIO Interrupts */
2988 for (i = 0; i < host->num_slots; i++) {
2989 struct dw_mci_slot *slot = host->slot[i];
2991 if (host->verid < DW_MMC_240A)
2992 sdio_int = SDMMC_INT_SDIO(i);
2994 sdio_int = SDMMC_INT_SDIO(i + 8);
2996 if (pending & sdio_int) {
2997 mci_writel(host, RINTSTS, sdio_int);
2998 mmc_signal_sdio_irq(slot->mmc);
3004 #ifdef CONFIG_MMC_DW_IDMAC
3005 /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3006 if (!(cpu_is_rk3036() || cpu_is_rk312x())){
3007 /* Handle DMA interrupts */
3008 pending = mci_readl(host, IDSTS);
3009 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3010 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3011 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3012 host->dma_ops->complete((void *)host);
3020 static void dw_mci_work_routine_card(struct work_struct *work)
3022 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3025 for (i = 0; i < host->num_slots; i++) {
3026 struct dw_mci_slot *slot = host->slot[i];
3027 struct mmc_host *mmc = slot->mmc;
3028 struct mmc_request *mrq;
3031 present = dw_mci_get_cd(mmc);
3033 /* Card insert, switch data line to uart function, and vice verse.
3034 ONLY audi chip need switched by software, using udbg tag in dts!
3036 if (!(IS_ERR(host->pins_udbg)) &&
3037 !(IS_ERR(host->pins_default))) {
3039 if (pinctrl_select_state(host->pinctrl,
3040 host->pins_default) < 0)
3042 "%s: Default pinctrl setting failed!\n",
3043 mmc_hostname(host->mmc));
3045 if (pinctrl_select_state(host->pinctrl,
3046 host->pins_udbg) < 0)
3048 "%s: Udbg pinctrl setting failed!\n",
3049 mmc_hostname(host->mmc));
3053 while (present != slot->last_detect_state) {
3054 dev_dbg(&slot->mmc->class_dev, "card %s\n",
3055 present ? "inserted" : "removed");
3056 MMC_DBG_BOOT_FUNC(mmc, " The card is %s. ===!!!!!!==[%s]\n",
3057 present ? "inserted" : "removed.", mmc_hostname(mmc));
3059 dw_mci_ctrl_all_reset(host);
3060 /* Stop edma when rountine card triggered */
3061 if(cpu_is_rk3036() || cpu_is_rk312x())
3062 if(host->dma_ops && host->dma_ops->stop)
3063 host->dma_ops->stop(host);
3064 rk_send_wakeup_key();//wake up system
3065 spin_lock_bh(&host->lock);
3067 /* Card change detected */
3068 slot->last_detect_state = present;
3070 /* Clean up queue if present */
3073 if (mrq == host->mrq) {
3077 switch (host->state) {
3080 case STATE_SENDING_CMD:
3081 mrq->cmd->error = -ENOMEDIUM;
3085 case STATE_SENDING_DATA:
3086 mrq->data->error = -ENOMEDIUM;
3087 dw_mci_stop_dma(host);
3089 case STATE_DATA_BUSY:
3090 case STATE_DATA_ERROR:
3091 if (mrq->data->error == -EINPROGRESS)
3092 mrq->data->error = -ENOMEDIUM;
3096 case STATE_SENDING_STOP:
3097 mrq->stop->error = -ENOMEDIUM;
3101 dw_mci_request_end(host, mrq);
3103 list_del(&slot->queue_node);
3104 mrq->cmd->error = -ENOMEDIUM;
3106 mrq->data->error = -ENOMEDIUM;
3108 mrq->stop->error = -ENOMEDIUM;
3110 MMC_DBG_CMD_FUNC(host->mmc,
3111 "dw_mci_work--reqeuest done, cmd=%d [%s]",
3112 mrq->cmd->opcode, mmc_hostname(mmc));
3114 spin_unlock(&host->lock);
3115 mmc_request_done(slot->mmc, mrq);
3116 spin_lock(&host->lock);
3120 /* Power down slot */
3122 /* Clear down the FIFO */
3123 dw_mci_fifo_reset(host);
3124 #ifdef CONFIG_MMC_DW_IDMAC
3125 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
3126 dw_mci_idmac_reset(host);
3130 spin_unlock_bh(&host->lock);
3132 present = dw_mci_get_cd(mmc);
3135 mmc_detect_change(slot->mmc,
3136 msecs_to_jiffies(host->pdata->detect_delay_ms));
3141 /* given a slot id, find out the device node representing that slot */
3142 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3144 struct device_node *np;
3148 if (!dev || !dev->of_node)
3151 for_each_child_of_node(dev->of_node, np) {
3152 addr = of_get_property(np, "reg", &len);
3153 if (!addr || (len < sizeof(int)))
3155 if (be32_to_cpup(addr) == slot)
3161 static struct dw_mci_of_slot_quirks {
3164 } of_slot_quirks[] = {
3166 .quirk = "disable-wp",
3167 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3171 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3173 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3178 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3179 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3180 quirks |= of_slot_quirks[idx].id;
3185 /* find out bus-width for a given slot */
3186 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3188 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3194 if (of_property_read_u32(np, "bus-width", &bus_wd))
3195 dev_err(dev, "bus-width property not found, assuming width"
3201 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3202 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3204 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3210 gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3212 /* Having a missing entry is valid; return silently */
3213 if (!gpio_is_valid(gpio))
3216 if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3217 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3221 gpio_direction_output(gpio, 0);//set 0 to pwr-en
3227 /* find the write protect gpio for a given slot; or -1 if none specified */
3228 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3230 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3236 gpio = of_get_named_gpio(np, "wp-gpios", 0);
3238 /* Having a missing entry is valid; return silently */
3239 if (!gpio_is_valid(gpio))
3242 if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3243 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3250 /* find the cd gpio for a given slot */
3251 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3252 struct mmc_host *mmc)
3254 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3260 gpio = of_get_named_gpio(np, "cd-gpios", 0);
3262 /* Having a missing entry is valid; return silently */
3263 if (!gpio_is_valid(gpio))
3266 if (mmc_gpio_request_cd(mmc, gpio, 0))
3267 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3270 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3272 struct mmc_host *mmc = dev_id;
3273 struct dw_mci_slot *slot = mmc_priv(mmc);
3274 struct dw_mci *host = slot->host;
3275 int gpio_cd = slot->cd_gpio;
3277 (gpio_get_value(gpio_cd) == 0) ?
3278 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
3279 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3281 /* wakeup system whether gpio debounce or not */
3282 rk_send_wakeup_key();
3284 /* no need to trigger detect flow when rescan is disabled.
3285 This case happended in dpm, that we just wakeup system and
3286 let suspend_post notify callback handle it.
3288 if(mmc->rescan_disable == 0)
3289 queue_work(host->card_workqueue, &host->card_work);
3291 printk("%s: rescan been disabled!\n", __FUNCTION__);
3296 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3297 struct mmc_host *mmc)
3299 struct dw_mci_slot *slot = mmc_priv(mmc);
3300 struct dw_mci *host = slot->host;
3304 /* Having a missing entry is valid; return silently */
3305 if (!gpio_is_valid(gpio))
3308 irq = gpio_to_irq(gpio);
3310 ret = devm_request_threaded_irq(
3311 &mmc->class_dev, irq,
3312 NULL, dw_mci_gpio_cd_irqt,
3313 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3318 "Request cd-gpio %d interrupt error!\n", gpio);
3320 /* enable wakeup event for gpio-cd in idle or deep suspend*/
3321 enable_irq_wake(irq);
3324 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3328 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3329 struct mmc_host *mmc)
3331 if (!gpio_is_valid(gpio))
3334 if (gpio_to_irq(gpio) >= 0) {
3335 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3336 devm_gpio_free(&mmc->class_dev, gpio);
3339 #else /* CONFIG_OF */
3340 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3344 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3348 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3352 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3356 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3357 struct mmc_host *mmc)
3361 #endif /* CONFIG_OF */
3363 /* @host: dw_mci host prvdata
3364 * Init pinctrl for each platform. Usually we assign
3365 * "defalut" tag for functional usage, "idle" tag for gpio
3366 * state and "udbg" tag for uart_dbg if any.
3368 static void dw_mci_init_pinctrl(struct dw_mci *host)
3370 /* Fixme: DON'T TOUCH EMMC SETTING! */
3371 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3374 /* Get pinctrl for DTS */
3375 host->pinctrl = devm_pinctrl_get(host->dev);
3376 if (IS_ERR(host->pinctrl)) {
3377 dev_err(host->dev, "%s: No pinctrl used!\n",
3378 mmc_hostname(host->mmc));
3382 /* Lookup idle state */
3384 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_IDLE);
3385 if (IS_ERR(host->pins_idle)) {
3386 dev_err(host->dev, "%s: No idle tag found!\n",
3387 mmc_hostname(host->mmc));
3389 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3391 "%s: Idle pinctrl setting failed!\n",
3392 mmc_hostname(host->mmc));
3395 /* Lookup default state */
3396 host->pins_default =
3397 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_DEFAULT);
3398 if (IS_ERR(host->pins_default)) {
3399 dev_err(host->dev, "%s: No default pinctrl found!\n",
3400 mmc_hostname(host->mmc));
3402 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3404 "%s: Default pinctrl setting failed!\n",
3405 mmc_hostname(host->mmc));
3408 /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3409 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3410 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3411 if (IS_ERR(host->pins_udbg)) {
3412 dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3413 mmc_hostname(host->mmc));
3415 if (!dw_mci_get_cd(host->mmc))
3416 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3417 dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3418 mmc_hostname(host->mmc));
3423 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3424 unsigned long mode, void *unused)
3426 struct mmc_host *host = container_of(
3427 notify_block, struct mmc_host, pm_notify);
3428 unsigned long flags;
3431 case PM_HIBERNATION_PREPARE:
3432 case PM_SUSPEND_PREPARE:
3433 dev_err(host->parent,
3434 "dw_mci_pm_notify: suspend prepare\n");
3435 spin_lock_irqsave(&host->lock, flags);
3436 host->rescan_disable = 1;
3437 spin_unlock_irqrestore(&host->lock, flags);
3438 if (cancel_delayed_work(&host->detect))
3439 wake_unlock(&host->detect_wake_lock);
3442 case PM_POST_SUSPEND:
3443 case PM_POST_HIBERNATION:
3444 case PM_POST_RESTORE:
3445 dev_err(host->parent,
3446 "dw_mci_pm_notify: post suspend\n");
3447 spin_lock_irqsave(&host->lock, flags);
3448 host->rescan_disable = 0;
3449 spin_unlock_irqrestore(&host->lock, flags);
3450 mmc_detect_change(host, 10);
3456 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3458 struct mmc_host *mmc;
3459 struct dw_mci_slot *slot;
3460 const struct dw_mci_drv_data *drv_data = host->drv_data;
3465 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3469 slot = mmc_priv(mmc);
3473 host->slot[id] = slot;
3476 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3478 mmc->ops = &dw_mci_ops;
3480 if (of_property_read_u32_array(host->dev->of_node,
3481 "clock-freq-min-max", freq, 2)) {
3482 mmc->f_min = DW_MCI_FREQ_MIN;
3483 mmc->f_max = DW_MCI_FREQ_MAX;
3485 printk("%s: fmin=%d, fmax=%d [%s]\n",
3486 __FUNCTION__, mmc->f_min,
3487 mmc->f_max, mmc_hostname(mmc));
3489 mmc->f_min = freq[0];
3490 mmc->f_max = freq[1];
3492 printk("%s: fmin=%d, fmax=%d [%s]\n",
3493 __FUNCTION__, mmc->f_min,
3494 mmc->f_max, mmc_hostname(mmc));
3497 if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3498 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3499 if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3500 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3501 if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3502 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3504 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3505 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3506 if (register_pm_notifier(&mmc->pm_notify)) {
3507 pr_err("dw_mci: register_pm_notifier failed\n");
3508 goto err_pm_notifier;
3512 if (host->cid == DW_MCI_TYPE_RK3368) {
3513 if (IS_ERR(host->grf))
3514 pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3516 /* Disable force_jtag */
3517 regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3518 } else if (cpu_is_rk3288()) {
3519 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3522 /* We assume only low-level chip use gpio_cd */
3523 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3524 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3525 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3526 if (gpio_is_valid(slot->cd_gpio)) {
3527 /* Request gpio int for card detection */
3528 dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3530 slot->cd_gpio = -ENODEV;
3531 dev_err(host->dev, "failed to get your cd-gpios!\n");
3535 if (host->pdata->get_ocr)
3536 mmc->ocr_avail = host->pdata->get_ocr(id);
3539 mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
3540 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33|
3541 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36 |
3542 MMC_VDD_26_27 | MMC_VDD_25_26 | MMC_VDD_24_25 |
3543 MMC_VDD_23_24 | MMC_VDD_22_23 | MMC_VDD_21_22 |
3544 MMC_VDD_20_21 | MMC_VDD_165_195;
3548 * Start with slot power disabled, it will be enabled when a card
3551 if (host->pdata->setpower)
3552 host->pdata->setpower(id, 0);
3554 if (host->pdata->caps)
3555 mmc->caps = host->pdata->caps;
3557 if (host->pdata->pm_caps)
3558 mmc->pm_caps = host->pdata->pm_caps;
3560 if (host->dev->of_node) {
3561 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3565 ctrl_id = to_platform_device(host->dev)->id;
3567 if (drv_data && drv_data->caps)
3568 mmc->caps |= drv_data->caps[ctrl_id];
3569 if (drv_data && drv_data->hold_reg_flag)
3570 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3572 /* set the compatibility of driver. */
3573 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3574 | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3576 if (host->pdata->caps2)
3577 mmc->caps2 = host->pdata->caps2;
3579 if (host->pdata->get_bus_wd)
3580 bus_width = host->pdata->get_bus_wd(slot->id);
3581 else if (host->dev->of_node)
3582 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3586 switch (bus_width) {
3588 mmc->caps |= MMC_CAP_8_BIT_DATA;
3590 mmc->caps |= MMC_CAP_4_BIT_DATA;
3593 if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3594 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3595 if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3596 mmc->caps |= MMC_CAP_SDIO_IRQ;
3597 if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3598 mmc->caps |= MMC_CAP_HW_RESET;
3599 if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3600 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3601 if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3602 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3603 if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3604 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3605 if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3606 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3608 /*Assign pm_caps pass to pm_flags*/
3609 mmc->pm_flags = mmc->pm_caps;
3611 if (host->pdata->blk_settings) {
3612 mmc->max_segs = host->pdata->blk_settings->max_segs;
3613 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3614 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3615 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3616 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3618 /* Useful defaults if platform data is unset. */
3619 #ifdef CONFIG_MMC_DW_IDMAC
3620 mmc->max_segs = host->ring_size;
3621 mmc->max_blk_size = 65536;
3622 mmc->max_blk_count = host->ring_size;
3623 mmc->max_seg_size = 0x1000;
3624 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3625 if(cpu_is_rk3036() || cpu_is_rk312x()){
3626 /* fixup for external dmac setting */
3628 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3629 mmc->max_blk_count = 65535;
3630 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3631 mmc->max_seg_size = mmc->max_req_size;
3635 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3636 mmc->max_blk_count = 512;
3637 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3638 mmc->max_seg_size = mmc->max_req_size;
3639 #endif /* CONFIG_MMC_DW_IDMAC */
3643 slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3645 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3650 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3651 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3655 if (IS_ERR(host->vmmc)) {
3656 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3659 ret = regulator_enable(host->vmmc);
3662 "failed to enable regulator: %d\n", ret);
3669 slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3671 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3672 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3674 dw_mci_init_pinctrl(host);
3675 ret = mmc_add_host(mmc);
3679 #if defined(CONFIG_DEBUG_FS)
3680 dw_mci_init_debugfs(slot);
3683 /* Card initially undetected */
3684 slot->last_detect_state = 1;
3688 unregister_pm_notifier(&mmc->pm_notify);
3691 if (gpio_is_valid(slot->cd_gpio))
3692 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3697 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3699 /* Shutdown detect IRQ */
3700 if (slot->host->pdata->exit)
3701 slot->host->pdata->exit(id);
3703 /* Debugfs stuff is cleaned up by mmc core */
3704 mmc_remove_host(slot->mmc);
3705 slot->host->slot[id] = NULL;
3706 mmc_free_host(slot->mmc);
3709 static void dw_mci_init_dma(struct dw_mci *host)
3711 /* Alloc memory for sg translation */
3712 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3713 &host->sg_dma, GFP_KERNEL);
3714 if (!host->sg_cpu) {
3715 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3720 /* Determine which DMA interface to use */
3721 #if defined(CONFIG_MMC_DW_IDMAC)
3722 if(cpu_is_rk3036() || cpu_is_rk312x()){
3723 host->dma_ops = &dw_mci_edmac_ops;
3724 dev_info(host->dev, "Using external DMA controller.\n");
3726 host->dma_ops = &dw_mci_idmac_ops;
3727 dev_info(host->dev, "Using internal DMA controller.\n");
3734 if (host->dma_ops->init && host->dma_ops->start &&
3735 host->dma_ops->stop && host->dma_ops->cleanup) {
3736 if (host->dma_ops->init(host)) {
3737 dev_err(host->dev, "%s: Unable to initialize "
3738 "DMA Controller.\n", __func__);
3742 dev_err(host->dev, "DMA initialization not found.\n");
3750 dev_info(host->dev, "Using PIO mode.\n");
3755 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3757 unsigned long timeout = jiffies + msecs_to_jiffies(500);
3760 ctrl = mci_readl(host, CTRL);
3762 mci_writel(host, CTRL, ctrl);
3764 /* wait till resets clear */
3766 ctrl = mci_readl(host, CTRL);
3767 if (!(ctrl & reset))
3769 } while (time_before(jiffies, timeout));
3772 "Timeout resetting block (ctrl reset %#x)\n",
3778 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3781 * Reseting generates a block interrupt, hence setting
3782 * the scatter-gather pointer to NULL.
3785 sg_miter_stop(&host->sg_miter);
3789 return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3792 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3794 return dw_mci_ctrl_reset(host,
3795 SDMMC_CTRL_FIFO_RESET |
3797 SDMMC_CTRL_DMA_RESET);
3800 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3805 buffer = host->regs_buffer;
3807 for (index = 0; index < DW_REGS_NUM ; index++){
3808 *buffer = mci_readreg(host, index*4);
3809 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3810 dw_mci_regs[index].name, *buffer);
3814 *buffer = mci_readl(host,CDTHRCTL);
3815 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3818 static void dw_mci_rst_post_resume(struct dw_mci *host)
3823 buffer = host->regs_buffer;
3825 for (index = 0; index < DW_REGS_NUM; index++){
3826 mci_writereg(host, index*4, *buffer);
3829 mci_writel(host, CDTHRCTL, *buffer);
3832 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3833 .pre_suspend = dw_mci_rst_pre_suspend,
3834 .post_resume = dw_mci_rst_post_resume,
3839 static struct dw_mci_of_quirks {
3844 .quirk = "broken-cd",
3845 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3849 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3851 struct dw_mci_board *pdata;
3852 struct device *dev = host->dev;
3853 struct device_node *np = dev->of_node;
3854 const struct dw_mci_drv_data *drv_data = host->drv_data;
3856 u32 clock_frequency;
3858 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3860 dev_err(dev, "could not allocate memory for pdata\n");
3861 return ERR_PTR(-ENOMEM);
3864 /* find out number of slots supported */
3865 if (of_property_read_u32(dev->of_node, "num-slots",
3866 &pdata->num_slots)) {
3867 dev_info(dev, "num-slots property not found, "
3868 "assuming 1 slot is available\n");
3869 pdata->num_slots = 1;
3872 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3873 dev_info(dev, "fifo-depth property not found, using "
3874 "value of FIFOTH register as default\n");
3876 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3878 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3879 pdata->bus_hz = clock_frequency;
3881 if (drv_data && drv_data->parse_dt) {
3882 ret = drv_data->parse_dt(host);
3884 return ERR_PTR(ret);
3887 if (of_find_property(np, "keep-power-in-suspend", NULL))
3888 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3890 if (of_find_property(np, "enable-sdio-wakeup", NULL))
3891 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3893 if (of_find_property(np, "supports-highspeed", NULL))
3894 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3896 if (of_find_property(np, "supports-UHS_SDR104", NULL))
3897 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3899 if (of_find_property(np, "supports-DDR_MODE", NULL))
3900 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3902 if (of_find_property(np, "caps2-mmc-hs200", NULL))
3903 pdata->caps2 |= MMC_CAP2_HS200;
3905 if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3906 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3908 if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3909 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3911 if (of_get_property(np, "cd-inverted", NULL))
3912 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3913 if (of_get_property(np, "bootpart-no-access", NULL))
3914 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3916 if (of_get_property(np, "controller-power-down", NULL)) {
3917 host->regs_buffer = (u32 *)devm_kzalloc(host->dev,
3918 DW_REGS_SIZE, GFP_KERNEL);
3919 if (!host->regs_buffer) {
3921 "could not allocate memory for regs_buffer\n");
3922 return ERR_PTR(-ENOMEM);
3925 host->rst_ops = &dw_mci_pdrst_ops;
3926 mmc_assume_removable = 0;
3932 #else /* CONFIG_OF */
3933 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3935 return ERR_PTR(-EINVAL);
3937 #endif /* CONFIG_OF */
3939 int dw_mci_probe(struct dw_mci *host)
3941 const struct dw_mci_drv_data *drv_data = host->drv_data;
3942 int width, i, ret = 0;
3948 host->pdata = dw_mci_parse_dt(host);
3949 if (IS_ERR(host->pdata)) {
3950 dev_err(host->dev, "platform data not available\n");
3955 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3957 "Platform data must supply select_slot function\n");
3962 * In 2.40a spec, Data offset is changed.
3963 * Need to check the version-id and set data-offset for DATA register.
3965 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3966 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3968 if (host->verid < DW_MMC_240A)
3969 host->data_offset = DATA_OFFSET;
3971 host->data_offset = DATA_240A_OFFSET;
3974 host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
3975 if (IS_ERR(host->hpclk_mmc)) {
3976 dev_err(host->dev, "failed to get hpclk_mmc\n");
3978 clk_prepare_enable(host->hpclk_mmc);
3982 host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3983 if (IS_ERR(host->hclk_mmc)) {
3984 dev_err(host->dev, "failed to get hclk_mmc\n");
3985 ret = PTR_ERR(host->hclk_mmc);
3989 clk_prepare_enable(host->hclk_mmc);
3992 host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3993 if (IS_ERR(host->clk_mmc)) {
3994 dev_err(host->dev, "failed to get clk mmc_per\n");
3995 ret = PTR_ERR(host->clk_mmc);
3999 host->bus_hz = host->pdata->bus_hz;
4000 if (!host->bus_hz) {
4001 dev_err(host->dev, "Platform data must supply bus speed\n");
4006 if (host->verid < DW_MMC_240A)
4007 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4009 //rockchip: fix divider 2 in clksum before controlller
4010 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4013 dev_err(host->dev, "failed to set clk mmc\n");
4016 clk_prepare_enable(host->clk_mmc);
4018 if (drv_data && drv_data->setup_clock) {
4019 ret = drv_data->setup_clock(host);
4022 "implementation specific clock setup failed\n");
4027 host->quirks = host->pdata->quirks;
4028 host->irq_state = true;
4029 host->set_speed = 0;
4031 host->svi_flags = 0;
4033 spin_lock_init(&host->lock);
4034 spin_lock_init(&host->slock);
4036 INIT_LIST_HEAD(&host->queue);
4038 * Get the host data width - this assumes that HCON has been set with
4039 * the correct values.
4041 i = (mci_readl(host, HCON) >> 7) & 0x7;
4043 host->push_data = dw_mci_push_data16;
4044 host->pull_data = dw_mci_pull_data16;
4046 host->data_shift = 1;
4047 } else if (i == 2) {
4048 host->push_data = dw_mci_push_data64;
4049 host->pull_data = dw_mci_pull_data64;
4051 host->data_shift = 3;
4053 /* Check for a reserved value, and warn if it is */
4055 "HCON reports a reserved host data width!\n"
4056 "Defaulting to 32-bit access.\n");
4057 host->push_data = dw_mci_push_data32;
4058 host->pull_data = dw_mci_pull_data32;
4060 host->data_shift = 2;
4063 /* Reset all blocks */
4064 if (!dw_mci_ctrl_all_reset(host))
4067 host->dma_ops = host->pdata->dma_ops;
4068 dw_mci_init_dma(host);
4070 /* Clear the interrupts for the host controller */
4071 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4072 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4074 /* Put in max timeout */
4075 mci_writel(host, TMOUT, 0xFFFFFFFF);
4078 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
4079 * Tx Mark = fifo_size / 2 DMA Size = 8
4081 if (!host->pdata->fifo_depth) {
4083 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4084 * have been overwritten by the bootloader, just like we're
4085 * about to do, so if you know the value for your hardware, you
4086 * should put it in the platform data.
4088 fifo_size = mci_readl(host, FIFOTH);
4089 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4091 fifo_size = host->pdata->fifo_depth;
4093 host->fifo_depth = fifo_size;
4095 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4096 mci_writel(host, FIFOTH, host->fifoth_val);
4098 /* disable clock to CIU */
4099 mci_writel(host, CLKENA, 0);
4100 mci_writel(host, CLKSRC, 0);
4102 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4103 host->card_workqueue = alloc_workqueue("dw-mci-card",
4104 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4105 if (!host->card_workqueue) {
4109 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4110 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4111 host->irq_flags, "dw-mci", host);
4115 if (host->pdata->num_slots)
4116 host->num_slots = host->pdata->num_slots;
4118 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4120 /* We need at least one slot to succeed */
4121 for (i = 0; i < host->num_slots; i++) {
4122 ret = dw_mci_init_slot(host, i);
4124 dev_dbg(host->dev, "slot %d init failed\n", i);
4130 * Enable interrupts for command done, data over, data empty, card det,
4131 * receive ready and error such as transmit, receive timeout, crc error
4133 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4134 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4135 SDMMC_INT_VSI | SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4136 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4137 !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4138 regs |= SDMMC_INT_CD;
4140 mci_writel(host, INTMASK, regs);
4142 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4144 dev_info(host->dev, "DW MMC controller at irq %d, "
4145 "%d bit host data width, "
4147 host->irq, width, fifo_size);
4150 dev_info(host->dev, "%d slots initialized\n", init_slots);
4152 dev_dbg(host->dev, "attempted to initialize %d slots, "
4153 "but failed on all\n", host->num_slots);
4158 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4159 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4164 destroy_workqueue(host->card_workqueue);
4167 if (host->use_dma && host->dma_ops->exit)
4168 host->dma_ops->exit(host);
4171 regulator_disable(host->vmmc);
4172 regulator_put(host->vmmc);
4176 if (!IS_ERR(host->clk_mmc))
4177 clk_disable_unprepare(host->clk_mmc);
4179 if (!IS_ERR(host->hclk_mmc))
4180 clk_disable_unprepare(host->hclk_mmc);
4183 EXPORT_SYMBOL(dw_mci_probe);
4185 void dw_mci_remove(struct dw_mci *host)
4187 struct mmc_host *mmc = host->mmc;
4188 struct dw_mci_slot *slot = mmc_priv(mmc);
4191 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4192 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4194 for(i = 0; i < host->num_slots; i++){
4195 dev_dbg(host->dev, "remove slot %d\n", i);
4197 dw_mci_cleanup_slot(host->slot[i], i);
4200 /* disable clock to CIU */
4201 mci_writel(host, CLKENA, 0);
4202 mci_writel(host, CLKSRC, 0);
4204 destroy_workqueue(host->card_workqueue);
4205 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4206 unregister_pm_notifier(&host->mmc->pm_notify);
4208 if (host->use_dma && host->dma_ops->exit)
4209 host->dma_ops->exit(host);
4211 if (gpio_is_valid(slot->cd_gpio))
4212 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4215 regulator_disable(host->vmmc);
4216 regulator_put(host->vmmc);
4218 if (!IS_ERR(host->clk_mmc))
4219 clk_disable_unprepare(host->clk_mmc);
4221 if (!IS_ERR(host->hclk_mmc))
4222 clk_disable_unprepare(host->hclk_mmc);
4223 if (!IS_ERR(host->hpclk_mmc))
4224 clk_disable_unprepare(host->hpclk_mmc);
4226 EXPORT_SYMBOL(dw_mci_remove);
4230 #ifdef CONFIG_PM_SLEEP
4232 * TODO: we should probably disable the clock to the card in the suspend path.
4234 extern int get_wifi_chip_type(void);
4235 int dw_mci_suspend(struct dw_mci *host)
4237 int present = dw_mci_get_cd(host->mmc);
4239 if((host->mmc->restrict_caps &
4240 RESTRICT_CARD_TYPE_SDIO) &&
4241 (get_wifi_chip_type() == WIFI_ESP8089 ||
4242 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4246 regulator_disable(host->vmmc);
4248 /* Only for sdmmc controller */
4249 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4250 disable_irq(host->irq);
4252 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4253 MMC_DBG_ERR_FUNC(host->mmc,
4254 "Idle pinctrl setting failed! [%s]",
4255 mmc_hostname(host->mmc));
4258 /* Soc rk3126/3036 already in gpio_cd mode */
4259 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4260 dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4261 enable_irq_wake(host->mmc->slot.cd_irq);
4265 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4266 mci_writel(host, INTMASK, 0x00);
4267 mci_writel(host, CTRL, 0x00);
4269 if (host->rst_ops &&
4270 host->rst_ops->pre_suspend)
4271 host->rst_ops->pre_suspend(host);
4275 EXPORT_SYMBOL(dw_mci_suspend);
4277 int dw_mci_resume(struct dw_mci *host)
4281 struct dw_mci_slot *slot;
4282 int present = dw_mci_get_cd(host->mmc);
4284 if (host->rst_ops &&
4285 host->rst_ops->post_resume)
4286 host->rst_ops->post_resume(host);
4289 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4290 (get_wifi_chip_type() == WIFI_ESP8089 ||
4291 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4294 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4295 slot = mmc_priv(host->mmc);
4296 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4300 /*only for sdmmc controller*/
4301 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4302 /* Soc rk3126/3036 already in gpio_cd mode */
4303 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4304 disable_irq_wake(host->mmc->slot.cd_irq);
4305 mmc_gpio_free_cd(host->mmc);
4309 if (!IS_ERR(host->pins_udbg)) {
4310 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4311 MMC_DBG_ERR_FUNC(host->mmc,
4312 "Idle pinctrl setting failed! [%s]",
4313 mmc_hostname(host->mmc));
4314 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4315 MMC_DBG_ERR_FUNC(host->mmc,
4316 "Udbg pinctrl setting failed! [%s]",
4317 mmc_hostname(host->mmc));
4319 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4320 MMC_DBG_ERR_FUNC(host->mmc,
4321 "Default pinctrl setting failed! [%s]",
4322 mmc_hostname(host->mmc));
4325 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4326 MMC_DBG_ERR_FUNC(host->mmc,
4327 "Default pinctrl setting failed! [%s]",
4328 mmc_hostname(host->mmc));
4333 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4334 else if(cpu_is_rk3036())
4335 grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4336 else if(cpu_is_rk312x())
4337 /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4338 grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4341 ret = regulator_enable(host->vmmc);
4344 "failed to enable regulator: %d\n", ret);
4349 if(!dw_mci_ctrl_all_reset(host)){
4354 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
4355 if(host->use_dma && host->dma_ops->init)
4356 host->dma_ops->init(host);
4359 * Restore the initial value at FIFOTH register
4360 * And Invalidate the prev_blksz with zero
4362 mci_writel(host, FIFOTH, host->fifoth_val);
4363 host->prev_blksz = 0;
4364 /* Put in max timeout */
4365 mci_writel(host, TMOUT, 0xFFFFFFFF);
4367 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4368 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4369 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4371 if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4372 regs |= SDMMC_INT_CD;
4374 mci_writel(host, INTMASK, regs);
4375 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4377 /*only for sdmmc controller*/
4378 if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)){
4379 enable_irq(host->irq);
4382 for(i = 0; i < host->num_slots; i++){
4383 struct dw_mci_slot *slot = host->slot[i];
4386 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4387 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4388 dw_mci_setup_bus(slot, true);
4394 EXPORT_SYMBOL(dw_mci_resume);
4395 #endif /* CONFIG_PM_SLEEP */
4397 static int __init dw_mci_init(void)
4399 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4400 pr_info("MHSC version = %s\n", RK_SDMMC_DRIVER_VERSION);
4404 static void __exit dw_mci_exit(void)
4408 module_init(dw_mci_init);
4409 module_exit(dw_mci_exit);
4411 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4412 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4413 MODULE_LICENSE("GPL v2");