2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 * Copyright (C) 2014 - 2015 Fuzhou Rockchip Electronics Co.Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/blkdev.h>
16 #include <linux/clk.h>
17 #include <linux/debugfs.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/suspend.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/card.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/mmc/rk_mmc.h>
39 #include <linux/bitops.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/workqueue.h>
43 #include <linux/of_gpio.h>
44 #include <linux/mmc/slot-gpio.h>
45 #include <linux/clk-private.h>
46 #include <linux/rockchip/cpu.h>
47 #include <linux/rfkill-wlan.h>
48 #include <linux/mfd/syscon.h>
49 #include <linux/regmap.h>
50 #include <linux/log2.h>
52 #include "rk_sdmmc_dbg.h"
53 #include <linux/regulator/rockchip_io_vol_domain.h>
54 #include "../../clk/rockchip/clk-ops.h"
56 #define RK_SDMMC_DRIVER_VERSION "Ver 2.00 2015-06-10"
58 /* Common flag combinations */
59 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
62 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
64 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
65 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
66 #define DW_MCI_SEND_STATUS 1
67 #define DW_MCI_RECV_STATUS 2
68 #define DW_MCI_DMA_THRESHOLD 16
69 #define DW_MCI_FREQ_MAX 50000000 /* unit: HZ */
70 #define DW_MCI_FREQ_MIN 300000 /* unit: HZ */
72 /* Max is 250ms showed in Spec */
73 #define SDMMC_DATA_TIMEOUT_SD 500
74 #define SDMMC_DATA_TIMEOUT_SDIO 250
75 #define SDMMC_DATA_TIMEOUT_EMMC 2500
76 #define SDMMC_CMD_RTO_MAX_HOLD 200
77 #define SDMMC_WAIT_FOR_UNBUSY 2500
79 #define DW_REGS_SIZE (0x0098 + 4)
80 #define DW_REGS_NUM (0x0098 / 4)
82 #ifdef CONFIG_MMC_DW_IDMAC
83 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
84 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
85 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
89 u32 des0; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
98 u32 des1; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
102 u32 des2; /* buffer 1 physical address */
104 u32 des3; /* buffer 2 physical address */
106 #endif /* CONFIG_MMC_DW_IDMAC */
109 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
110 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
111 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
112 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
113 extern void rk_send_wakeup_key(void);
115 #if defined(CONFIG_DEBUG_FS)
116 static int dw_mci_req_show(struct seq_file *s, void *v)
118 struct dw_mci_slot *slot = s->private;
119 struct mmc_request *mrq;
120 struct mmc_command *cmd;
121 struct mmc_command *stop;
122 struct mmc_data *data;
124 /* Make sure we get a consistent snapshot */
125 spin_lock_bh(&slot->host->lock);
135 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
136 cmd->opcode, cmd->arg, cmd->flags,
137 cmd->resp[0], cmd->resp[1], cmd->resp[2],
138 cmd->resp[2], cmd->error);
140 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
141 data->bytes_xfered, data->blocks,
142 data->blksz, data->flags, data->error);
145 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
146 stop->opcode, stop->arg, stop->flags,
147 stop->resp[0], stop->resp[1], stop->resp[2],
148 stop->resp[2], stop->error);
151 spin_unlock_bh(&slot->host->lock);
156 static int dw_mci_req_open(struct inode *inode, struct file *file)
158 return single_open(file, dw_mci_req_show, inode->i_private);
161 static const struct file_operations dw_mci_req_fops = {
162 .owner = THIS_MODULE,
163 .open = dw_mci_req_open,
166 .release = single_release,
169 static int dw_mci_regs_show(struct seq_file *s, void *v)
171 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
172 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
173 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
174 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
175 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
176 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
181 static int dw_mci_regs_open(struct inode *inode, struct file *file)
183 return single_open(file, dw_mci_regs_show, inode->i_private);
186 static const struct file_operations dw_mci_regs_fops = {
187 .owner = THIS_MODULE,
188 .open = dw_mci_regs_open,
191 .release = single_release,
194 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
196 struct mmc_host *mmc = slot->mmc;
197 struct dw_mci *host = slot->host;
201 root = mmc->debugfs_root;
205 node = debugfs_create_file("regs", S_IRUSR, root, host,
210 node = debugfs_create_file("req", S_IRUSR, root, slot,
215 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
219 node = debugfs_create_x32("pending_events", S_IRUSR, root,
220 (u32 *)&host->pending_events);
224 node = debugfs_create_x32("completed_events", S_IRUSR, root,
225 (u32 *)&host->completed_events);
232 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
234 #endif /* defined(CONFIG_DEBUG_FS) */
236 static void dw_mci_set_timeout(struct dw_mci *host)
238 /* timeout (maximum) */
239 mci_writel(host, TMOUT, 0xffffffff);
242 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
244 struct mmc_data *data;
245 struct dw_mci_slot *slot = mmc_priv(mmc);
246 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
248 cmd->error = -EINPROGRESS;
252 if (cmdr == MMC_STOP_TRANSMISSION)
253 cmdr |= SDMMC_CMD_STOP;
255 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
257 if (cmd->flags & MMC_RSP_PRESENT) {
258 /* We expect a response, so set this bit */
259 cmdr |= SDMMC_CMD_RESP_EXP;
260 if (cmd->flags & MMC_RSP_136)
261 cmdr |= SDMMC_CMD_RESP_LONG;
264 if (cmd->flags & MMC_RSP_CRC)
265 cmdr |= SDMMC_CMD_RESP_CRC;
269 cmdr |= SDMMC_CMD_DAT_EXP;
270 if (data->flags & MMC_DATA_STREAM)
271 cmdr |= SDMMC_CMD_STRM_MODE;
272 if (data->flags & MMC_DATA_WRITE)
273 cmdr |= SDMMC_CMD_DAT_WR;
276 if (drv_data && drv_data->prepare_command)
277 drv_data->prepare_command(slot->host, &cmdr);
282 static void dw_mci_start_command(struct dw_mci *host,
283 struct mmc_command *cmd, u32 cmd_flags)
285 struct dw_mci_slot *slot = host->slot[0];
287 host->pre_cmd = host->cmd;
290 "start command: ARGR=0x%08x CMDR=0x%08x\n",
291 cmd->arg, cmd_flags);
293 if(SD_SWITCH_VOLTAGE == cmd->opcode){
294 /*confirm non-low-power mode*/
295 mci_writel(host, CMDARG, 0);
296 dw_mci_disable_low_power(slot);
298 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
299 __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
301 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
304 mci_writel(host, CMDARG, cmd->arg);
307 /* Fix the value to 1 in current soc */
308 if(host->mmc->hold_reg_flag)
309 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
311 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
315 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
317 dw_mci_start_command(host, data->stop, host->stop_cmdr);
320 /* DMA interface functions */
321 static void dw_mci_stop_dma(struct dw_mci *host)
323 if (host->using_dma) {
324 /* Fixme: No need to terminate edma, may cause flush op */
325 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
326 host->dma_ops->stop(host);
327 host->dma_ops->cleanup(host);
330 /* Data transfer was stopped by the interrupt handler */
331 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
334 static int dw_mci_get_dma_dir(struct mmc_data *data)
336 if (data->flags & MMC_DATA_WRITE)
337 return DMA_TO_DEVICE;
339 return DMA_FROM_DEVICE;
342 #ifdef CONFIG_MMC_DW_IDMAC
343 static void dw_mci_dma_cleanup(struct dw_mci *host)
345 struct mmc_data *data = host->data;
348 if (!data->host_cookie)
349 dma_unmap_sg(host->dev,
352 dw_mci_get_dma_dir(data));
355 static void dw_mci_idmac_reset(struct dw_mci *host)
357 u32 bmod = mci_readl(host, BMOD);
358 /* Software reset of DMA */
359 bmod |= SDMMC_IDMAC_SWRESET;
360 mci_writel(host, BMOD, bmod);
363 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
367 /* Disable and reset the IDMAC interface */
368 temp = mci_readl(host, CTRL);
369 temp &= ~SDMMC_CTRL_USE_IDMAC;
370 temp |= SDMMC_CTRL_DMA_RESET;
371 mci_writel(host, CTRL, temp);
373 /* Stop the IDMAC running */
374 temp = mci_readl(host, BMOD);
375 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
376 temp |= SDMMC_IDMAC_SWRESET;
377 mci_writel(host, BMOD, temp);
380 static void dw_mci_idmac_complete_dma(void *arg)
382 struct dw_mci *host = arg;
383 struct mmc_data *data = host->data;
385 dev_vdbg(host->dev, "DMA complete\n");
387 host->dma_ops->cleanup(host);
390 * If the card was removed, data will be NULL. No point in trying to
391 * send the stop command or waiting for NBUSY in this case.
394 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
395 tasklet_schedule(&host->tasklet);
399 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
403 struct idmac_desc *desc = host->sg_cpu;
405 for (i = 0; i < sg_len; i++, desc++) {
406 unsigned int length = sg_dma_len(&data->sg[i]);
407 u32 mem_addr = sg_dma_address(&data->sg[i]);
409 /* Set the OWN bit and disable interrupts for this descriptor */
410 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
413 IDMAC_SET_BUFFER1_SIZE(desc, length);
415 /* Physical address to DMA to/from */
416 desc->des2 = mem_addr;
419 /* Set first descriptor */
421 desc->des0 |= IDMAC_DES0_FD;
423 /* Set last descriptor */
424 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
425 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
426 desc->des0 |= IDMAC_DES0_LD;
431 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
435 dw_mci_translate_sglist(host, host->data, sg_len);
437 /* Select IDMAC interface */
438 temp = mci_readl(host, CTRL);
439 temp |= SDMMC_CTRL_USE_IDMAC;
440 mci_writel(host, CTRL, temp);
444 /* Enable the IDMAC */
445 temp = mci_readl(host, BMOD);
446 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
447 mci_writel(host, BMOD, temp);
449 /* Start it running */
450 mci_writel(host, PLDMND, 1);
453 static int dw_mci_idmac_init(struct dw_mci *host)
455 struct idmac_desc *p;
458 /* Number of descriptors in the ring buffer */
459 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
461 /* Forward link the descriptor list */
462 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
463 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
466 /* Set the last descriptor as the end-of-ring descriptor */
467 p->des3 = host->sg_dma;
468 p->des0 = IDMAC_DES0_ER;
470 dw_mci_idmac_reset(host);
472 /* Mask out interrupts - get Tx & Rx complete only */
473 mci_writel(host, IDSTS, IDMAC_INT_CLR);
474 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
477 /* Set the descriptor base address */
478 mci_writel(host, DBADDR, host->sg_dma);
482 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
483 .init = dw_mci_idmac_init,
484 .start = dw_mci_idmac_start_dma,
485 .stop = dw_mci_idmac_stop_dma,
486 .complete = dw_mci_idmac_complete_dma,
487 .cleanup = dw_mci_dma_cleanup,
491 static void dw_mci_edma_cleanup(struct dw_mci *host)
493 struct mmc_data *data = host->data;
496 if (!data->host_cookie)
497 dma_unmap_sg(host->dev,
498 data->sg, data->sg_len,
499 dw_mci_get_dma_dir(data));
502 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
504 dmaengine_terminate_all(host->dms->ch);
507 static void dw_mci_edmac_complete_dma(void *arg)
509 struct dw_mci *host = arg;
510 struct mmc_data *data = host->data;
512 dev_vdbg(host->dev, "DMA complete\n");
515 if(data->flags & MMC_DATA_READ)
516 /* Invalidate cache after read */
517 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
518 data->sg_len, DMA_FROM_DEVICE);
520 host->dma_ops->cleanup(host);
523 * If the card was removed, data will be NULL. No point in trying to
524 * send the stop command or waiting for NBUSY in this case.
527 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
528 tasklet_schedule(&host->tasklet);
532 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
534 struct dma_slave_config slave_config;
535 struct dma_async_tx_descriptor *desc = NULL;
536 struct scatterlist *sgl = host->data->sg;
537 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
538 u32 sg_elems = host->data->sg_len;
539 u32 fifoth_val, mburst;
541 u32 idx, rx_wmark, tx_wmark;
544 /* Set external dma config: burst size, burst width*/
545 slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
546 slave_config.src_addr = slave_config.dst_addr;
547 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
548 slave_config.src_addr_width = slave_config.dst_addr_width;
550 /* Match FIFO dma burst MSIZE with external dma config*/
551 fifoth_val = mci_readl(host, FIFOTH);
552 mburst = mszs[(fifoth_val >> 28) & 0x7];
554 /* Edmac limit burst to 16, but work around for rk3036 to 8 */
555 if (unlikely(cpu_is_rk3036()))
560 if (mburst > burst_limit) {
561 mburst = burst_limit;
562 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
564 rx_wmark = mszs[idx] - 1;
565 tx_wmark = (host->fifo_depth) / 2;
566 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
568 mci_writel(host, FIFOTH, fifoth_val);
571 slave_config.dst_maxburst = mburst;
572 slave_config.src_maxburst = slave_config.dst_maxburst;
574 if(host->data->flags & MMC_DATA_WRITE){
575 slave_config.direction = DMA_MEM_TO_DEV;
576 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
579 "Error in dw_mci edmac write configuration.\n");
583 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
584 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
587 "Cannot prepare slave write sg the dw_mci edmac!\n");
591 /* Set dw_mci_edmac_complete_dma as callback */
592 desc->callback = dw_mci_edmac_complete_dma;
593 desc->callback_param = (void *)host;
594 dmaengine_submit(desc);
596 /* Flush cache before write */
597 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
598 sg_elems, DMA_TO_DEVICE);
599 dma_async_issue_pending(host->dms->ch);
602 slave_config.direction = DMA_DEV_TO_MEM;
603 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
606 "Error in dw_mci edmac read configuration.\n");
609 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
610 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
613 "Cannot prepare slave read sg for the dw_mci edmac!\n");
616 /* set dw_mci_edmac_complete_dma as callback */
617 desc->callback = dw_mci_edmac_complete_dma;
618 desc->callback_param = (void *)host;
619 dmaengine_submit(desc);
620 dma_async_issue_pending(host->dms->ch);
624 static int dw_mci_edmac_init(struct dw_mci *host)
628 /* Request external dma channel, SHOULD decide chn in dts */
630 host->dms = (struct dw_mci_dma_slave *)kzalloc
631 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
632 if (NULL == host->dms) {
633 dev_err(host->dev, "No enough memory to alloc dms.\n");
637 host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
638 if (!host->dms->ch) {
640 "Failed to get external DMA channel %d\n",
641 host->dms->ch->chan_id);
650 static void dw_mci_edmac_exit(struct dw_mci *host)
652 if (NULL != host->dms) {
653 if (NULL != host->dms->ch) {
654 dma_release_channel(host->dms->ch);
655 host->dms->ch = NULL;
662 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
663 .init = dw_mci_edmac_init,
664 .exit = dw_mci_edmac_exit,
665 .start = dw_mci_edmac_start_dma,
666 .stop = dw_mci_edmac_stop_dma,
667 .complete = dw_mci_edmac_complete_dma,
668 .cleanup = dw_mci_edma_cleanup,
670 #endif /* CONFIG_MMC_DW_IDMAC */
672 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
673 struct mmc_data *data,
676 struct scatterlist *sg;
677 unsigned int i, sg_len;
679 if (!next && data->host_cookie)
680 return data->host_cookie;
683 * We don't do DMA on "complex" transfers, i.e. with
684 * non-word-aligned buffers or lengths. Also, we don't bother
685 * with all the DMA setup overhead for short transfers.
687 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
693 for_each_sg(data->sg, sg, data->sg_len, i) {
694 if (sg->offset & 3 || sg->length & 3)
698 sg_len = dma_map_sg(host->dev,
701 dw_mci_get_dma_dir(data));
706 data->host_cookie = sg_len;
711 static void dw_mci_pre_req(struct mmc_host *mmc,
712 struct mmc_request *mrq,
715 struct dw_mci_slot *slot = mmc_priv(mmc);
716 struct mmc_data *data = mrq->data;
718 if (!slot->host->use_dma || !data)
721 if (data->host_cookie) {
722 data->host_cookie = 0;
726 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
727 data->host_cookie = 0;
730 static void dw_mci_post_req(struct mmc_host *mmc,
731 struct mmc_request *mrq,
734 struct dw_mci_slot *slot = mmc_priv(mmc);
735 struct mmc_data *data = mrq->data;
737 if (!slot->host->use_dma || !data)
740 if (data->host_cookie)
741 dma_unmap_sg(slot->host->dev,
744 dw_mci_get_dma_dir(data));
745 data->host_cookie = 0;
748 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
750 #ifdef CONFIG_MMC_DW_IDMAC
751 unsigned int blksz = data->blksz;
752 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
753 u32 fifo_width = 1 << host->data_shift;
754 u32 blksz_depth = blksz / fifo_width, fifoth_val;
755 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
756 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
758 tx_wmark = (host->fifo_depth) / 2;
759 tx_wmark_invers = host->fifo_depth - tx_wmark;
763 * if blksz is not a multiple of the FIFO width
765 if (blksz % fifo_width) {
772 if (!((blksz_depth % mszs[idx]) ||
773 (tx_wmark_invers % mszs[idx]))) {
775 rx_wmark = mszs[idx] - 1;
780 * If idx is '0', it won't be tried
781 * Thus, initial values are uesed
784 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
785 mci_writel(host, FIFOTH, fifoth_val);
790 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
792 unsigned int blksz = data->blksz;
793 u32 blksz_depth, fifo_depth;
796 WARN_ON(!(data->flags & MMC_DATA_READ));
798 if (host->timing != MMC_TIMING_MMC_HS200 &&
799 host->timing != MMC_TIMING_UHS_SDR104)
802 blksz_depth = blksz / (1 << host->data_shift);
803 fifo_depth = host->fifo_depth;
805 if (blksz_depth > fifo_depth)
809 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
810 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
811 * Currently just choose blksz.
814 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
818 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
821 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
829 /* If we don't have a channel, we can't do DMA */
833 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
835 /* Fixme: No need terminate edma, may cause flush op */
836 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
837 host->dma_ops->stop(host);
844 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
845 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
849 * Decide the MSIZE and RX/TX Watermark.
850 * If current block size is same with previous size,
851 * no need to update fifoth.
853 if (host->prev_blksz != data->blksz)
854 dw_mci_adjust_fifoth(host, data);
857 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
859 /* Enable the DMA interface */
860 temp = mci_readl(host, CTRL);
861 temp |= SDMMC_CTRL_DMA_ENABLE;
862 mci_writel(host, CTRL, temp);
864 /* Disable RX/TX IRQs, let DMA handle it */
865 spin_lock_irqsave(&host->slock, flags);
866 temp = mci_readl(host, INTMASK);
867 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
868 mci_writel(host, INTMASK, temp);
869 spin_unlock_irqrestore(&host->slock, flags);
871 host->dma_ops->start(host, sg_len);
876 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
881 data->error = -EINPROGRESS;
883 //WARN_ON(host->data);
888 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
890 if (data->flags & MMC_DATA_READ) {
891 host->dir_status = DW_MCI_RECV_STATUS;
892 dw_mci_ctrl_rd_thld(host, data);
894 host->dir_status = DW_MCI_SEND_STATUS;
897 MMC_DBG_INFO_FUNC(host->mmc,
898 "Dw_mci_submit_data, blocks = %d, blksz = %d [%s]",
899 data->blocks, data->blksz, mmc_hostname(host->mmc));
901 if (dw_mci_submit_data_dma(host, data)) {
902 int flags = SG_MITER_ATOMIC;
903 if (host->data->flags & MMC_DATA_READ)
904 flags |= SG_MITER_TO_SG;
906 flags |= SG_MITER_FROM_SG;
908 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
910 host->part_buf_start = 0;
911 host->part_buf_count = 0;
913 spin_lock_irqsave(&host->slock, flag);
914 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
915 temp = mci_readl(host, INTMASK);
916 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
917 mci_writel(host, INTMASK, temp);
918 spin_unlock_irqrestore(&host->slock, flag);
920 temp = mci_readl(host, CTRL);
921 temp &= ~SDMMC_CTRL_DMA_ENABLE;
922 mci_writel(host, CTRL, temp);
925 * Use the initial fifoth_val for PIO mode.
926 * If next issued data may be transfered by DMA mode,
927 * prev_blksz should be invalidated.
929 mci_writel(host, FIFOTH, host->fifoth_val);
930 host->prev_blksz = 0;
933 * Keep the current block size.
934 * It will be used to decide whether to update
935 * fifoth register next time.
937 host->prev_blksz = data->blksz;
941 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
943 struct dw_mci *host = slot->host;
944 unsigned long timeout = jiffies + msecs_to_jiffies(500);
945 unsigned int cmd_status = 0;
947 #ifdef SDMMC_WAIT_FOR_UNBUSY
949 timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
951 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
953 ret = time_before(jiffies, timeout);
954 cmd_status = mci_readl(host, STATUS);
956 (SDMMC_STAUTS_DATA_BUSY |
957 SDMMC_STAUTS_MC_BUSY)))
962 MMC_DBG_ERR_FUNC(host->mmc,
963 "mci_send_cmd: wait for unbusy timeout! [%s]",
964 mmc_hostname(host->mmc));
968 mci_writel(host, CMDARG, arg);
970 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
971 if(cmd & SDMMC_CMD_UPD_CLK)
972 timeout = jiffies + msecs_to_jiffies(50);
974 timeout = jiffies + msecs_to_jiffies(500);
976 while (time_before(jiffies, timeout)) {
977 cmd_status = mci_readl(host, CMD);
978 if (!(cmd_status & SDMMC_CMD_START))
982 dev_err(&slot->mmc->class_dev,
983 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
984 cmd, arg, cmd_status);
987 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
989 struct dw_mci *host = slot->host;
990 unsigned int tempck,clock = slot->clock;
995 MMC_DBG_INFO_FUNC(host->mmc,
996 "%s: clock=%d, current_speed=%d, bus_hz=%d, forc=%d[%s]\n",
997 __FUNCTION__, clock, host->current_speed, host->bus_hz,
998 force_clkinit, mmc_hostname(host->mmc));
1001 mci_writel(host, CLKENA, 0);
1002 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1003 if(host->svi_flags == 0)
1004 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1006 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1008 } else if (clock != host->current_speed || force_clkinit) {
1009 div = host->bus_hz / clock;
1010 if (host->bus_hz % clock && host->bus_hz > clock)
1012 * move the + 1 after the divide to prevent
1013 * over-clocking the card.
1017 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1019 if ((clock << div) != slot->__clk_old || force_clkinit) {
1020 tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1021 dev_info(&slot->mmc->class_dev,
1022 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1023 slot->id, host->bus_hz, clock,
1026 host->set_speed = tempck;
1027 host->set_div = div;
1031 mci_writel(host, CLKENA, 0);
1032 mci_writel(host, CLKSRC, 0);
1036 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1038 if(clock <= 400*1000){
1039 MMC_DBG_BOOT_FUNC(host->mmc,
1040 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1041 clock * 2, mmc_hostname(host->mmc));
1042 /* clk_mmc will change parents to 24MHz xtal*/
1043 clk_set_rate(host->clk_mmc, clock * 2);
1046 host->set_div = div;
1050 MMC_DBG_BOOT_FUNC(host->mmc,
1051 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1052 mmc_hostname(host->mmc));
1055 MMC_DBG_ERR_FUNC(host->mmc,
1056 "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1057 mmc_hostname(host->mmc));
1059 host->set_div = div;
1060 host->bus_hz = host->set_speed * 2;
1061 MMC_DBG_BOOT_FUNC(host->mmc,
1062 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1063 div, host->bus_hz, mmc_hostname(host->mmc));
1065 /* BUG may be here, come on, Linux BSP engineer looks!
1066 FIXME: HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1067 WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1068 some oops happened like that:
1069 mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1070 rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1071 rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1072 mmc0: new high speed DDR MMC card at address 0001
1073 mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1075 mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1076 mmcblk0: retrying using single block read
1077 mmcblk0: error -110 sending status command, retrying
1079 We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1082 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1083 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1086 host->set_div = div;
1087 host->bus_hz = host->set_speed * 2;
1088 MMC_DBG_BOOT_FUNC(host->mmc,
1089 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1090 div, host->bus_hz, mmc_hostname(host->mmc));
1093 if (host->verid < DW_MMC_240A)
1094 clk_set_rate(host->clk_mmc,(host->bus_hz));
1096 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1102 /* set clock to desired speed */
1103 mci_writel(host, CLKDIV, div);
1107 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1109 /* enable clock; only low power if no SDIO */
1110 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1112 if (host->verid < DW_MMC_240A)
1113 sdio_int = SDMMC_INT_SDIO(slot->id);
1115 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1117 if (!(mci_readl(host, INTMASK) & sdio_int))
1118 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1119 mci_writel(host, CLKENA, clk_en_a);
1123 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1124 /* keep the clock with reflecting clock dividor */
1125 slot->__clk_old = clock << div;
1128 host->current_speed = clock;
1130 if(slot->ctype != slot->pre_ctype)
1131 MMC_DBG_BOOT_FUNC(host->mmc,
1132 "Bus speed=%dHz,Bus width=%s.[%s]",
1134 (slot->ctype == SDMMC_CTYPE_4BIT) ? "4bits" : "8bits",
1135 mmc_hostname(host->mmc));
1137 slot->pre_ctype = slot->ctype;
1139 /* Set the current slot bus width */
1140 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1143 extern struct mmc_card *this_card;
1144 static void dw_mci_wait_unbusy(struct dw_mci *host)
1146 unsigned int timeout = SDMMC_DATA_TIMEOUT_SDIO;
1147 unsigned long time_loop;
1148 unsigned int status;
1149 unsigned int tmo = 300000;
1150 /* Secure erase flag */
1153 MMC_DBG_INFO_FUNC(host->mmc,
1154 "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1156 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1157 if (host->cmd && (host->cmd->opcode == MMC_ERASE) && this_card) {
1158 /* Special care for (secure)erase timeout calculation */
1159 if ((host->cmd->arg & (0x1 << 31)) == 1)
1162 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1164 (timeout = (this_card->ext_csd.hc_erase_timeout) *
1165 tmo * (this_card->ext_csd.sec_erase_mult)) :
1166 (timeout = (this_card->ext_csd.hc_erase_timeout) * tmo);
1169 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1170 timeout = SDMMC_DATA_TIMEOUT_EMMC;
1171 } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1172 timeout = SDMMC_DATA_TIMEOUT_SD;
1175 time_loop = jiffies + msecs_to_jiffies(timeout);
1177 status = mci_readl(host, STATUS);
1178 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1180 } while (time_before(jiffies, time_loop));
1183 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1186 * 0--status is busy.
1187 * 1--status is unbusy.
1189 int dw_mci_card_busy(struct mmc_host *mmc)
1191 struct dw_mci_slot *slot = mmc_priv(mmc);
1192 struct dw_mci *host = slot->host;
1194 MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1195 host->svi_flags, mmc_hostname(host->mmc));
1198 if(host->svi_flags == 0){
1200 host->svi_flags = 1;
1201 return host->svi_flags;
1204 host->svi_flags = 0;
1205 return host->svi_flags;
1211 static void __dw_mci_start_request(struct dw_mci *host,
1212 struct dw_mci_slot *slot,
1213 struct mmc_command *cmd)
1215 struct mmc_request *mrq;
1216 struct mmc_data *data;
1220 if (host->pdata->select_slot)
1221 host->pdata->select_slot(slot->id);
1223 host->cur_slot = slot;
1226 dw_mci_wait_unbusy(host);
1228 host->pending_events = 0;
1229 host->completed_events = 0;
1230 host->data_status = 0;
1234 dw_mci_set_timeout(host);
1235 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1236 mci_writel(host, BLKSIZ, data->blksz);
1239 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1241 /* this is the first command, send the initialization clock */
1242 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1243 cmdflags |= SDMMC_CMD_INIT;
1246 dw_mci_submit_data(host, data);
1250 dw_mci_start_command(host, cmd, cmdflags);
1253 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1256 static void dw_mci_start_request(struct dw_mci *host,
1257 struct dw_mci_slot *slot)
1259 struct mmc_request *mrq = slot->mrq;
1260 struct mmc_command *cmd;
1262 MMC_DBG_INFO_FUNC(host->mmc,
1263 " Begin to start the new request. cmd=%d(arg=0x%x)[%s]",
1264 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1266 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1267 __dw_mci_start_request(host, slot, cmd);
1270 /* must be called with host->lock held */
1271 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1272 struct mmc_request *mrq)
1274 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1279 if (host->state == STATE_IDLE) {
1280 host->state = STATE_SENDING_CMD;
1281 dw_mci_start_request(host, slot);
1283 list_add_tail(&slot->queue_node, &host->queue);
1287 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1289 struct dw_mci_slot *slot = mmc_priv(mmc);
1290 struct dw_mci *host = slot->host;
1295 * The check for card presence and queueing of the request must be
1296 * atomic, otherwise the card could be removed in between and the
1297 * request wouldn't fail until another card was inserted.
1299 spin_lock_bh(&host->lock);
1301 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1302 spin_unlock_bh(&host->lock);
1303 mrq->cmd->error = -ENOMEDIUM;
1304 MMC_DBG_CMD_FUNC(host->mmc, "%s: no card,so reqeuest done, cmd=%d [%s]",
1305 __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1307 mmc_request_done(mmc, mrq);
1311 MMC_DBG_CMD_FUNC(host->mmc,
1312 "======>\n pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]",
1313 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1315 dw_mci_queue_request(host, slot, mrq);
1317 spin_unlock_bh(&host->lock);
1320 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1322 struct dw_mci_slot *slot = mmc_priv(mmc);
1323 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1324 struct dw_mci *host = slot->host;
1326 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1329 #ifdef SDMMC_WAIT_FOR_UNBUSY
1330 unsigned long time_loop;
1333 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1334 if(host->svi_flags == 1)
1335 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1337 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1339 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1342 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1343 printk("%d..%s: no card. [%s]\n", \
1344 __LINE__, __FUNCTION__, mmc_hostname(mmc));
1349 ret = time_before(jiffies, time_loop);
1350 regs = mci_readl(slot->host, STATUS);
1351 if (!(regs & (SDMMC_STAUTS_DATA_BUSY |
1352 SDMMC_STAUTS_MC_BUSY)))
1358 printk("slot->flags = %lu ", slot->flags);
1359 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1360 if(host->svi_flags != 1)
1363 printk("%s: wait for unbusy timeout....... STATUS = 0x%x [%s]\n",
1364 __FUNCTION__, regs, mmc_hostname(mmc));
1368 switch (ios->bus_width) {
1369 case MMC_BUS_WIDTH_4:
1370 slot->ctype = SDMMC_CTYPE_4BIT;
1372 case MMC_BUS_WIDTH_8:
1373 slot->ctype = SDMMC_CTYPE_8BIT;
1376 /* set default 1 bit mode */
1377 slot->ctype = SDMMC_CTYPE_1BIT;
1378 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1381 regs = mci_readl(slot->host, UHS_REG);
1384 if (ios->timing == MMC_TIMING_UHS_DDR50)
1385 regs |= ((0x1 << slot->id) << 16);
1387 regs &= ~((0x1 << slot->id) << 16);
1389 mci_writel(slot->host, UHS_REG, regs);
1390 slot->host->timing = ios->timing;
1393 * Use mirror of ios->clock to prevent race with mmc
1394 * core ios update when finding the minimum.
1396 slot->clock = ios->clock;
1398 if (drv_data && drv_data->set_ios)
1399 drv_data->set_ios(slot->host, ios);
1401 /* Slot specific timing and width adjustment */
1402 dw_mci_setup_bus(slot, false);
1406 switch (ios->power_mode) {
1409 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1410 if (slot->host->pdata->setpower)
1411 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1412 regs = mci_readl(slot->host, PWREN);
1413 regs |= (1 << slot->id);
1414 mci_writel(slot->host, PWREN, regs);
1417 /* Power down slot */
1418 if(slot->host->pdata->setpower)
1419 slot->host->pdata->setpower(slot->id, 0);
1420 regs = mci_readl(slot->host, PWREN);
1421 regs &= ~(1 << slot->id);
1422 mci_writel(slot->host, PWREN, regs);
1429 static int dw_mci_get_ro(struct mmc_host *mmc)
1432 struct dw_mci_slot *slot = mmc_priv(mmc);
1433 struct dw_mci_board *brd = slot->host->pdata;
1435 /* Use platform get_ro function, else try on board write protect */
1436 if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1438 else if(brd->get_ro)
1439 read_only = brd->get_ro(slot->id);
1440 else if(gpio_is_valid(slot->wp_gpio))
1441 read_only = gpio_get_value(slot->wp_gpio);
1444 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1446 dev_dbg(&mmc->class_dev, "card is %s\n",
1447 read_only ? "read-only" : "read-write");
1452 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1454 struct dw_mci_slot *slot = mmc_priv(mmc);
1455 struct dw_mci *host = slot->host;
1457 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1460 spin_lock_bh(&host->lock);
1463 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1465 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1467 spin_unlock_bh(&host->lock);
1469 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1470 if (__clk_is_enabled(host->hclk_mmc) == false)
1471 clk_prepare_enable(host->hclk_mmc);
1472 if (__clk_is_enabled(host->clk_mmc) == false)
1473 clk_prepare_enable(host->clk_mmc);
1475 if (__clk_is_enabled(host->clk_mmc) == true)
1476 clk_disable_unprepare(slot->host->clk_mmc);
1477 if (__clk_is_enabled(host->hclk_mmc) == true)
1478 clk_disable_unprepare(slot->host->hclk_mmc);
1481 mmc_detect_change(slot->mmc, 20);
1487 static int dw_mci_get_cd(struct mmc_host *mmc)
1490 struct dw_mci_slot *slot = mmc_priv(mmc);
1491 struct dw_mci_board *brd = slot->host->pdata;
1492 struct dw_mci *host = slot->host;
1493 int gpio_cd = mmc_gpio_get_cd(mmc);
1494 int force_jtag_bit, force_jtag_reg;
1498 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1499 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1500 gpio_cd = slot->cd_gpio;
1501 irq = gpio_to_irq(gpio_cd);
1502 if (gpio_is_valid(gpio_cd)) {
1503 gpio_val = gpio_get_value(gpio_cd);
1504 if (soc_is_rk3036()) {
1505 force_jtag_bit = 11;
1506 force_jtag_reg = RK312X_GRF_SOC_CON0;
1507 } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1508 force_jtag_reg = RK312X_GRF_SOC_CON0;
1512 if (gpio_val == gpio_get_value(gpio_cd)) {
1513 gpio_cd = (gpio_val == 0 ? 1 : 0);
1515 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1516 /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1517 grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1519 dw_mci_ctrl_all_reset(host);
1521 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1522 /* Really card detected: SHOULD disable force_jtag */
1523 grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1528 gpio_val = gpio_get_value(gpio_cd);
1530 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
1531 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1532 return slot->last_detect_state;
1535 dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1539 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1540 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1542 /* Use platform get_cd function, else try onboard card detect */
1543 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1545 else if (brd->get_cd)
1546 present = !brd->get_cd(slot->id);
1547 else if (!IS_ERR_VALUE(gpio_cd))
1550 present = ((mci_readl(slot->host, CDETECT) & (1 << slot->id))
1553 spin_lock_bh(&host->lock);
1555 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1556 dev_dbg(&mmc->class_dev, "card is present\n");
1558 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1559 dev_dbg(&mmc->class_dev, "card is not present\n");
1561 spin_unlock_bh(&host->lock);
1568 * Dts Should caps emmc controller with poll-hw-reset
1570 static void dw_mci_hw_reset(struct mmc_host *mmc)
1572 struct dw_mci_slot *slot = mmc_priv(mmc);
1573 struct dw_mci *host = slot->host;
1578 unsigned long timeout;
1581 /* (1) CMD12 to end any transfer in process */
1582 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1583 | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1585 if(host->mmc->hold_reg_flag)
1586 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1587 mci_writel(host, CMDARG, 0);
1589 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1591 timeout = jiffies + msecs_to_jiffies(500);
1593 ret = time_before(jiffies, timeout);
1594 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1599 MMC_DBG_ERR_FUNC(host->mmc,
1600 "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1601 __func__, mmc_hostname(host->mmc));
1603 /* (2) wait DTO, even if no response is sent back by card */
1605 timeout = jiffies + msecs_to_jiffies(5);
1607 ret = time_before(jiffies, timeout);
1608 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1609 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1615 /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1617 /* Software reset - BMOD[0] for IDMA only */
1618 regs = mci_readl(host, BMOD);
1619 regs |= SDMMC_IDMAC_SWRESET;
1620 mci_writel(host, BMOD, regs);
1621 udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1622 regs = mci_readl(host, BMOD);
1623 if(regs & SDMMC_IDMAC_SWRESET)
1624 MMC_DBG_WARN_FUNC(host->mmc,
1625 "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1626 __func__, mmc_hostname(host->mmc));
1628 /* DMA reset - CTRL[2] */
1629 regs = mci_readl(host, CTRL);
1630 regs |= SDMMC_CTRL_DMA_RESET;
1631 mci_writel(host, CTRL, regs);
1632 udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1633 regs = mci_readl(host, CTRL);
1634 if(regs & SDMMC_CTRL_DMA_RESET)
1635 MMC_DBG_WARN_FUNC(host->mmc,
1636 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1637 __func__, mmc_hostname(host->mmc));
1639 /* FIFO reset - CTRL[1] */
1640 regs = mci_readl(host, CTRL);
1641 regs |= SDMMC_CTRL_FIFO_RESET;
1642 mci_writel(host, CTRL, regs);
1643 mdelay(1); /* no timing limited, 1ms is random value */
1644 regs = mci_readl(host, CTRL);
1645 if(regs & SDMMC_CTRL_FIFO_RESET)
1646 MMC_DBG_WARN_FUNC(host->mmc,
1647 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1648 __func__, mmc_hostname(host->mmc));
1651 According to eMMC spec
1652 tRstW >= 1us ; RST_n pulse width
1653 tRSCA >= 200us ; RST_n to Command time
1654 tRSTH >= 1us ; RST_n high period
1656 mci_writel(slot->host, PWREN, 0x0);
1657 mci_writel(slot->host, RST_N, 0x0);
1659 udelay(10); /* 10us for bad quality eMMc. */
1661 mci_writel(slot->host, PWREN, 0x1);
1662 mci_writel(slot->host, RST_N, 0x1);
1664 usleep_range(500, 1000); /* at least 500(> 200us) */
1668 * Disable lower power mode.
1670 * Low power mode will stop the card clock when idle. According to the
1671 * description of the CLKENA register we should disable low power mode
1672 * for SDIO cards if we need SDIO interrupts to work.
1674 * This function is fast if low power mode is already disabled.
1676 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1678 struct dw_mci *host = slot->host;
1680 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1682 clk_en_a = mci_readl(host, CLKENA);
1684 if (clk_en_a & clken_low_pwr) {
1685 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1686 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1687 SDMMC_CMD_PRV_DAT_WAIT, 0);
1691 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1693 struct dw_mci_slot *slot = mmc_priv(mmc);
1694 struct dw_mci *host = slot->host;
1695 unsigned long flags;
1699 spin_lock_irqsave(&host->slock, flags);
1701 /* Enable/disable Slot Specific SDIO interrupt */
1702 int_mask = mci_readl(host, INTMASK);
1704 if (host->verid < DW_MMC_240A)
1705 sdio_int = SDMMC_INT_SDIO(slot->id);
1707 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1711 * Turn off low power mode if it was enabled. This is a bit of
1712 * a heavy operation and we disable / enable IRQs a lot, so
1713 * we'll leave low power mode disabled and it will get
1714 * re-enabled again in dw_mci_setup_bus().
1716 dw_mci_disable_low_power(slot);
1718 mci_writel(host, INTMASK,
1719 (int_mask | sdio_int));
1721 mci_writel(host, INTMASK,
1722 (int_mask & ~sdio_int));
1725 spin_unlock_irqrestore(&host->slock, flags);
1728 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1730 IO_DOMAIN_12 = 1200,
1731 IO_DOMAIN_18 = 1800,
1732 IO_DOMAIN_33 = 3300,
1734 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1744 MMC_DBG_ERR_FUNC(host->mmc,
1745 "%s : Not support io domain voltage [%s]\n",
1746 __FUNCTION__, mmc_hostname(host->mmc));
1749 MMC_DBG_ERR_FUNC(host->mmc,
1750 "%s : Err io domain voltage [%s]\n",
1751 __FUNCTION__, mmc_hostname(host->mmc));
1755 if (cpu_is_rk3288()) {
1756 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1757 grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1760 } else if (host->cid == DW_MCI_TYPE_RK3368) {
1761 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1762 regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1766 MMC_DBG_ERR_FUNC(host->mmc,
1767 "%s : unknown chip [%s]\n",
1768 __FUNCTION__, mmc_hostname(host->mmc));
1772 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1773 struct mmc_ios *ios)
1776 unsigned int value,uhs_reg;
1779 * Signal Voltage Switching is only applicable for Host Controllers
1782 if (host->verid < DW_MMC_240A)
1785 uhs_reg = mci_readl(host, UHS_REG);
1786 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: vol=%d.[%s]\n",
1787 __FUNCTION__, ios->signal_voltage, mmc_hostname(host->mmc));
1789 switch (ios->signal_voltage) {
1790 case MMC_SIGNAL_VOLTAGE_330:
1791 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1793 if (cpu_is_rk3288())
1794 ret = io_domain_regulator_set_voltage(
1795 host->vmmc, 3300000, 3300000);
1797 ret = regulator_set_voltage(host->vmmc,
1800 /* regulator_put(host->vmmc); */
1801 MMC_DBG_SW_VOL_FUNC(host->mmc,"%s =%dmV set 3.3 end, ret = %d\n",
1802 __func__, regulator_get_voltage(host->vmmc), ret);
1804 MMC_DBG_SW_VOL_FUNC(host->mmc,
1805 "%s: Switching to 3.3V signalling voltage "
1806 " failed\n", mmc_hostname(host->mmc));
1809 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1812 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: [%s]\n",
1813 __FUNCTION__, mmc_hostname(host->mmc));
1815 /* set High-power mode */
1816 value = mci_readl(host, CLKENA);
1817 value &= ~SDMMC_CLKEN_LOW_PWR;
1818 mci_writel(host,CLKENA , value);
1820 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1821 mci_writel(host,UHS_REG , uhs_reg);
1824 usleep_range(5000, 5500);
1826 /* 3.3V regulator output should be stable within 5 ms */
1827 uhs_reg = mci_readl(host, UHS_REG);
1828 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1831 MMC_DBG_SW_VOL_FUNC(host->mmc,
1832 "%s: 3.3V regulator output did not became stable\n",
1833 mmc_hostname(host->mmc));
1836 case MMC_SIGNAL_VOLTAGE_180:
1838 if (cpu_is_rk3288())
1839 ret = io_domain_regulator_set_voltage(
1840 host->vmmc, 1800000, 1800000);
1842 ret = regulator_set_voltage(
1843 host->vmmc, 1800000, 1800000);
1844 /* regulator_put(host->vmmc); */
1845 MMC_DBG_SW_VOL_FUNC(host->mmc,
1846 "%s =%dmV set 1.8end, ret=%d . \n",
1847 __func__, regulator_get_voltage(host->vmmc), ret);
1849 MMC_DBG_SW_VOL_FUNC(host->mmc,
1850 "%s: Switching to 1.8V signalling voltage "
1851 " failed\n", mmc_hostname(host->mmc));
1854 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1858 * Enable 1.8V Signal Enable in the Host Control2
1861 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1864 usleep_range(5000, 5500);
1865 MMC_DBG_SW_VOL_FUNC(host->mmc, "%d..%s: .[%s]\n",__LINE__,
1866 __FUNCTION__, mmc_hostname(host->mmc));
1868 /* 1.8V regulator output should be stable within 5 ms */
1869 uhs_reg = mci_readl(host, UHS_REG);
1870 if (uhs_reg & SDMMC_UHS_VOLT_REG_18)
1873 MMC_DBG_SW_VOL_FUNC(host->mmc,
1874 "%s: 1.8V regulator output did not became stable\n",
1875 mmc_hostname(host->mmc));
1878 case MMC_SIGNAL_VOLTAGE_120:
1880 if (cpu_is_rk3288())
1881 ret = io_domain_regulator_set_voltage(
1882 host->vmmc, 1200000, 1200000);
1884 ret = regulator_set_voltage(host->vmmc,
1887 MMC_DBG_SW_VOL_FUNC(host->mmc,
1888 "%s: Switching to 1.2V signalling voltage "
1889 " failed\n", mmc_hostname(host->mmc));
1895 /* No signal voltage switch required */
1901 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1902 struct mmc_ios *ios)
1904 struct dw_mci_slot *slot = mmc_priv(mmc);
1905 struct dw_mci *host = slot->host;
1908 if (host->verid < DW_MMC_240A)
1911 err = dw_mci_do_start_signal_voltage_switch(host, ios);
1917 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1919 struct dw_mci_slot *slot = mmc_priv(mmc);
1920 struct dw_mci *host = slot->host;
1921 const struct dw_mci_drv_data *drv_data = host->drv_data;
1922 struct dw_mci_tuning_data tuning_data;
1925 /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1926 if(cpu_is_rk3036() || cpu_is_rk312x())
1929 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1930 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1931 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1932 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1933 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1934 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1935 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1939 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1940 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1941 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1944 "Undefined command(%d) for tuning\n", opcode);
1948 if (drv_data && drv_data->execute_tuning)
1949 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1954 static void dw_mci_post_tmo(struct mmc_host *mmc)
1956 struct dw_mci_slot *slot = mmc_priv(mmc);
1957 struct dw_mci *host = slot->host;
1958 struct mmc_data *data;
1959 u32 ret, i, regs, cmd_flags;
1961 unsigned long timeout = 0;
1962 bool ret_timeout = true;
1965 opcode = host->mrq->cmd->opcode;
1966 host->cur_slot->mrq = NULL;
1968 host->state = STATE_IDLE;
1972 if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
1973 (opcode == MMC_SEND_TUNING_BLOCK))
1976 printk("[%s] -- Timeout recovery procedure start --\n",
1977 mmc_hostname(host->mmc));
1979 mci_writel(host, CMDARG, 0);
1981 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
1982 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1984 if (host->mmc->hold_reg_flag)
1985 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1987 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1989 timeout = jiffies + msecs_to_jiffies(500);
1991 while(ret_timeout) {
1992 ret_timeout = time_before(jiffies, timeout);
1993 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1997 if (false == ret_timeout)
1998 MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
1999 mmc_hostname(host->mmc));
2001 if (!dw_mci_ctrl_all_reset(host)) {
2006 #ifdef CONFIG_MMC_DW_IDMAC
2007 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
2008 if (host->use_dma && host->dma_ops->init)
2009 host->dma_ops->init(host);
2013 * Restore the initial value at FIFOTH register
2014 * And Invalidate the prev_blksz with zero
2016 mci_writel(host, FIFOTH, host->fifoth_val);
2017 host->prev_blksz = 0;
2018 mci_writel(host, TMOUT, 0xFFFFFFFF);
2019 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2020 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
2021 | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
2022 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2023 regs |= SDMMC_INT_CD;
2025 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2026 if (host->verid < DW_MMC_240A)
2027 sdio_int = SDMMC_INT_SDIO(0);
2029 sdio_int = SDMMC_INT_SDIO(8);
2031 if (mci_readl(host, INTMASK) & sdio_int)
2035 mci_writel(host, INTMASK, regs);
2036 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2037 for (i = 0; i < host->num_slots; i++) {
2038 struct dw_mci_slot *slot = host->slot[i];
2041 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2042 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2043 dw_mci_setup_bus(slot, true);
2046 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2048 printk("[%s] -- Timeout recovery procedure finished --\n",
2049 mmc_hostname(host->mmc));
2052 static const struct mmc_host_ops dw_mci_ops = {
2053 .request = dw_mci_request,
2054 .pre_req = dw_mci_pre_req,
2055 .post_req = dw_mci_post_req,
2056 .set_ios = dw_mci_set_ios,
2057 .get_ro = dw_mci_get_ro,
2058 .get_cd = dw_mci_get_cd,
2059 .set_sdio_status = dw_mci_set_sdio_status,
2060 .hw_reset = dw_mci_hw_reset,
2061 .enable_sdio_irq = dw_mci_enable_sdio_irq,
2062 .execute_tuning = dw_mci_execute_tuning,
2063 .post_tmo = dw_mci_post_tmo,
2064 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2065 .start_signal_voltage_switch
2066 = dw_mci_start_signal_voltage_switch,
2067 .card_busy = dw_mci_card_busy,
2071 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2072 __releases(&host->lock)
2073 __acquires(&host->lock)
2075 if (DW_MCI_SEND_STATUS == host->dir_status){
2076 dw_mci_wait_unbusy(host);
2080 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2081 __releases(&host->lock)
2082 __acquires(&host->lock)
2084 struct dw_mci_slot *slot;
2085 struct mmc_host *prev_mmc = host->cur_slot->mmc;
2087 //WARN_ON(host->cmd || host->data);
2089 dw_mci_deal_data_end(host, mrq);
2092 MMC_DBG_CMD_FUNC(host->mmc,
2093 " reqeust end--reqeuest done, cmd=%d, "
2094 "cmderr=%d, host->state=%d [%s]",
2095 mrq->cmd->opcode, mrq->cmd->error,
2096 host->state,mmc_hostname(host->mmc));
2098 MMC_DBG_CMD_FUNC(host->mmc,
2099 " reqeust end--reqeuest done, cmd=%d, "
2100 "dataerr=%d, host->state=%d [%s]",
2101 mrq->cmd->opcode,mrq->data->error,
2102 host->state, mmc_hostname(host->mmc));
2104 host->cur_slot->mrq = NULL;
2106 if (!list_empty(&host->queue)) {
2107 slot = list_entry(host->queue.next,
2108 struct dw_mci_slot, queue_node);
2109 list_del(&slot->queue_node);
2110 dev_vdbg(host->dev, "list not empty: %s is next\n",
2111 mmc_hostname(slot->mmc));
2112 host->state = STATE_SENDING_CMD;
2113 MMC_DBG_CMD_FUNC(host->mmc,
2114 " list is not empty. run the request in list. [%s]",
2115 mmc_hostname(host->mmc));
2116 dw_mci_start_request(host, slot);
2118 dev_vdbg(host->dev, "list empty\n");
2119 host->state = STATE_IDLE;
2122 spin_unlock(&host->lock);
2123 mmc_request_done(prev_mmc, mrq);
2124 spin_lock(&host->lock);
2127 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2129 u32 status = host->cmd_status;
2131 host->cmd_status = 0;
2133 /* Read the response from the card (up to 16 bytes) */
2134 if (cmd->flags & MMC_RSP_PRESENT) {
2135 if (cmd->flags & MMC_RSP_136) {
2136 cmd->resp[3] = mci_readl(host, RESP0);
2137 cmd->resp[2] = mci_readl(host, RESP1);
2138 cmd->resp[1] = mci_readl(host, RESP2);
2139 cmd->resp[0] = mci_readl(host, RESP3);
2141 MMC_DBG_INFO_FUNC(host->mmc,
2142 "Command complete cmd=%d, "
2143 "resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]",
2144 cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0],
2145 mmc_hostname(host->mmc));
2147 cmd->resp[0] = mci_readl(host, RESP0);
2151 MMC_DBG_INFO_FUNC(host->mmc,
2152 "Command complete cmd=%d,resp[0]=0x%x. [%s]",
2153 cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2157 if (status & SDMMC_INT_RTO)
2159 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2162 cmd->error = -ETIMEDOUT;
2163 }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2164 cmd->error = -EILSEQ;
2165 }else if (status & SDMMC_INT_RESP_ERR){
2171 MMC_DBG_CMD_FUNC(host->mmc,
2172 "Command complete, cmd=%d,cmdError=%d [%s]",
2173 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2176 if(MMC_SEND_STATUS != cmd->opcode)
2177 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2178 MMC_DBG_CMD_FUNC(host->mmc,
2179 "Command complete, cmd=%d,cmdError=%d [%s]",
2180 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2184 /* newer ip versions need a delay between retries */
2185 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2190 static void dw_mci_tasklet_func(unsigned long priv)
2192 struct dw_mci *host = (struct dw_mci *)priv;
2193 struct dw_mci_slot *slot = mmc_priv(host->mmc);
2194 struct mmc_data *data;
2195 struct mmc_command *cmd;
2196 enum dw_mci_state state;
2197 enum dw_mci_state prev_state;
2198 u32 status, cmd_flags;
2199 unsigned long timeout = 0;
2202 spin_lock(&host->lock);
2204 state = host->state;
2214 case STATE_SENDING_CMD:
2215 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2216 &host->pending_events))
2221 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2222 dw_mci_command_complete(host, cmd);
2223 if (cmd == host->mrq->sbc && !cmd->error) {
2224 prev_state = state = STATE_SENDING_CMD;
2225 __dw_mci_start_request(host, host->cur_slot,
2230 if (cmd->data && cmd->error) {
2231 dw_mci_stop_dma(host);
2234 send_stop_cmd(host, data);
2235 state = STATE_SENDING_STOP;
2238 /* host->data = NULL; */
2241 send_stop_abort(host, data);
2242 state = STATE_SENDING_STOP;
2245 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2248 if (!host->mrq->data || cmd->error) {
2249 dw_mci_request_end(host, host->mrq);
2253 prev_state = state = STATE_SENDING_DATA;
2256 case STATE_SENDING_DATA:
2257 if (test_and_clear_bit(EVENT_DATA_ERROR,
2258 &host->pending_events)) {
2259 dw_mci_stop_dma(host);
2262 send_stop_cmd(host, data);
2264 /*single block read/write, send stop cmd
2265 manually to prevent host controller halt*/
2266 MMC_DBG_INFO_FUNC(host->mmc,
2267 "%s status 1 0x%08x [%s]\n",
2268 __func__, mci_readl(host, STATUS),
2269 mmc_hostname(host->mmc));
2271 mci_writel(host, CMDARG, 0);
2273 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2274 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2276 if(host->mmc->hold_reg_flag)
2277 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2279 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2281 timeout = jiffies + msecs_to_jiffies(500);
2284 ret = time_before(jiffies, timeout);
2285 if (!(mci_readl(host, CMD) & SDMMC_CMD_START))
2289 MMC_DBG_ERR_FUNC(host->mmc,
2290 "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2291 __func__, mmc_hostname(host->mmc));
2294 send_stop_abort(host, data);
2296 state = STATE_DATA_ERROR;
2300 MMC_DBG_CMD_FUNC(host->mmc,
2301 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2302 "wait for EVENT_XFER_COMPLETE.[%s]",
2303 prev_state, state, mmc_hostname(host->mmc));
2305 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2306 &host->pending_events))
2308 MMC_DBG_INFO_FUNC(host->mmc,
2309 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2310 "wait for EVENT_DATA_COMPLETE. [%s]",
2311 prev_state, state, mmc_hostname(host->mmc));
2313 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2314 prev_state = state = STATE_DATA_BUSY;
2317 case STATE_DATA_BUSY:
2318 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2319 &host->pending_events))
2322 dw_mci_deal_data_end(host, host->mrq);
2323 MMC_DBG_INFO_FUNC(host->mmc,
2324 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, "
2325 "after EVENT_DATA_COMPLETE. [%s]",
2326 prev_state, state, mmc_hostname(host->mmc));
2328 /* host->data = NULL; */
2329 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2330 status = host->data_status;
2332 if (status & DW_MCI_DATA_ERROR_FLAGS) {
2333 if((SDMMC_CTYPE_1BIT != slot->ctype) &&
2334 (MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2335 MMC_DBG_ERR_FUNC(host->mmc,
2336 "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,"
2337 "datastatus=0x%x [%s]",
2338 prev_state, state, status, mmc_hostname(host->mmc));
2340 if (status & SDMMC_INT_DRTO) {
2341 data->error = -ETIMEDOUT;
2342 } else if (status & SDMMC_INT_DCRC) {
2343 data->error = -EILSEQ;
2344 } else if (status & SDMMC_INT_EBE &&
2345 host->dir_status == DW_MCI_SEND_STATUS){
2347 * No data CRC status was returned.
2348 * The number of bytes transferred will
2349 * be exaggerated in PIO mode.
2351 data->bytes_xfered = 0;
2352 data->error = -ETIMEDOUT;
2361 * After an error, there may be data lingering
2362 * in the FIFO, so reset it - doing so
2363 * generates a block interrupt, hence setting
2364 * the scatter-gather pointer to NULL.
2366 dw_mci_fifo_reset(host);
2368 data->bytes_xfered = data->blocks * data->blksz;
2373 MMC_DBG_CMD_FUNC(host->mmc,
2374 "Pre-state[%d]-->NowState[%d]: "
2375 "no stop and no dataerr, exit [%s]",
2376 prev_state, state, mmc_hostname(host->mmc));
2377 dw_mci_request_end(host, host->mrq);
2380 MMC_DBG_CMD_FUNC(host->mmc,
2381 "Pre-state[%d]-->NowState[%d]: begin to stop [%s]",
2382 prev_state, state, mmc_hostname(host->mmc));
2384 if (host->mrq->sbc && !data->error) {
2385 data->stop->error = 0;
2387 MMC_DBG_CMD_FUNC(host->mmc,
2388 "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit [%s]",
2389 prev_state,state,mmc_hostname(host->mmc));
2391 dw_mci_request_end(host, host->mrq);
2395 prev_state = state = STATE_SENDING_STOP;
2397 send_stop_cmd(host, data);
2399 MMC_DBG_CMD_FUNC(host->mmc,
2400 "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP [%s]",
2401 prev_state, state, mmc_hostname(host->mmc));
2403 case STATE_SENDING_STOP:
2404 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2405 &host->pending_events))
2408 MMC_DBG_CMD_FUNC(host->mmc,
2409 "Pre-state[%d]-->NowState[%d]: begin to send cmd12 [%s]",
2410 prev_state, state, mmc_hostname(host->mmc));
2412 /* CMD error in data command */
2413 if (host->mrq->cmd->error && host->mrq->data) {
2414 dw_mci_fifo_reset(host);
2422 dw_mci_command_complete(host, host->mrq->stop);
2424 if (host->mrq->stop)
2425 dw_mci_command_complete(host, host->mrq->stop);
2427 host->cmd_status = 0;
2430 dw_mci_request_end(host, host->mrq);
2433 case STATE_DATA_ERROR:
2434 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2435 &host->pending_events))
2438 state = STATE_DATA_BUSY;
2441 } while (state != prev_state);
2443 host->state = state;
2445 spin_unlock(&host->lock);
2448 /* push final bytes to part_buf, only use during push */
2449 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2451 memcpy((void *)&host->part_buf, buf, cnt);
2452 host->part_buf_count = cnt;
2455 /* append bytes to part_buf, only use during push */
2456 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2458 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2459 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2460 host->part_buf_count += cnt;
2464 /* pull first bytes from part_buf, only use during pull */
2465 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2467 cnt = min(cnt, (int)host->part_buf_count);
2469 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2471 host->part_buf_count -= cnt;
2472 host->part_buf_start += cnt;
2477 /* pull final bytes from the part_buf, assuming it's just been filled */
2478 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2480 memcpy(buf, &host->part_buf, cnt);
2481 host->part_buf_start = cnt;
2482 host->part_buf_count = (1 << host->data_shift) - cnt;
2485 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2487 struct mmc_data *data = host->data;
2490 /* try and push anything in the part_buf */
2491 if (unlikely(host->part_buf_count)) {
2492 int len = dw_mci_push_part_bytes(host, buf, cnt);
2495 if (host->part_buf_count == 2) {
2496 mci_writew(host, DATA(host->data_offset),
2498 host->part_buf_count = 0;
2501 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2502 if (unlikely((unsigned long)buf & 0x1)) {
2504 u16 aligned_buf[64];
2505 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2506 int items = len >> 1;
2508 /* memcpy from input buffer into aligned buffer */
2509 memcpy(aligned_buf, buf, len);
2512 /* push data from aligned buffer into fifo */
2513 for (i = 0; i < items; ++i)
2514 mci_writew(host, DATA(host->data_offset),
2521 for (; cnt >= 2; cnt -= 2)
2522 mci_writew(host, DATA(host->data_offset), *pdata++);
2525 /* put anything remaining in the part_buf */
2527 dw_mci_set_part_bytes(host, buf, cnt);
2528 /* Push data if we have reached the expected data length */
2529 if ((data->bytes_xfered + init_cnt) ==
2530 (data->blksz * data->blocks))
2531 mci_writew(host, DATA(host->data_offset),
2536 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2538 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2539 if (unlikely((unsigned long)buf & 0x1)) {
2541 /* pull data from fifo into aligned buffer */
2542 u16 aligned_buf[64];
2543 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2544 int items = len >> 1;
2546 for (i = 0; i < items; ++i)
2547 aligned_buf[i] = mci_readw(host,
2548 DATA(host->data_offset));
2549 /* memcpy from aligned buffer into output buffer */
2550 memcpy(buf, aligned_buf, len);
2558 for (; cnt >= 2; cnt -= 2)
2559 *pdata++ = mci_readw(host, DATA(host->data_offset));
2563 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2564 dw_mci_pull_final_bytes(host, buf, cnt);
2568 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2570 struct mmc_data *data = host->data;
2573 /* try and push anything in the part_buf */
2574 if (unlikely(host->part_buf_count)) {
2575 int len = dw_mci_push_part_bytes(host, buf, cnt);
2578 if (host->part_buf_count == 4) {
2579 mci_writel(host, DATA(host->data_offset),
2581 host->part_buf_count = 0;
2584 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2585 if (unlikely((unsigned long)buf & 0x3)) {
2587 u32 aligned_buf[32];
2588 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2589 int items = len >> 2;
2591 /* memcpy from input buffer into aligned buffer */
2592 memcpy(aligned_buf, buf, len);
2595 /* push data from aligned buffer into fifo */
2596 for (i = 0; i < items; ++i)
2597 mci_writel(host, DATA(host->data_offset),
2604 for (; cnt >= 4; cnt -= 4)
2605 mci_writel(host, DATA(host->data_offset), *pdata++);
2608 /* put anything remaining in the part_buf */
2610 dw_mci_set_part_bytes(host, buf, cnt);
2611 /* Push data if we have reached the expected data length */
2612 if ((data->bytes_xfered + init_cnt) ==
2613 (data->blksz * data->blocks))
2614 mci_writel(host, DATA(host->data_offset),
2619 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2621 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2622 if (unlikely((unsigned long)buf & 0x3)) {
2624 /* pull data from fifo into aligned buffer */
2625 u32 aligned_buf[32];
2626 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2627 int items = len >> 2;
2629 for (i = 0; i < items; ++i)
2630 aligned_buf[i] = mci_readl(host,
2631 DATA(host->data_offset));
2632 /* memcpy from aligned buffer into output buffer */
2633 memcpy(buf, aligned_buf, len);
2641 for (; cnt >= 4; cnt -= 4)
2642 *pdata++ = mci_readl(host, DATA(host->data_offset));
2646 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2647 dw_mci_pull_final_bytes(host, buf, cnt);
2651 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2653 struct mmc_data *data = host->data;
2656 /* try and push anything in the part_buf */
2657 if (unlikely(host->part_buf_count)) {
2658 int len = dw_mci_push_part_bytes(host, buf, cnt);
2662 if (host->part_buf_count == 8) {
2663 mci_writeq(host, DATA(host->data_offset),
2665 host->part_buf_count = 0;
2668 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2669 if (unlikely((unsigned long)buf & 0x7)) {
2671 u64 aligned_buf[16];
2672 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2673 int items = len >> 3;
2675 /* memcpy from input buffer into aligned buffer */
2676 memcpy(aligned_buf, buf, len);
2679 /* push data from aligned buffer into fifo */
2680 for (i = 0; i < items; ++i)
2681 mci_writeq(host, DATA(host->data_offset),
2688 for (; cnt >= 8; cnt -= 8)
2689 mci_writeq(host, DATA(host->data_offset), *pdata++);
2692 /* put anything remaining in the part_buf */
2694 dw_mci_set_part_bytes(host, buf, cnt);
2695 /* Push data if we have reached the expected data length */
2696 if ((data->bytes_xfered + init_cnt) ==
2697 (data->blksz * data->blocks))
2698 mci_writeq(host, DATA(host->data_offset),
2703 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2705 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2706 if (unlikely((unsigned long)buf & 0x7)) {
2708 /* pull data from fifo into aligned buffer */
2709 u64 aligned_buf[16];
2710 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2711 int items = len >> 3;
2713 for (i = 0; i < items; ++i)
2714 aligned_buf[i] = mci_readq(host,
2715 DATA(host->data_offset));
2716 /* memcpy from aligned buffer into output buffer */
2717 memcpy(buf, aligned_buf, len);
2725 for (; cnt >= 8; cnt -= 8)
2726 *pdata++ = mci_readq(host, DATA(host->data_offset));
2730 host->part_buf = mci_readq(host, DATA(host->data_offset));
2731 dw_mci_pull_final_bytes(host, buf, cnt);
2735 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2739 /* get remaining partial bytes */
2740 len = dw_mci_pull_part_bytes(host, buf, cnt);
2741 if (unlikely(len == cnt))
2746 /* get the rest of the data */
2747 host->pull_data(host, buf, cnt);
2750 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2752 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2754 unsigned int offset;
2755 struct mmc_data *data = host->data;
2756 int shift = host->data_shift;
2759 unsigned int remain, fcnt;
2761 if(!host->mmc->bus_refs){
2762 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2766 if (!sg_miter_next(sg_miter))
2769 host->sg = sg_miter->piter.sg;
2770 buf = sg_miter->addr;
2771 remain = sg_miter->length;
2775 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2776 << shift) + host->part_buf_count;
2777 len = min(remain, fcnt);
2780 dw_mci_pull_data(host, (void *)(buf + offset), len);
2781 data->bytes_xfered += len;
2786 sg_miter->consumed = offset;
2787 status = mci_readl(host, MINTSTS);
2788 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2789 /* if the RXDR is ready read again */
2790 } while ((status & SDMMC_INT_RXDR) ||
2791 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2794 if (!sg_miter_next(sg_miter))
2796 sg_miter->consumed = 0;
2798 sg_miter_stop(sg_miter);
2802 sg_miter_stop(sg_miter);
2806 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2809 static void dw_mci_write_data_pio(struct dw_mci *host)
2811 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2813 unsigned int offset;
2814 struct mmc_data *data = host->data;
2815 int shift = host->data_shift;
2818 unsigned int fifo_depth = host->fifo_depth;
2819 unsigned int remain, fcnt;
2821 if (!host->mmc->bus_refs){
2822 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2827 if (!sg_miter_next(sg_miter))
2830 host->sg = sg_miter->piter.sg;
2831 buf = sg_miter->addr;
2832 remain = sg_miter->length;
2836 fcnt = ((fifo_depth -
2837 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2838 << shift) - host->part_buf_count;
2839 len = min(remain, fcnt);
2842 host->push_data(host, (void *)(buf + offset), len);
2843 data->bytes_xfered += len;
2848 sg_miter->consumed = offset;
2849 status = mci_readl(host, MINTSTS);
2850 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2851 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2854 if (!sg_miter_next(sg_miter))
2856 sg_miter->consumed = 0;
2858 sg_miter_stop(sg_miter);
2862 sg_miter_stop(sg_miter);
2866 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2869 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2871 if (!host->cmd_status)
2872 host->cmd_status = status;
2879 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2880 tasklet_schedule(&host->tasklet);
2883 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2885 struct dw_mci *host = dev_id;
2886 u32 pending, sdio_int;
2889 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2892 * DTO fix - version 2.10a and below, and only if internal DMA
2895 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2897 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2898 pending |= SDMMC_INT_DATA_OVER;
2902 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2903 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2904 host->cmd_status = pending;
2906 MMC_DBG_INFO_FUNC(host->mmc,
2907 "%s cmd_status INT=0x%x,[%s]",
2908 __FUNCTION__, host->cmd_status,
2909 mmc_hostname(host->mmc));
2911 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2914 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2915 /* if there is an error report DATA_ERROR */
2916 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2917 host->data_status = pending;
2919 printk(KERN_ERR "[%s] Data transmission error !!!! MINTSTS: [0x%08x]\n",
2920 mmc_hostname(host->mmc), pending);
2921 mmc_retune_needed(host->mmc);
2922 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2924 MMC_DBG_INFO_FUNC(host->mmc,
2925 "%s data_status INT=0x%x,[%s]",
2926 __FUNCTION__, host->data_status,
2927 mmc_hostname(host->mmc));
2928 tasklet_schedule(&host->tasklet);
2931 if (pending & SDMMC_INT_DATA_OVER) {
2932 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2933 MMC_DBG_CMD_FUNC(host->mmc,
2934 "SDMMC_INT_DATA_OVER, INT-pending=0x%x [%s]",
2935 pending, mmc_hostname(host->mmc));
2936 if (!host->data_status)
2937 host->data_status = pending;
2939 if (host->dir_status == DW_MCI_RECV_STATUS) {
2940 if (host->sg != NULL)
2941 dw_mci_read_data_pio(host, true);
2943 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2944 tasklet_schedule(&host->tasklet);
2947 if (pending & SDMMC_INT_RXDR) {
2948 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2949 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2950 dw_mci_read_data_pio(host, false);
2953 if (pending & SDMMC_INT_TXDR) {
2954 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2955 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2956 dw_mci_write_data_pio(host);
2959 if (pending & SDMMC_INT_VSI) {
2960 MMC_DBG_SW_VOL_FUNC(host->mmc,
2961 "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",
2962 pending, mmc_hostname(host->mmc));
2963 mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2964 dw_mci_cmd_interrupt(host, pending);
2967 if (pending & SDMMC_INT_CMD_DONE) {
2968 MMC_DBG_CMD_FUNC(host->mmc,
2969 "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",
2970 mci_readl(host, CMD), pending, mmc_hostname(host->mmc));
2971 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2972 dw_mci_cmd_interrupt(host, pending);
2975 if (pending & SDMMC_INT_CD) {
2976 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2977 MMC_DBG_INFO_FUNC(host->mmc,
2978 "SDMMC_INT_CD, INT-pending=0x%x. [%s]",
2979 pending, mmc_hostname(host->mmc));
2980 wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2981 queue_work(host->card_workqueue, &host->card_work);
2984 if (pending & SDMMC_INT_HLE) {
2985 mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2986 MMC_DBG_CMD_FUNC(host->mmc,
2987 "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",
2988 pending, mmc_hostname(host->mmc));
2992 /* Handle SDIO Interrupts */
2993 for (i = 0; i < host->num_slots; i++) {
2994 struct dw_mci_slot *slot = host->slot[i];
2996 if (host->verid < DW_MMC_240A)
2997 sdio_int = SDMMC_INT_SDIO(i);
2999 sdio_int = SDMMC_INT_SDIO(i + 8);
3001 if (pending & sdio_int) {
3002 mci_writel(host, RINTSTS, sdio_int);
3003 mmc_signal_sdio_irq(slot->mmc);
3009 #ifdef CONFIG_MMC_DW_IDMAC
3010 /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3011 if (!(cpu_is_rk3036() || cpu_is_rk312x())){
3012 /* Handle DMA interrupts */
3013 pending = mci_readl(host, IDSTS);
3014 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3015 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3016 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3017 host->dma_ops->complete((void *)host);
3025 static void dw_mci_work_routine_card(struct work_struct *work)
3027 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3030 for (i = 0; i < host->num_slots; i++) {
3031 struct dw_mci_slot *slot = host->slot[i];
3032 struct mmc_host *mmc = slot->mmc;
3033 struct mmc_request *mrq;
3036 present = dw_mci_get_cd(mmc);
3038 /* Card insert, switch data line to uart function, and vice verse.
3039 ONLY audi chip need switched by software, using udbg tag in dts!
3041 if (!(IS_ERR(host->pins_udbg)) &&
3042 !(IS_ERR(host->pins_default))) {
3044 if (pinctrl_select_state(host->pinctrl,
3045 host->pins_default) < 0)
3047 "%s: Default pinctrl setting failed!\n",
3048 mmc_hostname(host->mmc));
3050 if (pinctrl_select_state(host->pinctrl,
3051 host->pins_udbg) < 0)
3053 "%s: Udbg pinctrl setting failed!\n",
3054 mmc_hostname(host->mmc));
3058 while (present != slot->last_detect_state) {
3059 dev_dbg(&slot->mmc->class_dev, "card %s\n",
3060 present ? "inserted" : "removed");
3061 MMC_DBG_BOOT_FUNC(mmc, " The card is %s. ===!!!!!!==[%s]\n",
3062 present ? "inserted" : "removed.", mmc_hostname(mmc));
3064 dw_mci_ctrl_all_reset(host);
3065 /* Stop edma when rountine card triggered */
3066 if(cpu_is_rk3036() || cpu_is_rk312x())
3067 if(host->dma_ops && host->dma_ops->stop)
3068 host->dma_ops->stop(host);
3069 rk_send_wakeup_key();//wake up system
3070 spin_lock_bh(&host->lock);
3072 /* Card change detected */
3073 slot->last_detect_state = present;
3075 /* Clean up queue if present */
3078 if (mrq == host->mrq) {
3082 switch (host->state) {
3085 case STATE_SENDING_CMD:
3086 mrq->cmd->error = -ENOMEDIUM;
3090 case STATE_SENDING_DATA:
3091 mrq->data->error = -ENOMEDIUM;
3092 dw_mci_stop_dma(host);
3094 case STATE_DATA_BUSY:
3095 case STATE_DATA_ERROR:
3096 if (mrq->data->error == -EINPROGRESS)
3097 mrq->data->error = -ENOMEDIUM;
3101 case STATE_SENDING_STOP:
3102 mrq->stop->error = -ENOMEDIUM;
3106 dw_mci_request_end(host, mrq);
3108 list_del(&slot->queue_node);
3109 mrq->cmd->error = -ENOMEDIUM;
3111 mrq->data->error = -ENOMEDIUM;
3113 mrq->stop->error = -ENOMEDIUM;
3115 MMC_DBG_CMD_FUNC(host->mmc,
3116 "dw_mci_work--reqeuest done, cmd=%d [%s]",
3117 mrq->cmd->opcode, mmc_hostname(mmc));
3119 spin_unlock(&host->lock);
3120 mmc_request_done(slot->mmc, mrq);
3121 spin_lock(&host->lock);
3125 /* Power down slot */
3127 /* Clear down the FIFO */
3128 dw_mci_fifo_reset(host);
3129 #ifdef CONFIG_MMC_DW_IDMAC
3130 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
3131 dw_mci_idmac_reset(host);
3135 spin_unlock_bh(&host->lock);
3137 present = dw_mci_get_cd(mmc);
3140 mmc_detect_change(slot->mmc,
3141 msecs_to_jiffies(host->pdata->detect_delay_ms));
3146 /* given a slot id, find out the device node representing that slot */
3147 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3149 struct device_node *np;
3153 if (!dev || !dev->of_node)
3156 for_each_child_of_node(dev->of_node, np) {
3157 addr = of_get_property(np, "reg", &len);
3158 if (!addr || (len < sizeof(int)))
3160 if (be32_to_cpup(addr) == slot)
3166 static struct dw_mci_of_slot_quirks {
3169 } of_slot_quirks[] = {
3171 .quirk = "disable-wp",
3172 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3176 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3178 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3183 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3184 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3185 quirks |= of_slot_quirks[idx].id;
3190 /* find out bus-width for a given slot */
3191 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3193 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3199 if (of_property_read_u32(np, "bus-width", &bus_wd))
3200 dev_err(dev, "bus-width property not found, assuming width"
3206 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3207 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3209 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3215 gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3217 /* Having a missing entry is valid; return silently */
3218 if (!gpio_is_valid(gpio))
3221 if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3222 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3226 gpio_direction_output(gpio, 0);//set 0 to pwr-en
3232 /* find the write protect gpio for a given slot; or -1 if none specified */
3233 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3235 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3241 gpio = of_get_named_gpio(np, "wp-gpios", 0);
3243 /* Having a missing entry is valid; return silently */
3244 if (!gpio_is_valid(gpio))
3247 if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3248 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3255 /* find the cd gpio for a given slot */
3256 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3257 struct mmc_host *mmc)
3259 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3265 gpio = of_get_named_gpio(np, "cd-gpios", 0);
3267 /* Having a missing entry is valid; return silently */
3268 if (!gpio_is_valid(gpio))
3271 if (mmc_gpio_request_cd(mmc, gpio, 0))
3272 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3275 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3277 struct mmc_host *mmc = dev_id;
3278 struct dw_mci_slot *slot = mmc_priv(mmc);
3279 struct dw_mci *host = slot->host;
3280 int gpio_cd = slot->cd_gpio;
3282 (gpio_get_value(gpio_cd) == 0) ?
3283 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
3284 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3286 /* wakeup system whether gpio debounce or not */
3287 rk_send_wakeup_key();
3289 /* no need to trigger detect flow when rescan is disabled.
3290 This case happended in dpm, that we just wakeup system and
3291 let suspend_post notify callback handle it.
3293 if(mmc->rescan_disable == 0)
3294 queue_work(host->card_workqueue, &host->card_work);
3296 printk("%s: rescan been disabled!\n", __FUNCTION__);
3301 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3302 struct mmc_host *mmc)
3304 struct dw_mci_slot *slot = mmc_priv(mmc);
3305 struct dw_mci *host = slot->host;
3309 /* Having a missing entry is valid; return silently */
3310 if (!gpio_is_valid(gpio))
3313 irq = gpio_to_irq(gpio);
3315 ret = devm_request_threaded_irq(
3316 &mmc->class_dev, irq,
3317 NULL, dw_mci_gpio_cd_irqt,
3318 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3323 "Request cd-gpio %d interrupt error!\n", gpio);
3325 /* enable wakeup event for gpio-cd in idle or deep suspend*/
3326 enable_irq_wake(irq);
3329 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3333 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3334 struct mmc_host *mmc)
3336 if (!gpio_is_valid(gpio))
3339 if (gpio_to_irq(gpio) >= 0) {
3340 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3341 devm_gpio_free(&mmc->class_dev, gpio);
3344 #else /* CONFIG_OF */
3345 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3349 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3353 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3357 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3361 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3362 struct mmc_host *mmc)
3366 #endif /* CONFIG_OF */
3368 /* @host: dw_mci host prvdata
3369 * Init pinctrl for each platform. Usually we assign
3370 * "defalut" tag for functional usage, "idle" tag for gpio
3371 * state and "udbg" tag for uart_dbg if any.
3373 static void dw_mci_init_pinctrl(struct dw_mci *host)
3375 /* Fixme: DON'T TOUCH EMMC SETTING! */
3376 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3379 /* Get pinctrl for DTS */
3380 host->pinctrl = devm_pinctrl_get(host->dev);
3381 if (IS_ERR(host->pinctrl)) {
3382 dev_err(host->dev, "%s: No pinctrl used!\n",
3383 mmc_hostname(host->mmc));
3387 /* Lookup idle state */
3389 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_IDLE);
3390 if (IS_ERR(host->pins_idle)) {
3391 dev_err(host->dev, "%s: No idle tag found!\n",
3392 mmc_hostname(host->mmc));
3394 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3396 "%s: Idle pinctrl setting failed!\n",
3397 mmc_hostname(host->mmc));
3400 /* Lookup default state */
3401 host->pins_default =
3402 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_DEFAULT);
3403 if (IS_ERR(host->pins_default)) {
3404 dev_err(host->dev, "%s: No default pinctrl found!\n",
3405 mmc_hostname(host->mmc));
3407 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3409 "%s: Default pinctrl setting failed!\n",
3410 mmc_hostname(host->mmc));
3413 /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3414 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3415 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3416 if (IS_ERR(host->pins_udbg)) {
3417 dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3418 mmc_hostname(host->mmc));
3420 if (!dw_mci_get_cd(host->mmc))
3421 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3422 dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3423 mmc_hostname(host->mmc));
3428 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3429 unsigned long mode, void *unused)
3431 struct mmc_host *host = container_of(
3432 notify_block, struct mmc_host, pm_notify);
3433 unsigned long flags;
3436 case PM_HIBERNATION_PREPARE:
3437 case PM_SUSPEND_PREPARE:
3438 dev_err(host->parent,
3439 "dw_mci_pm_notify: suspend prepare\n");
3440 spin_lock_irqsave(&host->lock, flags);
3441 host->rescan_disable = 1;
3442 spin_unlock_irqrestore(&host->lock, flags);
3443 if (cancel_delayed_work(&host->detect))
3444 wake_unlock(&host->detect_wake_lock);
3447 case PM_POST_SUSPEND:
3448 case PM_POST_HIBERNATION:
3449 case PM_POST_RESTORE:
3450 dev_err(host->parent,
3451 "dw_mci_pm_notify: post suspend\n");
3452 spin_lock_irqsave(&host->lock, flags);
3453 host->rescan_disable = 0;
3454 spin_unlock_irqrestore(&host->lock, flags);
3455 mmc_detect_change(host, 10);
3461 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3463 struct mmc_host *mmc;
3464 struct dw_mci_slot *slot;
3465 const struct dw_mci_drv_data *drv_data = host->drv_data;
3470 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3474 slot = mmc_priv(mmc);
3478 host->slot[id] = slot;
3481 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3483 mmc->ops = &dw_mci_ops;
3485 if (of_property_read_u32_array(host->dev->of_node,
3486 "clock-freq-min-max", freq, 2)) {
3487 mmc->f_min = DW_MCI_FREQ_MIN;
3488 mmc->f_max = DW_MCI_FREQ_MAX;
3490 printk("%s: fmin=%d, fmax=%d [%s]\n",
3491 __FUNCTION__, mmc->f_min,
3492 mmc->f_max, mmc_hostname(mmc));
3494 mmc->f_min = freq[0];
3495 mmc->f_max = freq[1];
3497 printk("%s: fmin=%d, fmax=%d [%s]\n",
3498 __FUNCTION__, mmc->f_min,
3499 mmc->f_max, mmc_hostname(mmc));
3502 if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3503 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3504 if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3505 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3506 if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3507 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3509 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3510 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3511 if (register_pm_notifier(&mmc->pm_notify)) {
3512 pr_err("dw_mci: register_pm_notifier failed\n");
3513 goto err_pm_notifier;
3517 if (host->cid == DW_MCI_TYPE_RK3368) {
3518 if (IS_ERR(host->grf))
3519 pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3521 /* Disable force_jtag */
3522 regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3523 } else if (cpu_is_rk3288()) {
3524 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3527 /* We assume only low-level chip use gpio_cd */
3528 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3529 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3530 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3531 if (gpio_is_valid(slot->cd_gpio)) {
3532 /* Request gpio int for card detection */
3533 dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3535 slot->cd_gpio = -ENODEV;
3536 dev_err(host->dev, "failed to get your cd-gpios!\n");
3540 if (host->pdata->get_ocr)
3541 mmc->ocr_avail = host->pdata->get_ocr(id);
3544 mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
3545 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33|
3546 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36 |
3547 MMC_VDD_26_27 | MMC_VDD_25_26 | MMC_VDD_24_25 |
3548 MMC_VDD_23_24 | MMC_VDD_22_23 | MMC_VDD_21_22 |
3549 MMC_VDD_20_21 | MMC_VDD_165_195;
3553 * Start with slot power disabled, it will be enabled when a card
3556 if (host->pdata->setpower)
3557 host->pdata->setpower(id, 0);
3559 if (host->pdata->caps)
3560 mmc->caps = host->pdata->caps;
3562 if (host->pdata->pm_caps)
3563 mmc->pm_caps = host->pdata->pm_caps;
3565 if (host->dev->of_node) {
3566 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3570 ctrl_id = to_platform_device(host->dev)->id;
3572 if (drv_data && drv_data->caps)
3573 mmc->caps |= drv_data->caps[ctrl_id];
3574 if (drv_data && drv_data->hold_reg_flag)
3575 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3577 /* set the compatibility of driver. */
3578 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3579 | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3581 if (host->pdata->caps2)
3582 mmc->caps2 = host->pdata->caps2;
3584 if (host->pdata->get_bus_wd)
3585 bus_width = host->pdata->get_bus_wd(slot->id);
3586 else if (host->dev->of_node)
3587 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3591 switch (bus_width) {
3593 mmc->caps |= MMC_CAP_8_BIT_DATA;
3595 mmc->caps |= MMC_CAP_4_BIT_DATA;
3598 if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3599 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3600 if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3601 mmc->caps |= MMC_CAP_SDIO_IRQ;
3602 if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3603 mmc->caps |= MMC_CAP_HW_RESET;
3604 if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3605 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3606 if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3607 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3608 if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3609 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3610 if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3611 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3613 /*Assign pm_caps pass to pm_flags*/
3614 mmc->pm_flags = mmc->pm_caps;
3616 if (host->pdata->blk_settings) {
3617 mmc->max_segs = host->pdata->blk_settings->max_segs;
3618 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3619 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3620 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3621 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3623 /* Useful defaults if platform data is unset. */
3624 #ifdef CONFIG_MMC_DW_IDMAC
3625 mmc->max_segs = host->ring_size;
3626 mmc->max_blk_size = 65536;
3627 mmc->max_blk_count = host->ring_size;
3628 mmc->max_seg_size = 0x1000;
3629 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3630 if(cpu_is_rk3036() || cpu_is_rk312x()){
3631 /* fixup for external dmac setting */
3633 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3634 mmc->max_blk_count = 65535;
3635 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3636 mmc->max_seg_size = mmc->max_req_size;
3640 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3641 mmc->max_blk_count = 512;
3642 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3643 mmc->max_seg_size = mmc->max_req_size;
3644 #endif /* CONFIG_MMC_DW_IDMAC */
3648 slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3650 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3655 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3656 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3660 if (IS_ERR(host->vmmc)) {
3661 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3664 ret = regulator_enable(host->vmmc);
3667 "failed to enable regulator: %d\n", ret);
3674 slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3676 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3677 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3679 dw_mci_init_pinctrl(host);
3680 ret = mmc_add_host(mmc);
3684 #if defined(CONFIG_DEBUG_FS)
3685 dw_mci_init_debugfs(slot);
3688 /* Card initially undetected */
3689 slot->last_detect_state = 1;
3693 unregister_pm_notifier(&mmc->pm_notify);
3696 if (gpio_is_valid(slot->cd_gpio))
3697 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3702 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3704 /* Shutdown detect IRQ */
3705 if (slot->host->pdata->exit)
3706 slot->host->pdata->exit(id);
3708 /* Debugfs stuff is cleaned up by mmc core */
3709 mmc_remove_host(slot->mmc);
3710 slot->host->slot[id] = NULL;
3711 mmc_free_host(slot->mmc);
3714 static void dw_mci_init_dma(struct dw_mci *host)
3716 /* Alloc memory for sg translation */
3717 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3718 &host->sg_dma, GFP_KERNEL);
3719 if (!host->sg_cpu) {
3720 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3725 /* Determine which DMA interface to use */
3726 #if defined(CONFIG_MMC_DW_IDMAC)
3727 if(cpu_is_rk3036() || cpu_is_rk312x()){
3728 host->dma_ops = &dw_mci_edmac_ops;
3729 dev_info(host->dev, "Using external DMA controller.\n");
3731 host->dma_ops = &dw_mci_idmac_ops;
3732 dev_info(host->dev, "Using internal DMA controller.\n");
3739 if (host->dma_ops->init && host->dma_ops->start &&
3740 host->dma_ops->stop && host->dma_ops->cleanup) {
3741 if (host->dma_ops->init(host)) {
3742 dev_err(host->dev, "%s: Unable to initialize "
3743 "DMA Controller.\n", __func__);
3747 dev_err(host->dev, "DMA initialization not found.\n");
3755 dev_info(host->dev, "Using PIO mode.\n");
3760 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3762 unsigned long timeout = jiffies + msecs_to_jiffies(500);
3765 ctrl = mci_readl(host, CTRL);
3767 mci_writel(host, CTRL, ctrl);
3769 /* wait till resets clear */
3771 ctrl = mci_readl(host, CTRL);
3772 if (!(ctrl & reset))
3774 } while (time_before(jiffies, timeout));
3777 "Timeout resetting block (ctrl reset %#x)\n",
3783 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3786 * Reseting generates a block interrupt, hence setting
3787 * the scatter-gather pointer to NULL.
3790 sg_miter_stop(&host->sg_miter);
3794 return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3797 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3799 return dw_mci_ctrl_reset(host,
3800 SDMMC_CTRL_FIFO_RESET |
3802 SDMMC_CTRL_DMA_RESET);
3805 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3810 buffer = host->regs_buffer;
3812 for (index = 0; index < DW_REGS_NUM ; index++){
3813 *buffer = mci_readreg(host, index*4);
3814 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3815 dw_mci_regs[index].name, *buffer);
3819 *buffer = mci_readl(host,CDTHRCTL);
3820 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3823 static void dw_mci_rst_post_resume(struct dw_mci *host)
3828 buffer = host->regs_buffer;
3830 for (index = 0; index < DW_REGS_NUM; index++){
3831 mci_writereg(host, index*4, *buffer);
3834 mci_writel(host, CDTHRCTL, *buffer);
3837 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3838 .pre_suspend = dw_mci_rst_pre_suspend,
3839 .post_resume = dw_mci_rst_post_resume,
3844 static struct dw_mci_of_quirks {
3849 .quirk = "broken-cd",
3850 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3854 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3856 struct dw_mci_board *pdata;
3857 struct device *dev = host->dev;
3858 struct device_node *np = dev->of_node;
3859 const struct dw_mci_drv_data *drv_data = host->drv_data;
3861 u32 clock_frequency;
3863 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3865 dev_err(dev, "could not allocate memory for pdata\n");
3866 return ERR_PTR(-ENOMEM);
3869 /* find out number of slots supported */
3870 if (of_property_read_u32(dev->of_node, "num-slots",
3871 &pdata->num_slots)) {
3872 dev_info(dev, "num-slots property not found, "
3873 "assuming 1 slot is available\n");
3874 pdata->num_slots = 1;
3877 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3878 dev_info(dev, "fifo-depth property not found, using "
3879 "value of FIFOTH register as default\n");
3881 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3883 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3884 pdata->bus_hz = clock_frequency;
3886 if (drv_data && drv_data->parse_dt) {
3887 ret = drv_data->parse_dt(host);
3889 return ERR_PTR(ret);
3892 if (of_find_property(np, "keep-power-in-suspend", NULL))
3893 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3895 if (of_find_property(np, "enable-sdio-wakeup", NULL))
3896 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3898 if (of_find_property(np, "supports-highspeed", NULL))
3899 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3901 if (of_find_property(np, "supports-UHS_SDR104", NULL))
3902 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3904 if (of_find_property(np, "supports-DDR_MODE", NULL))
3905 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3907 if (of_find_property(np, "caps2-mmc-hs200", NULL))
3908 pdata->caps2 |= MMC_CAP2_HS200;
3910 if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3911 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3913 if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3914 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3916 if (of_get_property(np, "cd-inverted", NULL))
3917 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3919 if (of_get_property(np, "bootpart-no-access", NULL))
3920 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3922 if (of_get_property(np, "controller-power-down", NULL)) {
3924 (u32 *)devm_kzalloc(host->dev,
3925 DW_REGS_SIZE, GFP_KERNEL);
3926 if (!host->regs_buffer) {
3928 "could not allocate memory for regs_buffer\n");
3929 return ERR_PTR(-ENOMEM);
3932 host->rst_ops = &dw_mci_pdrst_ops;
3935 if (of_get_property(np, "assume_removable", NULL))
3936 mmc_assume_removable = 0;
3941 #else /* CONFIG_OF */
3942 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3944 return ERR_PTR(-EINVAL);
3946 #endif /* CONFIG_OF */
3948 int dw_mci_probe(struct dw_mci *host)
3950 const struct dw_mci_drv_data *drv_data = host->drv_data;
3951 int width, i, ret = 0;
3957 host->pdata = dw_mci_parse_dt(host);
3958 if (IS_ERR(host->pdata)) {
3959 dev_err(host->dev, "platform data not available\n");
3964 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3966 "Platform data must supply select_slot function\n");
3971 * In 2.40a spec, Data offset is changed.
3972 * Need to check the version-id and set data-offset for DATA register.
3974 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3975 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3977 if (host->verid < DW_MMC_240A)
3978 host->data_offset = DATA_OFFSET;
3980 host->data_offset = DATA_240A_OFFSET;
3983 host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
3984 if (IS_ERR(host->hpclk_mmc)) {
3985 dev_err(host->dev, "failed to get hpclk_mmc\n");
3987 clk_prepare_enable(host->hpclk_mmc);
3991 host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3992 if (IS_ERR(host->hclk_mmc)) {
3993 dev_err(host->dev, "failed to get hclk_mmc\n");
3994 ret = PTR_ERR(host->hclk_mmc);
3998 clk_prepare_enable(host->hclk_mmc);
4001 host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
4002 if (IS_ERR(host->clk_mmc)) {
4003 dev_err(host->dev, "failed to get clk mmc_per\n");
4004 ret = PTR_ERR(host->clk_mmc);
4008 host->bus_hz = host->pdata->bus_hz;
4009 if (!host->bus_hz) {
4010 dev_err(host->dev, "Platform data must supply bus speed\n");
4015 if (host->verid < DW_MMC_240A)
4016 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4018 //rockchip: fix divider 2 in clksum before controlller
4019 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4022 dev_err(host->dev, "failed to set clk mmc\n");
4025 clk_prepare_enable(host->clk_mmc);
4027 if (drv_data && drv_data->setup_clock) {
4028 ret = drv_data->setup_clock(host);
4031 "implementation specific clock setup failed\n");
4036 host->quirks = host->pdata->quirks;
4037 host->irq_state = true;
4038 host->set_speed = 0;
4040 host->svi_flags = 0;
4042 spin_lock_init(&host->lock);
4043 spin_lock_init(&host->slock);
4045 INIT_LIST_HEAD(&host->queue);
4047 * Get the host data width - this assumes that HCON has been set with
4048 * the correct values.
4050 i = (mci_readl(host, HCON) >> 7) & 0x7;
4052 host->push_data = dw_mci_push_data16;
4053 host->pull_data = dw_mci_pull_data16;
4055 host->data_shift = 1;
4056 } else if (i == 2) {
4057 host->push_data = dw_mci_push_data64;
4058 host->pull_data = dw_mci_pull_data64;
4060 host->data_shift = 3;
4062 /* Check for a reserved value, and warn if it is */
4064 "HCON reports a reserved host data width!\n"
4065 "Defaulting to 32-bit access.\n");
4066 host->push_data = dw_mci_push_data32;
4067 host->pull_data = dw_mci_pull_data32;
4069 host->data_shift = 2;
4072 /* Reset all blocks */
4073 if (!dw_mci_ctrl_all_reset(host))
4076 host->dma_ops = host->pdata->dma_ops;
4077 dw_mci_init_dma(host);
4079 /* Clear the interrupts for the host controller */
4080 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4081 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4083 /* Put in max timeout */
4084 mci_writel(host, TMOUT, 0xFFFFFFFF);
4087 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
4088 * Tx Mark = fifo_size / 2 DMA Size = 8
4090 if (!host->pdata->fifo_depth) {
4092 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4093 * have been overwritten by the bootloader, just like we're
4094 * about to do, so if you know the value for your hardware, you
4095 * should put it in the platform data.
4097 fifo_size = mci_readl(host, FIFOTH);
4098 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4100 fifo_size = host->pdata->fifo_depth;
4102 host->fifo_depth = fifo_size;
4104 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4105 mci_writel(host, FIFOTH, host->fifoth_val);
4107 /* disable clock to CIU */
4108 mci_writel(host, CLKENA, 0);
4109 mci_writel(host, CLKSRC, 0);
4111 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4112 host->card_workqueue = alloc_workqueue("dw-mci-card",
4113 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4114 if (!host->card_workqueue) {
4118 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4119 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4120 host->irq_flags, "dw-mci", host);
4124 if (host->pdata->num_slots)
4125 host->num_slots = host->pdata->num_slots;
4127 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4129 /* We need at least one slot to succeed */
4130 for (i = 0; i < host->num_slots; i++) {
4131 ret = dw_mci_init_slot(host, i);
4133 dev_dbg(host->dev, "slot %d init failed\n", i);
4139 * Enable interrupts for command done, data over, data empty, card det,
4140 * receive ready and error such as transmit, receive timeout, crc error
4142 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4143 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4144 SDMMC_INT_VSI | SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4145 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4146 !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4147 regs |= SDMMC_INT_CD;
4149 mci_writel(host, INTMASK, regs);
4151 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4153 dev_info(host->dev, "DW MMC controller at irq %d, "
4154 "%d bit host data width, "
4156 host->irq, width, fifo_size);
4159 dev_info(host->dev, "%d slots initialized\n", init_slots);
4161 dev_dbg(host->dev, "attempted to initialize %d slots, "
4162 "but failed on all\n", host->num_slots);
4167 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4168 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4173 destroy_workqueue(host->card_workqueue);
4176 if (host->use_dma && host->dma_ops->exit)
4177 host->dma_ops->exit(host);
4180 regulator_disable(host->vmmc);
4181 regulator_put(host->vmmc);
4185 if (!IS_ERR(host->clk_mmc))
4186 clk_disable_unprepare(host->clk_mmc);
4188 if (!IS_ERR(host->hclk_mmc))
4189 clk_disable_unprepare(host->hclk_mmc);
4192 EXPORT_SYMBOL(dw_mci_probe);
4194 void dw_mci_remove(struct dw_mci *host)
4196 struct mmc_host *mmc = host->mmc;
4197 struct dw_mci_slot *slot = mmc_priv(mmc);
4200 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4201 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4203 for(i = 0; i < host->num_slots; i++){
4204 dev_dbg(host->dev, "remove slot %d\n", i);
4206 dw_mci_cleanup_slot(host->slot[i], i);
4209 /* disable clock to CIU */
4210 mci_writel(host, CLKENA, 0);
4211 mci_writel(host, CLKSRC, 0);
4213 destroy_workqueue(host->card_workqueue);
4214 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4215 unregister_pm_notifier(&host->mmc->pm_notify);
4217 if (host->use_dma && host->dma_ops->exit)
4218 host->dma_ops->exit(host);
4220 if (gpio_is_valid(slot->cd_gpio))
4221 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4224 regulator_disable(host->vmmc);
4225 regulator_put(host->vmmc);
4227 if (!IS_ERR(host->clk_mmc))
4228 clk_disable_unprepare(host->clk_mmc);
4230 if (!IS_ERR(host->hclk_mmc))
4231 clk_disable_unprepare(host->hclk_mmc);
4232 if (!IS_ERR(host->hpclk_mmc))
4233 clk_disable_unprepare(host->hpclk_mmc);
4235 EXPORT_SYMBOL(dw_mci_remove);
4239 #ifdef CONFIG_PM_SLEEP
4241 * TODO: we should probably disable the clock to the card in the suspend path.
4243 extern int get_wifi_chip_type(void);
4244 int dw_mci_suspend(struct dw_mci *host)
4246 int present = dw_mci_get_cd(host->mmc);
4248 if((host->mmc->restrict_caps &
4249 RESTRICT_CARD_TYPE_SDIO) &&
4250 (get_wifi_chip_type() == WIFI_ESP8089 ||
4251 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4255 regulator_disable(host->vmmc);
4257 /* Only for sdmmc controller */
4258 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4259 disable_irq(host->irq);
4261 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4262 MMC_DBG_ERR_FUNC(host->mmc,
4263 "Idle pinctrl setting failed! [%s]",
4264 mmc_hostname(host->mmc));
4267 /* Soc rk3126/3036 already in gpio_cd mode */
4268 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4269 dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4270 enable_irq_wake(host->mmc->slot.cd_irq);
4274 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4275 mci_writel(host, INTMASK, 0x00);
4276 mci_writel(host, CTRL, 0x00);
4278 if (host->rst_ops &&
4279 host->rst_ops->pre_suspend)
4280 host->rst_ops->pre_suspend(host);
4284 EXPORT_SYMBOL(dw_mci_suspend);
4286 int dw_mci_resume(struct dw_mci *host)
4290 struct dw_mci_slot *slot;
4291 int present = dw_mci_get_cd(host->mmc);
4293 if (host->rst_ops &&
4294 host->rst_ops->post_resume)
4295 host->rst_ops->post_resume(host);
4298 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4299 (get_wifi_chip_type() == WIFI_ESP8089 ||
4300 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4303 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4304 slot = mmc_priv(host->mmc);
4305 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4309 /*only for sdmmc controller*/
4310 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4311 /* Soc rk3126/3036 already in gpio_cd mode */
4312 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4313 disable_irq_wake(host->mmc->slot.cd_irq);
4314 mmc_gpio_free_cd(host->mmc);
4318 if (!IS_ERR(host->pins_udbg)) {
4319 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4320 MMC_DBG_ERR_FUNC(host->mmc,
4321 "Idle pinctrl setting failed! [%s]",
4322 mmc_hostname(host->mmc));
4323 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4324 MMC_DBG_ERR_FUNC(host->mmc,
4325 "Udbg pinctrl setting failed! [%s]",
4326 mmc_hostname(host->mmc));
4328 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4329 MMC_DBG_ERR_FUNC(host->mmc,
4330 "Default pinctrl setting failed! [%s]",
4331 mmc_hostname(host->mmc));
4334 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4335 MMC_DBG_ERR_FUNC(host->mmc,
4336 "Default pinctrl setting failed! [%s]",
4337 mmc_hostname(host->mmc));
4341 if (cpu_is_rk3288())
4342 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4343 else if (cpu_is_rk3036())
4344 grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4345 else if (cpu_is_rk312x())
4346 /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4347 grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4350 ret = regulator_enable(host->vmmc);
4353 "failed to enable regulator: %d\n", ret);
4358 if (!dw_mci_ctrl_all_reset(host)){
4363 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
4364 if(host->use_dma && host->dma_ops->init)
4365 host->dma_ops->init(host);
4368 * Restore the initial value at FIFOTH register
4369 * And Invalidate the prev_blksz with zero
4371 mci_writel(host, FIFOTH, host->fifoth_val);
4372 host->prev_blksz = 0;
4373 /* Put in max timeout */
4374 mci_writel(host, TMOUT, 0xFFFFFFFF);
4376 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4377 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4378 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4380 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4381 regs |= SDMMC_INT_CD;
4383 mci_writel(host, INTMASK, regs);
4384 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4386 /* Only for sdmmc controller */
4387 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
4388 enable_irq(host->irq);
4390 for (i = 0; i < host->num_slots; i++){
4391 struct dw_mci_slot *slot = host->slot[i];
4394 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4395 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4396 dw_mci_setup_bus(slot, true);
4402 EXPORT_SYMBOL(dw_mci_resume);
4403 #endif /* CONFIG_PM_SLEEP */
4405 static int __init dw_mci_init(void)
4407 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4408 pr_info("MHSC version = %s\n", RK_SDMMC_DRIVER_VERSION);
4412 static void __exit dw_mci_exit(void)
4416 module_init(dw_mci_init);
4417 module_exit(dw_mci_exit);
4419 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4420 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4421 MODULE_LICENSE("GPL v2");