2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 * Copyright (C) 2014 - 2015 Fuzhou Rockchip Electronics Co.Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/blkdev.h>
16 #include <linux/clk.h>
17 #include <linux/debugfs.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/err.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/suspend.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/card.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/mmc/rk_mmc.h>
39 #include <linux/bitops.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/workqueue.h>
43 #include <linux/of_gpio.h>
44 #include <linux/mmc/slot-gpio.h>
45 #include <linux/clk-private.h>
46 #include <linux/rockchip/cpu.h>
47 #include <linux/rfkill-wlan.h>
48 #include <linux/mfd/syscon.h>
49 #include <linux/regmap.h>
50 #include <linux/log2.h>
51 #include <asm-generic/dma-mapping-common.h>
53 #include "rk_sdmmc_dbg.h"
54 #include <linux/regulator/rockchip_io_vol_domain.h>
55 #include "../../clk/rockchip/clk-ops.h"
57 #define RK_SDMMC_DRIVER_VERSION "Ver 2.00 2015-06-10"
59 /* Common flag combinations */
60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
63 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
65 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
66 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
67 #define DW_MCI_SEND_STATUS 1
68 #define DW_MCI_RECV_STATUS 2
69 #define DW_MCI_DMA_THRESHOLD 16
70 #define DW_MCI_FREQ_MAX 50000000 /* unit: HZ */
71 #define DW_MCI_FREQ_MIN 300000 /* unit: HZ */
73 /* Max is 250ms showed in Spec */
74 #define SDMMC_DATA_TIMEOUT_SD 500
75 #define SDMMC_DATA_TIMEOUT_SDIO 250
76 #define SDMMC_DATA_TIMEOUT_EMMC 2500
77 #define SDMMC_CMD_RTO_MAX_HOLD 200
78 #define SDMMC_WAIT_FOR_UNBUSY 2500
80 #define DW_REGS_SIZE (0x0098 + 4)
81 #define DW_REGS_NUM (0x0098 / 4)
83 #ifdef CONFIG_MMC_DW_IDMAC
84 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
85 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
86 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
90 u32 des0; /* Control Descriptor */
91 #define IDMAC_DES0_DIC BIT(1)
92 #define IDMAC_DES0_LD BIT(2)
93 #define IDMAC_DES0_FD BIT(3)
94 #define IDMAC_DES0_CH BIT(4)
95 #define IDMAC_DES0_ER BIT(5)
96 #define IDMAC_DES0_CES BIT(30)
97 #define IDMAC_DES0_OWN BIT(31)
99 u32 des1; /* Buffer sizes */
100 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
101 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
103 u32 des2; /* buffer 1 physical address */
105 u32 des3; /* buffer 2 physical address */
107 #endif /* CONFIG_MMC_DW_IDMAC */
110 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
111 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
112 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
113 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
114 extern void rk_send_wakeup_key(void);
116 #if defined(CONFIG_DEBUG_FS)
117 static int dw_mci_req_show(struct seq_file *s, void *v)
119 struct dw_mci_slot *slot = s->private;
120 struct mmc_request *mrq;
121 struct mmc_command *cmd;
122 struct mmc_command *stop;
123 struct mmc_data *data;
125 /* Make sure we get a consistent snapshot */
126 spin_lock_bh(&slot->host->lock);
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 cmd->opcode, cmd->arg, cmd->flags,
138 cmd->resp[0], cmd->resp[1], cmd->resp[2],
139 cmd->resp[2], cmd->error);
141 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
142 data->bytes_xfered, data->blocks,
143 data->blksz, data->flags, data->error);
146 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
147 stop->opcode, stop->arg, stop->flags,
148 stop->resp[0], stop->resp[1], stop->resp[2],
149 stop->resp[2], stop->error);
152 spin_unlock_bh(&slot->host->lock);
157 static int dw_mci_req_open(struct inode *inode, struct file *file)
159 return single_open(file, dw_mci_req_show, inode->i_private);
162 static const struct file_operations dw_mci_req_fops = {
163 .owner = THIS_MODULE,
164 .open = dw_mci_req_open,
167 .release = single_release,
170 static int dw_mci_regs_show(struct seq_file *s, void *v)
172 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
173 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
174 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
175 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
176 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
177 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
184 return single_open(file, dw_mci_regs_show, inode->i_private);
187 static const struct file_operations dw_mci_regs_fops = {
188 .owner = THIS_MODULE,
189 .open = dw_mci_regs_open,
192 .release = single_release,
195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
197 struct mmc_host *mmc = slot->mmc;
198 struct dw_mci *host = slot->host;
202 root = mmc->debugfs_root;
206 node = debugfs_create_file("regs", S_IRUSR, root, host,
211 node = debugfs_create_file("req", S_IRUSR, root, slot,
216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
220 node = debugfs_create_x32("pending_events", S_IRUSR, root,
221 (u32 *)&host->pending_events);
225 node = debugfs_create_x32("completed_events", S_IRUSR, root,
226 (u32 *)&host->completed_events);
233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
235 #endif /* defined(CONFIG_DEBUG_FS) */
237 static void dw_mci_set_timeout(struct dw_mci *host)
239 /* timeout (maximum) */
240 mci_writel(host, TMOUT, 0xffffffff);
243 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
245 struct mmc_data *data;
246 struct dw_mci_slot *slot = mmc_priv(mmc);
247 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
249 cmd->error = -EINPROGRESS;
253 if (cmdr == MMC_STOP_TRANSMISSION)
254 cmdr |= SDMMC_CMD_STOP;
256 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
258 if (cmd->flags & MMC_RSP_PRESENT) {
259 /* We expect a response, so set this bit */
260 cmdr |= SDMMC_CMD_RESP_EXP;
261 if (cmd->flags & MMC_RSP_136)
262 cmdr |= SDMMC_CMD_RESP_LONG;
265 if (cmd->flags & MMC_RSP_CRC)
266 cmdr |= SDMMC_CMD_RESP_CRC;
270 cmdr |= SDMMC_CMD_DAT_EXP;
271 if (data->flags & MMC_DATA_STREAM)
272 cmdr |= SDMMC_CMD_STRM_MODE;
273 if (data->flags & MMC_DATA_WRITE)
274 cmdr |= SDMMC_CMD_DAT_WR;
277 if (drv_data && drv_data->prepare_command)
278 drv_data->prepare_command(slot->host, &cmdr);
283 static void dw_mci_start_command(struct dw_mci *host,
284 struct mmc_command *cmd, u32 cmd_flags)
286 struct dw_mci_slot *slot = host->slot[0];
288 host->pre_cmd = host->cmd;
291 "start command: ARGR=0x%08x CMDR=0x%08x\n",
292 cmd->arg, cmd_flags);
294 if(SD_SWITCH_VOLTAGE == cmd->opcode){
295 /*confirm non-low-power mode*/
296 mci_writel(host, CMDARG, 0);
297 dw_mci_disable_low_power(slot);
299 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
300 __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
302 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
305 mci_writel(host, CMDARG, cmd->arg);
308 /* Fix the value to 1 in current soc */
309 if(host->mmc->hold_reg_flag)
310 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
312 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
316 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
318 dw_mci_start_command(host, data->stop, host->stop_cmdr);
321 /* DMA interface functions */
322 static void dw_mci_stop_dma(struct dw_mci *host)
324 if (host->using_dma) {
325 /* Fixme: No need to terminate edma, may cause flush op */
326 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
327 host->dma_ops->stop(host);
328 host->dma_ops->cleanup(host);
331 /* Data transfer was stopped by the interrupt handler */
332 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
335 static int dw_mci_get_dma_dir(struct mmc_data *data)
337 if (data->flags & MMC_DATA_WRITE)
338 return DMA_TO_DEVICE;
340 return DMA_FROM_DEVICE;
343 #ifdef CONFIG_MMC_DW_IDMAC
344 static void dw_mci_dma_cleanup(struct dw_mci *host)
346 struct mmc_data *data = host->data;
349 if (!data->host_cookie)
350 dma_unmap_sg(host->dev,
353 dw_mci_get_dma_dir(data));
356 static void dw_mci_idmac_reset(struct dw_mci *host)
358 u32 bmod = mci_readl(host, BMOD);
359 /* Software reset of DMA */
360 bmod |= SDMMC_IDMAC_SWRESET;
361 mci_writel(host, BMOD, bmod);
364 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
368 /* Disable and reset the IDMAC interface */
369 temp = mci_readl(host, CTRL);
370 temp &= ~SDMMC_CTRL_USE_IDMAC;
371 temp |= SDMMC_CTRL_DMA_RESET;
372 mci_writel(host, CTRL, temp);
374 /* Stop the IDMAC running */
375 temp = mci_readl(host, BMOD);
376 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
377 temp |= SDMMC_IDMAC_SWRESET;
378 mci_writel(host, BMOD, temp);
381 static void dw_mci_idmac_complete_dma(void *arg)
383 struct dw_mci *host = arg;
384 struct mmc_data *data = host->data;
386 dev_vdbg(host->dev, "DMA complete\n");
388 host->dma_ops->cleanup(host);
391 * If the card was removed, data will be NULL. No point in trying to
392 * send the stop command or waiting for NBUSY in this case.
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
396 tasklet_schedule(&host->tasklet);
400 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
404 struct idmac_desc *desc = host->sg_cpu;
406 for (i = 0; i < sg_len; i++, desc++) {
407 unsigned int length = sg_dma_len(&data->sg[i]);
408 u32 mem_addr = sg_dma_address(&data->sg[i]);
410 /* Set the OWN bit and disable interrupts for this descriptor */
411 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
414 IDMAC_SET_BUFFER1_SIZE(desc, length);
416 /* Physical address to DMA to/from */
417 desc->des2 = mem_addr;
420 /* Set first descriptor */
422 desc->des0 |= IDMAC_DES0_FD;
424 /* Set last descriptor */
425 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
426 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
427 desc->des0 |= IDMAC_DES0_LD;
432 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
436 dw_mci_translate_sglist(host, host->data, sg_len);
438 /* Select IDMAC interface */
439 temp = mci_readl(host, CTRL);
440 temp |= SDMMC_CTRL_USE_IDMAC;
441 mci_writel(host, CTRL, temp);
445 /* Enable the IDMAC */
446 temp = mci_readl(host, BMOD);
447 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
448 mci_writel(host, BMOD, temp);
450 /* Start it running */
451 mci_writel(host, PLDMND, 1);
454 static int dw_mci_idmac_init(struct dw_mci *host)
456 struct idmac_desc *p;
459 /* Number of descriptors in the ring buffer */
460 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
462 /* Forward link the descriptor list */
463 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
464 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
467 /* Set the last descriptor as the end-of-ring descriptor */
468 p->des3 = host->sg_dma;
469 p->des0 = IDMAC_DES0_ER;
471 dw_mci_idmac_reset(host);
473 /* Mask out interrupts - get Tx & Rx complete only */
474 mci_writel(host, IDSTS, IDMAC_INT_CLR);
475 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
478 /* Set the descriptor base address */
479 mci_writel(host, DBADDR, host->sg_dma);
483 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
484 .init = dw_mci_idmac_init,
485 .start = dw_mci_idmac_start_dma,
486 .stop = dw_mci_idmac_stop_dma,
487 .complete = dw_mci_idmac_complete_dma,
488 .cleanup = dw_mci_dma_cleanup,
492 static void dw_mci_edma_cleanup(struct dw_mci *host)
494 struct mmc_data *data = host->data;
497 if (!data->host_cookie)
498 dma_unmap_sg(host->dev,
499 data->sg, data->sg_len,
500 dw_mci_get_dma_dir(data));
503 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
505 dmaengine_terminate_all(host->dms->ch);
508 static void dw_mci_edmac_complete_dma(void *arg)
510 struct dw_mci *host = arg;
511 struct mmc_data *data = host->data;
513 dev_vdbg(host->dev, "DMA complete\n");
516 if(data->flags & MMC_DATA_READ)
517 /* Invalidate cache after read */
518 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
519 data->sg_len, DMA_FROM_DEVICE);
521 host->dma_ops->cleanup(host);
524 * If the card was removed, data will be NULL. No point in trying to
525 * send the stop command or waiting for NBUSY in this case.
528 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
529 tasklet_schedule(&host->tasklet);
533 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
535 struct dma_slave_config slave_config;
536 struct dma_async_tx_descriptor *desc = NULL;
537 struct scatterlist *sgl = host->data->sg;
538 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
539 u32 sg_elems = host->data->sg_len;
540 u32 fifoth_val, mburst;
542 u32 idx, rx_wmark, tx_wmark;
545 /* Set external dma config: burst size, burst width*/
546 slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
547 slave_config.src_addr = slave_config.dst_addr;
548 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
549 slave_config.src_addr_width = slave_config.dst_addr_width;
551 /* Match FIFO dma burst MSIZE with external dma config*/
552 fifoth_val = mci_readl(host, FIFOTH);
553 mburst = mszs[(fifoth_val >> 28) & 0x7];
555 /* Edmac limit burst to 16, but work around for rk3036 to 8 */
556 if (unlikely(cpu_is_rk3036()))
561 if (mburst > burst_limit) {
562 mburst = burst_limit;
563 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
565 rx_wmark = mszs[idx] - 1;
566 tx_wmark = (host->fifo_depth) / 2;
567 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
569 mci_writel(host, FIFOTH, fifoth_val);
572 slave_config.dst_maxburst = mburst;
573 slave_config.src_maxburst = slave_config.dst_maxburst;
575 if(host->data->flags & MMC_DATA_WRITE){
576 slave_config.direction = DMA_MEM_TO_DEV;
577 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
580 "Error in dw_mci edmac write configuration.\n");
584 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
585 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
588 "Cannot prepare slave write sg the dw_mci edmac!\n");
592 /* Set dw_mci_edmac_complete_dma as callback */
593 desc->callback = dw_mci_edmac_complete_dma;
594 desc->callback_param = (void *)host;
595 dmaengine_submit(desc);
597 /* Flush cache before write */
598 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
599 sg_elems, DMA_TO_DEVICE);
600 dma_async_issue_pending(host->dms->ch);
603 slave_config.direction = DMA_DEV_TO_MEM;
604 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
607 "Error in dw_mci edmac read configuration.\n");
610 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
611 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
614 "Cannot prepare slave read sg for the dw_mci edmac!\n");
617 /* set dw_mci_edmac_complete_dma as callback */
618 desc->callback = dw_mci_edmac_complete_dma;
619 desc->callback_param = (void *)host;
620 dmaengine_submit(desc);
621 dma_async_issue_pending(host->dms->ch);
625 static int dw_mci_edmac_init(struct dw_mci *host)
629 /* Request external dma channel, SHOULD decide chn in dts */
631 host->dms = (struct dw_mci_dma_slave *)kzalloc
632 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
633 if (NULL == host->dms) {
634 dev_err(host->dev, "No enough memory to alloc dms.\n");
638 host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
639 if (!host->dms->ch) {
641 "Failed to get external DMA channel\n");
650 static void dw_mci_edmac_exit(struct dw_mci *host)
652 if (NULL != host->dms) {
653 if (NULL != host->dms->ch) {
654 dma_release_channel(host->dms->ch);
655 host->dms->ch = NULL;
662 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
663 .init = dw_mci_edmac_init,
664 .exit = dw_mci_edmac_exit,
665 .start = dw_mci_edmac_start_dma,
666 .stop = dw_mci_edmac_stop_dma,
667 .complete = dw_mci_edmac_complete_dma,
668 .cleanup = dw_mci_edma_cleanup,
670 #endif /* CONFIG_MMC_DW_IDMAC */
672 static struct dma_attrs dw_mci_direct_attrs;
674 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
675 struct mmc_data *data,
678 struct scatterlist *sg;
679 unsigned int i, sg_len;
680 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
681 struct dma_attrs *attrs;
684 if (!next && data->host_cookie)
685 return data->host_cookie;
688 * We don't do DMA on "complex" transfers, i.e. with
689 * non-word-aligned buffers or lengths. Also, we don't bother
690 * with all the DMA setup overhead for short transfers.
692 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
698 for_each_sg(data->sg, sg, data->sg_len, i) {
699 if (sg->offset & 3 || sg->length & 3)
702 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
703 attrs = (data->flags & MMC_DATA_DIRECT) ? &dw_mci_direct_attrs : NULL;
704 sg_len = dma_map_sg_attrs(host->dev,
707 dw_mci_get_dma_dir(data), attrs);
710 sg_len = dma_map_sg(host->dev,
713 dw_mci_get_dma_dir(data));
719 data->host_cookie = sg_len;
724 static void dw_mci_pre_req(struct mmc_host *mmc,
725 struct mmc_request *mrq,
728 struct dw_mci_slot *slot = mmc_priv(mmc);
729 struct mmc_data *data = mrq->data;
731 if (!slot->host->use_dma || !data)
734 if (data->host_cookie) {
735 data->host_cookie = 0;
739 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
740 data->host_cookie = 0;
743 static void dw_mci_post_req(struct mmc_host *mmc,
744 struct mmc_request *mrq,
747 struct dw_mci_slot *slot = mmc_priv(mmc);
748 struct mmc_data *data = mrq->data;
750 if (!slot->host->use_dma || !data)
753 if (data->host_cookie)
754 dma_unmap_sg(slot->host->dev,
757 dw_mci_get_dma_dir(data));
758 data->host_cookie = 0;
761 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
763 #ifdef CONFIG_MMC_DW_IDMAC
764 unsigned int blksz = data->blksz;
765 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
766 u32 fifo_width = 1 << host->data_shift;
767 u32 blksz_depth = blksz / fifo_width, fifoth_val;
768 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
769 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
771 tx_wmark = (host->fifo_depth) / 2;
772 tx_wmark_invers = host->fifo_depth - tx_wmark;
776 * if blksz is not a multiple of the FIFO width
778 if (blksz % fifo_width) {
785 if (!((blksz_depth % mszs[idx]) ||
786 (tx_wmark_invers % mszs[idx]))) {
788 rx_wmark = mszs[idx] - 1;
793 * If idx is '0', it won't be tried
794 * Thus, initial values are uesed
797 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
798 mci_writel(host, FIFOTH, fifoth_val);
803 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
805 unsigned int blksz = data->blksz;
806 u32 blksz_depth, fifo_depth;
809 WARN_ON(!(data->flags & MMC_DATA_READ));
811 if (host->timing != MMC_TIMING_MMC_HS200 &&
812 host->timing != MMC_TIMING_UHS_SDR104)
815 blksz_depth = blksz / (1 << host->data_shift);
816 fifo_depth = host->fifo_depth;
818 if (blksz_depth > fifo_depth)
822 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
823 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
824 * Currently just choose blksz.
827 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
831 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
834 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
842 /* If we don't have a channel, we can't do DMA */
846 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
848 /* Fixme: No need terminate edma, may cause flush op */
849 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
850 host->dma_ops->stop(host);
857 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
858 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
862 * Decide the MSIZE and RX/TX Watermark.
863 * If current block size is same with previous size,
864 * no need to update fifoth.
866 if (host->prev_blksz != data->blksz)
867 dw_mci_adjust_fifoth(host, data);
870 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
872 /* Enable the DMA interface */
873 temp = mci_readl(host, CTRL);
874 temp |= SDMMC_CTRL_DMA_ENABLE;
875 mci_writel(host, CTRL, temp);
877 /* Disable RX/TX IRQs, let DMA handle it */
878 spin_lock_irqsave(&host->slock, flags);
879 temp = mci_readl(host, INTMASK);
880 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
881 mci_writel(host, INTMASK, temp);
882 spin_unlock_irqrestore(&host->slock, flags);
884 host->dma_ops->start(host, sg_len);
889 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
894 data->error = -EINPROGRESS;
896 //WARN_ON(host->data);
901 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
903 if (data->flags & MMC_DATA_READ) {
904 host->dir_status = DW_MCI_RECV_STATUS;
905 dw_mci_ctrl_rd_thld(host, data);
907 host->dir_status = DW_MCI_SEND_STATUS;
910 MMC_DBG_INFO_FUNC(host->mmc,
911 "Dw_mci_submit_data, blocks = %d, blksz = %d [%s]",
912 data->blocks, data->blksz, mmc_hostname(host->mmc));
914 if (dw_mci_submit_data_dma(host, data)) {
915 int flags = SG_MITER_ATOMIC;
916 if (host->data->flags & MMC_DATA_READ)
917 flags |= SG_MITER_TO_SG;
919 flags |= SG_MITER_FROM_SG;
921 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
923 host->part_buf_start = 0;
924 host->part_buf_count = 0;
926 spin_lock_irqsave(&host->slock, flag);
927 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
928 temp = mci_readl(host, INTMASK);
929 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
930 mci_writel(host, INTMASK, temp);
931 spin_unlock_irqrestore(&host->slock, flag);
933 temp = mci_readl(host, CTRL);
934 temp &= ~SDMMC_CTRL_DMA_ENABLE;
935 mci_writel(host, CTRL, temp);
938 * Use the initial fifoth_val for PIO mode.
939 * If next issued data may be transfered by DMA mode,
940 * prev_blksz should be invalidated.
942 mci_writel(host, FIFOTH, host->fifoth_val);
943 host->prev_blksz = 0;
946 * Keep the current block size.
947 * It will be used to decide whether to update
948 * fifoth register next time.
950 host->prev_blksz = data->blksz;
954 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
956 struct dw_mci *host = slot->host;
957 unsigned long timeout = jiffies + msecs_to_jiffies(500);
958 unsigned int cmd_status = 0;
960 #ifdef SDMMC_WAIT_FOR_UNBUSY
962 timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
964 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
966 ret = time_before(jiffies, timeout);
967 cmd_status = mci_readl(host, STATUS);
969 (SDMMC_STAUTS_DATA_BUSY |
970 SDMMC_STAUTS_MC_BUSY)))
975 MMC_DBG_ERR_FUNC(host->mmc,
976 "mci_send_cmd: wait for unbusy timeout! [%s]",
977 mmc_hostname(host->mmc));
981 mci_writel(host, CMDARG, arg);
983 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
984 if(cmd & SDMMC_CMD_UPD_CLK)
985 timeout = jiffies + msecs_to_jiffies(50);
987 timeout = jiffies + msecs_to_jiffies(500);
989 while (time_before(jiffies, timeout)) {
990 cmd_status = mci_readl(host, CMD);
991 if (!(cmd_status & SDMMC_CMD_START))
995 dev_err(&slot->mmc->class_dev,
996 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
997 cmd, arg, cmd_status);
1000 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1002 struct dw_mci *host = slot->host;
1003 unsigned int tempck,clock = slot->clock;
1008 MMC_DBG_INFO_FUNC(host->mmc,
1009 "%s: clock=%d, current_speed=%d, bus_hz=%d, forc=%d[%s]\n",
1010 __FUNCTION__, clock, host->current_speed, host->bus_hz,
1011 force_clkinit, mmc_hostname(host->mmc));
1014 mci_writel(host, CLKENA, 0);
1015 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1016 if(host->svi_flags == 0)
1017 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1019 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1021 } else if (clock != host->current_speed || force_clkinit) {
1022 div = host->bus_hz / clock;
1023 if (host->bus_hz % clock && host->bus_hz > clock)
1025 * move the + 1 after the divide to prevent
1026 * over-clocking the card.
1030 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1032 if ((clock << div) != slot->__clk_old || force_clkinit) {
1033 tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1034 dev_info(&slot->mmc->class_dev,
1035 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1036 slot->id, host->bus_hz, clock,
1039 host->set_speed = tempck;
1040 host->set_div = div;
1044 mci_writel(host, CLKENA, 0);
1045 mci_writel(host, CLKSRC, 0);
1049 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1051 if(clock <= 400*1000){
1052 MMC_DBG_BOOT_FUNC(host->mmc,
1053 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1054 clock * 2, mmc_hostname(host->mmc));
1055 /* clk_mmc will change parents to 24MHz xtal*/
1056 clk_set_rate(host->clk_mmc, clock * 2);
1059 host->set_div = div;
1063 MMC_DBG_BOOT_FUNC(host->mmc,
1064 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1065 mmc_hostname(host->mmc));
1068 MMC_DBG_ERR_FUNC(host->mmc,
1069 "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1070 mmc_hostname(host->mmc));
1072 host->set_div = div;
1073 host->bus_hz = host->set_speed * 2;
1074 MMC_DBG_BOOT_FUNC(host->mmc,
1075 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1076 div, host->bus_hz, mmc_hostname(host->mmc));
1078 /* BUG may be here, come on, Linux BSP engineer looks!
1079 FIXME: HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1080 WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1081 some oops happened like that:
1082 mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1083 rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1084 rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1085 mmc0: new high speed DDR MMC card at address 0001
1086 mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1088 mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1089 mmcblk0: retrying using single block read
1090 mmcblk0: error -110 sending status command, retrying
1092 We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1095 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1096 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1099 host->set_div = div;
1100 host->bus_hz = host->set_speed * 2;
1101 MMC_DBG_BOOT_FUNC(host->mmc,
1102 "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1103 div, host->bus_hz, mmc_hostname(host->mmc));
1106 if (host->verid < DW_MMC_240A)
1107 clk_set_rate(host->clk_mmc,(host->bus_hz));
1109 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1115 /* set clock to desired speed */
1116 mci_writel(host, CLKDIV, div);
1120 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1122 /* enable clock; only low power if no SDIO */
1123 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1125 if (host->verid < DW_MMC_240A)
1126 sdio_int = SDMMC_INT_SDIO(slot->id);
1128 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1130 if (!(mci_readl(host, INTMASK) & sdio_int))
1131 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1132 mci_writel(host, CLKENA, clk_en_a);
1136 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1137 /* keep the clock with reflecting clock dividor */
1138 slot->__clk_old = clock << div;
1141 host->current_speed = clock;
1143 if(slot->ctype != slot->pre_ctype)
1144 MMC_DBG_BOOT_FUNC(host->mmc,
1145 "Bus speed=%dHz,Bus width=%s.[%s]",
1147 (slot->ctype == SDMMC_CTYPE_4BIT) ? "4bits" : "8bits",
1148 mmc_hostname(host->mmc));
1150 slot->pre_ctype = slot->ctype;
1152 /* Set the current slot bus width */
1153 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1156 extern struct mmc_card *this_card;
1157 static void dw_mci_wait_unbusy(struct dw_mci *host)
1159 unsigned int timeout = SDMMC_DATA_TIMEOUT_SDIO;
1160 unsigned long time_loop;
1161 unsigned int status;
1162 unsigned int tmo = 300000;
1163 /* Secure erase flag */
1166 MMC_DBG_INFO_FUNC(host->mmc,
1167 "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1169 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1170 if (host->cmd && (host->cmd->opcode == MMC_ERASE) && this_card) {
1171 /* Special care for (secure)erase timeout calculation */
1172 if ((host->cmd->arg & (0x1 << 31)) == 1)
1175 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1177 (timeout = (this_card->ext_csd.hc_erase_timeout) *
1178 tmo * (this_card->ext_csd.sec_erase_mult)) :
1179 (timeout = (this_card->ext_csd.hc_erase_timeout) * tmo);
1182 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1183 timeout = SDMMC_DATA_TIMEOUT_EMMC;
1184 } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1185 timeout = SDMMC_DATA_TIMEOUT_SD;
1188 time_loop = jiffies + msecs_to_jiffies(timeout);
1190 status = mci_readl(host, STATUS);
1191 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1193 } while (time_before(jiffies, time_loop));
1196 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1199 * 0--status is busy.
1200 * 1--status is unbusy.
1202 int dw_mci_card_busy(struct mmc_host *mmc)
1204 struct dw_mci_slot *slot = mmc_priv(mmc);
1205 struct dw_mci *host = slot->host;
1207 MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1208 host->svi_flags, mmc_hostname(host->mmc));
1211 if(host->svi_flags == 0){
1213 host->svi_flags = 1;
1214 return host->svi_flags;
1217 host->svi_flags = 0;
1218 return host->svi_flags;
1224 static void __dw_mci_start_request(struct dw_mci *host,
1225 struct dw_mci_slot *slot,
1226 struct mmc_command *cmd)
1228 struct mmc_request *mrq;
1229 struct mmc_data *data;
1233 if (host->pdata->select_slot)
1234 host->pdata->select_slot(slot->id);
1236 host->cur_slot = slot;
1239 dw_mci_wait_unbusy(host);
1241 host->pending_events = 0;
1242 host->completed_events = 0;
1243 host->data_status = 0;
1244 host->cmd_status = 0;
1248 dw_mci_set_timeout(host);
1249 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1250 mci_writel(host, BLKSIZ, data->blksz);
1253 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1255 /* this is the first command, send the initialization clock */
1256 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1257 cmdflags |= SDMMC_CMD_INIT;
1260 dw_mci_submit_data(host, data);
1264 dw_mci_start_command(host, cmd, cmdflags);
1267 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1270 static void dw_mci_start_request(struct dw_mci *host,
1271 struct dw_mci_slot *slot)
1273 struct mmc_request *mrq = slot->mrq;
1274 struct mmc_command *cmd;
1276 MMC_DBG_INFO_FUNC(host->mmc,
1277 " Begin to start the new request. cmd=%d(arg=0x%x)[%s]",
1278 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1280 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1281 __dw_mci_start_request(host, slot, cmd);
1284 /* must be called with host->lock held */
1285 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1286 struct mmc_request *mrq)
1288 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1293 if (host->state == STATE_IDLE) {
1294 host->state = STATE_SENDING_CMD;
1295 dw_mci_start_request(host, slot);
1297 list_add_tail(&slot->queue_node, &host->queue);
1301 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1303 struct dw_mci_slot *slot = mmc_priv(mmc);
1304 struct dw_mci *host = slot->host;
1309 * The check for card presence and queueing of the request must be
1310 * atomic, otherwise the card could be removed in between and the
1311 * request wouldn't fail until another card was inserted.
1313 spin_lock_bh(&host->lock);
1315 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1316 spin_unlock_bh(&host->lock);
1317 mrq->cmd->error = -ENOMEDIUM;
1318 MMC_DBG_CMD_FUNC(host->mmc, "%s: no card,so reqeuest done, cmd=%d [%s]",
1319 __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1321 mmc_request_done(mmc, mrq);
1325 MMC_DBG_CMD_FUNC(host->mmc,
1326 "======>\n pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]",
1327 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1329 dw_mci_queue_request(host, slot, mrq);
1331 spin_unlock_bh(&host->lock);
1334 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1336 struct dw_mci_slot *slot = mmc_priv(mmc);
1337 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1338 struct dw_mci *host = slot->host;
1340 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1343 #ifdef SDMMC_WAIT_FOR_UNBUSY
1344 unsigned long time_loop;
1347 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1348 if(host->svi_flags == 1)
1349 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1351 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1353 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1356 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1357 printk("%d..%s: no card. [%s]\n", \
1358 __LINE__, __FUNCTION__, mmc_hostname(mmc));
1363 ret = time_before(jiffies, time_loop);
1364 regs = mci_readl(slot->host, STATUS);
1365 if (!(regs & (SDMMC_STAUTS_DATA_BUSY |
1366 SDMMC_STAUTS_MC_BUSY)))
1372 printk("slot->flags = %lu ", slot->flags);
1373 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1374 if(host->svi_flags != 1)
1377 printk("%s: wait for unbusy timeout....... STATUS = 0x%x [%s]\n",
1378 __FUNCTION__, regs, mmc_hostname(mmc));
1382 switch (ios->bus_width) {
1383 case MMC_BUS_WIDTH_4:
1384 slot->ctype = SDMMC_CTYPE_4BIT;
1386 case MMC_BUS_WIDTH_8:
1387 slot->ctype = SDMMC_CTYPE_8BIT;
1390 /* set default 1 bit mode */
1391 slot->ctype = SDMMC_CTYPE_1BIT;
1392 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1395 regs = mci_readl(slot->host, UHS_REG);
1398 if (ios->timing == MMC_TIMING_UHS_DDR50)
1399 regs |= ((0x1 << slot->id) << 16);
1401 regs &= ~((0x1 << slot->id) << 16);
1403 mci_writel(slot->host, UHS_REG, regs);
1404 slot->host->timing = ios->timing;
1407 * Use mirror of ios->clock to prevent race with mmc
1408 * core ios update when finding the minimum.
1410 slot->clock = ios->clock;
1412 if (drv_data && drv_data->set_ios)
1413 drv_data->set_ios(slot->host, ios);
1415 /* Slot specific timing and width adjustment */
1416 dw_mci_setup_bus(slot, false);
1420 switch (ios->power_mode) {
1423 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1424 if (slot->host->pdata->setpower)
1425 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1426 regs = mci_readl(slot->host, PWREN);
1427 regs |= (1 << slot->id);
1428 mci_writel(slot->host, PWREN, regs);
1431 /* Power down slot */
1432 if(slot->host->pdata->setpower)
1433 slot->host->pdata->setpower(slot->id, 0);
1434 regs = mci_readl(slot->host, PWREN);
1435 regs &= ~(1 << slot->id);
1436 mci_writel(slot->host, PWREN, regs);
1443 static int dw_mci_get_ro(struct mmc_host *mmc)
1446 struct dw_mci_slot *slot = mmc_priv(mmc);
1447 struct dw_mci_board *brd = slot->host->pdata;
1449 /* Use platform get_ro function, else try on board write protect */
1450 if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1452 else if(brd->get_ro)
1453 read_only = brd->get_ro(slot->id);
1454 else if(gpio_is_valid(slot->wp_gpio))
1455 read_only = gpio_get_value(slot->wp_gpio);
1458 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1460 dev_dbg(&mmc->class_dev, "card is %s\n",
1461 read_only ? "read-only" : "read-write");
1466 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1468 struct dw_mci_slot *slot = mmc_priv(mmc);
1469 struct dw_mci *host = slot->host;
1471 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1474 spin_lock_bh(&host->lock);
1477 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1479 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1481 spin_unlock_bh(&host->lock);
1483 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1484 if (__clk_is_enabled(host->hclk_mmc) == false)
1485 clk_prepare_enable(host->hclk_mmc);
1486 if (__clk_is_enabled(host->clk_mmc) == false)
1487 clk_prepare_enable(host->clk_mmc);
1489 if (__clk_is_enabled(host->clk_mmc) == true)
1490 clk_disable_unprepare(slot->host->clk_mmc);
1491 if (__clk_is_enabled(host->hclk_mmc) == true)
1492 clk_disable_unprepare(slot->host->hclk_mmc);
1495 mmc_detect_change(slot->mmc, 20);
1501 static int dw_mci_get_cd(struct mmc_host *mmc)
1504 struct dw_mci_slot *slot = mmc_priv(mmc);
1505 struct dw_mci_board *brd = slot->host->pdata;
1506 struct dw_mci *host = slot->host;
1507 int gpio_cd = mmc_gpio_get_cd(mmc);
1508 int force_jtag_bit, force_jtag_reg;
1512 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1513 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1514 gpio_cd = slot->cd_gpio;
1515 irq = gpio_to_irq(gpio_cd);
1516 if (gpio_is_valid(gpio_cd)) {
1517 gpio_val = gpio_get_value(gpio_cd);
1518 if (soc_is_rk3036()) {
1519 force_jtag_bit = 11;
1520 force_jtag_reg = RK312X_GRF_SOC_CON0;
1521 } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1522 force_jtag_reg = RK312X_GRF_SOC_CON0;
1526 if (gpio_val == gpio_get_value(gpio_cd)) {
1527 gpio_cd = (gpio_val == 0 ? 1 : 0);
1529 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1530 /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1531 grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1533 dw_mci_ctrl_all_reset(host);
1535 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1536 /* Really card detected: SHOULD disable force_jtag */
1537 grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1542 gpio_val = gpio_get_value(gpio_cd);
1544 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
1545 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1546 return slot->last_detect_state;
1549 dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1553 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1554 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1556 /* Use platform get_cd function, else try onboard card detect */
1557 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1559 else if (brd->get_cd)
1560 present = !brd->get_cd(slot->id);
1561 else if (!IS_ERR_VALUE(gpio_cd))
1564 present = ((mci_readl(slot->host, CDETECT) & (1 << slot->id))
1567 spin_lock_bh(&host->lock);
1569 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1570 dev_dbg(&mmc->class_dev, "card is present\n");
1572 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1573 dev_dbg(&mmc->class_dev, "card is not present\n");
1575 spin_unlock_bh(&host->lock);
1582 * Dts Should caps emmc controller with poll-hw-reset
1584 static void dw_mci_hw_reset(struct mmc_host *mmc)
1586 struct dw_mci_slot *slot = mmc_priv(mmc);
1587 struct dw_mci *host = slot->host;
1592 unsigned long timeout;
1595 /* (1) CMD12 to end any transfer in process */
1596 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1597 | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1599 if(host->mmc->hold_reg_flag)
1600 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1601 mci_writel(host, CMDARG, 0);
1603 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1605 timeout = jiffies + msecs_to_jiffies(500);
1607 ret = time_before(jiffies, timeout);
1608 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1613 MMC_DBG_ERR_FUNC(host->mmc,
1614 "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1615 __func__, mmc_hostname(host->mmc));
1617 /* (2) wait DTO, even if no response is sent back by card */
1619 timeout = jiffies + msecs_to_jiffies(5);
1621 ret = time_before(jiffies, timeout);
1622 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1623 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1629 /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1631 /* Software reset - BMOD[0] for IDMA only */
1632 regs = mci_readl(host, BMOD);
1633 regs |= SDMMC_IDMAC_SWRESET;
1634 mci_writel(host, BMOD, regs);
1635 udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1636 regs = mci_readl(host, BMOD);
1637 if(regs & SDMMC_IDMAC_SWRESET)
1638 MMC_DBG_WARN_FUNC(host->mmc,
1639 "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1640 __func__, mmc_hostname(host->mmc));
1642 /* DMA reset - CTRL[2] */
1643 regs = mci_readl(host, CTRL);
1644 regs |= SDMMC_CTRL_DMA_RESET;
1645 mci_writel(host, CTRL, regs);
1646 udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1647 regs = mci_readl(host, CTRL);
1648 if(regs & SDMMC_CTRL_DMA_RESET)
1649 MMC_DBG_WARN_FUNC(host->mmc,
1650 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1651 __func__, mmc_hostname(host->mmc));
1653 /* FIFO reset - CTRL[1] */
1654 regs = mci_readl(host, CTRL);
1655 regs |= SDMMC_CTRL_FIFO_RESET;
1656 mci_writel(host, CTRL, regs);
1657 mdelay(1); /* no timing limited, 1ms is random value */
1658 regs = mci_readl(host, CTRL);
1659 if(regs & SDMMC_CTRL_FIFO_RESET)
1660 MMC_DBG_WARN_FUNC(host->mmc,
1661 "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1662 __func__, mmc_hostname(host->mmc));
1665 According to eMMC spec
1666 tRstW >= 1us ; RST_n pulse width
1667 tRSCA >= 200us ; RST_n to Command time
1668 tRSTH >= 1us ; RST_n high period
1670 mci_writel(slot->host, PWREN, 0x0);
1671 mci_writel(slot->host, RST_N, 0x0);
1673 udelay(10); /* 10us for bad quality eMMc. */
1675 mci_writel(slot->host, PWREN, 0x1);
1676 mci_writel(slot->host, RST_N, 0x1);
1678 usleep_range(500, 1000); /* at least 500(> 200us) */
1682 * Disable lower power mode.
1684 * Low power mode will stop the card clock when idle. According to the
1685 * description of the CLKENA register we should disable low power mode
1686 * for SDIO cards if we need SDIO interrupts to work.
1688 * This function is fast if low power mode is already disabled.
1690 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1692 struct dw_mci *host = slot->host;
1694 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1696 clk_en_a = mci_readl(host, CLKENA);
1698 if (clk_en_a & clken_low_pwr) {
1699 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1700 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1701 SDMMC_CMD_PRV_DAT_WAIT, 0);
1705 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1707 struct dw_mci_slot *slot = mmc_priv(mmc);
1708 struct dw_mci *host = slot->host;
1709 unsigned long flags;
1713 spin_lock_irqsave(&host->slock, flags);
1715 /* Enable/disable Slot Specific SDIO interrupt */
1716 int_mask = mci_readl(host, INTMASK);
1718 if (host->verid < DW_MMC_240A)
1719 sdio_int = SDMMC_INT_SDIO(slot->id);
1721 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1725 * Turn off low power mode if it was enabled. This is a bit of
1726 * a heavy operation and we disable / enable IRQs a lot, so
1727 * we'll leave low power mode disabled and it will get
1728 * re-enabled again in dw_mci_setup_bus().
1730 dw_mci_disable_low_power(slot);
1732 mci_writel(host, INTMASK,
1733 (int_mask | sdio_int));
1735 mci_writel(host, INTMASK,
1736 (int_mask & ~sdio_int));
1739 spin_unlock_irqrestore(&host->slock, flags);
1742 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1744 IO_DOMAIN_12 = 1200,
1745 IO_DOMAIN_18 = 1800,
1746 IO_DOMAIN_33 = 3300,
1748 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1758 MMC_DBG_ERR_FUNC(host->mmc,
1759 "%s : Not support io domain voltage [%s]\n",
1760 __FUNCTION__, mmc_hostname(host->mmc));
1763 MMC_DBG_ERR_FUNC(host->mmc,
1764 "%s : Err io domain voltage [%s]\n",
1765 __FUNCTION__, mmc_hostname(host->mmc));
1769 if (cpu_is_rk3288()) {
1770 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1771 grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1774 } else if (host->cid == DW_MCI_TYPE_RK3368) {
1775 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1776 regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1780 MMC_DBG_ERR_FUNC(host->mmc,
1781 "%s : unknown chip [%s]\n",
1782 __FUNCTION__, mmc_hostname(host->mmc));
1786 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1787 struct mmc_ios *ios)
1790 unsigned int value,uhs_reg;
1793 * Signal Voltage Switching is only applicable for Host Controllers
1796 if (host->verid < DW_MMC_240A)
1799 uhs_reg = mci_readl(host, UHS_REG);
1800 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: vol=%d.[%s]\n",
1801 __FUNCTION__, ios->signal_voltage, mmc_hostname(host->mmc));
1803 switch (ios->signal_voltage) {
1804 case MMC_SIGNAL_VOLTAGE_330:
1805 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1807 if (cpu_is_rk3288())
1808 ret = io_domain_regulator_set_voltage(
1809 host->vmmc, 3300000, 3300000);
1811 ret = regulator_set_voltage(host->vmmc,
1814 /* regulator_put(host->vmmc); */
1815 MMC_DBG_SW_VOL_FUNC(host->mmc,"%s =%dmV set 3.3 end, ret = %d\n",
1816 __func__, regulator_get_voltage(host->vmmc), ret);
1818 MMC_DBG_SW_VOL_FUNC(host->mmc,
1819 "%s: Switching to 3.3V signalling voltage "
1820 " failed\n", mmc_hostname(host->mmc));
1823 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1826 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: [%s]\n",
1827 __FUNCTION__, mmc_hostname(host->mmc));
1829 /* set High-power mode */
1830 value = mci_readl(host, CLKENA);
1831 value &= ~SDMMC_CLKEN_LOW_PWR;
1832 mci_writel(host,CLKENA , value);
1834 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1835 mci_writel(host,UHS_REG , uhs_reg);
1838 usleep_range(5000, 5500);
1840 /* 3.3V regulator output should be stable within 5 ms */
1841 uhs_reg = mci_readl(host, UHS_REG);
1842 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1845 MMC_DBG_SW_VOL_FUNC(host->mmc,
1846 "%s: 3.3V regulator output did not became stable\n",
1847 mmc_hostname(host->mmc));
1850 case MMC_SIGNAL_VOLTAGE_180:
1852 if (cpu_is_rk3288())
1853 ret = io_domain_regulator_set_voltage(
1854 host->vmmc, 1800000, 1800000);
1856 ret = regulator_set_voltage(
1857 host->vmmc, 1800000, 1800000);
1858 /* regulator_put(host->vmmc); */
1859 MMC_DBG_SW_VOL_FUNC(host->mmc,
1860 "%s =%dmV set 1.8end, ret=%d . \n",
1861 __func__, regulator_get_voltage(host->vmmc), ret);
1863 MMC_DBG_SW_VOL_FUNC(host->mmc,
1864 "%s: Switching to 1.8V signalling voltage "
1865 " failed\n", mmc_hostname(host->mmc));
1868 dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1872 * Enable 1.8V Signal Enable in the Host Control2
1875 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1878 usleep_range(5000, 5500);
1879 MMC_DBG_SW_VOL_FUNC(host->mmc, "%d..%s: .[%s]\n",__LINE__,
1880 __FUNCTION__, mmc_hostname(host->mmc));
1882 /* 1.8V regulator output should be stable within 5 ms */
1883 uhs_reg = mci_readl(host, UHS_REG);
1884 if (uhs_reg & SDMMC_UHS_VOLT_REG_18)
1887 MMC_DBG_SW_VOL_FUNC(host->mmc,
1888 "%s: 1.8V regulator output did not became stable\n",
1889 mmc_hostname(host->mmc));
1892 case MMC_SIGNAL_VOLTAGE_120:
1894 if (cpu_is_rk3288())
1895 ret = io_domain_regulator_set_voltage(
1896 host->vmmc, 1200000, 1200000);
1898 ret = regulator_set_voltage(host->vmmc,
1901 MMC_DBG_SW_VOL_FUNC(host->mmc,
1902 "%s: Switching to 1.2V signalling voltage "
1903 " failed\n", mmc_hostname(host->mmc));
1909 /* No signal voltage switch required */
1915 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1916 struct mmc_ios *ios)
1918 struct dw_mci_slot *slot = mmc_priv(mmc);
1919 struct dw_mci *host = slot->host;
1922 if (host->verid < DW_MMC_240A)
1925 err = dw_mci_do_start_signal_voltage_switch(host, ios);
1931 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1933 struct dw_mci_slot *slot = mmc_priv(mmc);
1934 struct dw_mci *host = slot->host;
1935 const struct dw_mci_drv_data *drv_data = host->drv_data;
1936 struct dw_mci_tuning_data tuning_data;
1939 /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1940 if(cpu_is_rk3036() || cpu_is_rk312x())
1943 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1944 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1945 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1946 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1947 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1948 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1949 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1953 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1954 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1955 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1958 "Undefined command(%d) for tuning\n", opcode);
1962 if (drv_data && drv_data->execute_tuning)
1963 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1968 static void dw_mci_post_tmo(struct mmc_host *mmc)
1970 struct dw_mci_slot *slot = mmc_priv(mmc);
1971 struct dw_mci *host = slot->host;
1972 u32 i, regs, cmd_flags;
1974 unsigned long timeout = 0;
1975 bool ret_timeout = true, is_retry = false;
1978 if (host->cur_slot->mrq->data)
1979 dw_mci_stop_dma(host);
1981 offset = host->cru_reset_offset;
1982 opcode = host->mrq->cmd->opcode;
1983 host->cur_slot->mrq = NULL;
1985 host->state = STATE_IDLE;
1988 if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
1989 (opcode == MMC_SEND_TUNING_BLOCK))
1992 printk("[%s] -- Timeout recovery procedure start --\n",
1993 mmc_hostname(host->mmc));
1996 mci_writel(host, INTMASK, 0x0);
2000 mci_writel(host, CMDARG, 0);
2002 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2003 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2005 if (host->mmc->hold_reg_flag)
2006 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2008 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2010 timeout = jiffies + msecs_to_jiffies(10);
2012 while(ret_timeout) {
2013 ret_timeout = time_before(jiffies, timeout);
2014 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2018 if (false == ret_timeout) {
2019 MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
2020 mmc_hostname(host->mmc));
2021 if (host->cid == DW_MCI_TYPE_RK3368) {
2022 /* pd_peri mmc AHB bus software reset request */
2023 regmap_write(host->cru, host->cru_regsbase,
2024 (0x1<<offset)<<16 | (0x1 << offset));
2026 regmap_write(host->cru, host->cru_regsbase,
2027 (0x1<<offset)<<16 | (0x0 << offset));
2029 /* pd_peri mmc AHB bus software reset request */
2030 cru_writel(((0x1<<offset)<<16) | (0x1 << offset),
2031 host->cru_regsbase);
2033 cru_writel(((0x1<<offset)<<16) | (0x0 << offset),
2034 host->cru_regsbase);
2037 if (!dw_mci_ctrl_all_reset(host))
2039 if (is_retry == true)
2043 #ifdef CONFIG_MMC_DW_IDMAC
2044 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
2045 if (host->use_dma && host->dma_ops->init)
2046 host->dma_ops->init(host);
2050 * Restore the initial value at FIFOTH register
2051 * And Invalidate the prev_blksz with zero
2053 mci_writel(host, FIFOTH, host->fifoth_val);
2054 host->prev_blksz = 0;
2055 mci_writel(host, TMOUT, 0xFFFFFFFF);
2056 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2057 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2058 SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
2060 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2061 regs |= SDMMC_INT_CD;
2063 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2064 if (host->verid < DW_MMC_240A)
2065 sdio_int = SDMMC_INT_SDIO(0);
2067 sdio_int = SDMMC_INT_SDIO(8);
2069 if (mci_readl(host, INTMASK) & sdio_int)
2073 mci_writel(host, INTMASK, regs);
2074 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2075 for (i = 0; i < host->num_slots; i++) {
2076 struct dw_mci_slot *slot = host->slot[i];
2079 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2080 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2081 dw_mci_setup_bus(slot, true);
2084 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2085 if (ret_timeout == false) {
2092 printk("[%s] -- Timeout recovery procedure finished --\n",
2093 mmc_hostname(host->mmc));
2096 static const struct mmc_host_ops dw_mci_ops = {
2097 .request = dw_mci_request,
2098 .pre_req = dw_mci_pre_req,
2099 .post_req = dw_mci_post_req,
2100 .set_ios = dw_mci_set_ios,
2101 .get_ro = dw_mci_get_ro,
2102 .get_cd = dw_mci_get_cd,
2103 .set_sdio_status = dw_mci_set_sdio_status,
2104 .hw_reset = dw_mci_hw_reset,
2105 .enable_sdio_irq = dw_mci_enable_sdio_irq,
2106 .execute_tuning = dw_mci_execute_tuning,
2107 .post_tmo = dw_mci_post_tmo,
2108 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2109 .start_signal_voltage_switch
2110 = dw_mci_start_signal_voltage_switch,
2111 .card_busy = dw_mci_card_busy,
2115 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2116 __releases(&host->lock)
2117 __acquires(&host->lock)
2119 if (DW_MCI_SEND_STATUS == host->dir_status){
2120 dw_mci_wait_unbusy(host);
2124 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2125 __releases(&host->lock)
2126 __acquires(&host->lock)
2128 struct dw_mci_slot *slot;
2129 struct mmc_host *prev_mmc = host->cur_slot->mmc;
2131 //WARN_ON(host->cmd || host->data);
2133 dw_mci_deal_data_end(host, mrq);
2136 MMC_DBG_CMD_FUNC(host->mmc,
2137 " reqeust end--reqeuest done, cmd=%d, "
2138 "cmderr=%d, host->state=%d [%s]",
2139 mrq->cmd->opcode, mrq->cmd->error,
2140 host->state,mmc_hostname(host->mmc));
2142 MMC_DBG_CMD_FUNC(host->mmc,
2143 " reqeust end--reqeuest done, cmd=%d, "
2144 "dataerr=%d, host->state=%d [%s]",
2145 mrq->cmd->opcode,mrq->data->error,
2146 host->state, mmc_hostname(host->mmc));
2148 host->cur_slot->mrq = NULL;
2150 if (!list_empty(&host->queue)) {
2151 slot = list_entry(host->queue.next,
2152 struct dw_mci_slot, queue_node);
2153 list_del(&slot->queue_node);
2154 dev_vdbg(host->dev, "list not empty: %s is next\n",
2155 mmc_hostname(slot->mmc));
2156 host->state = STATE_SENDING_CMD;
2157 MMC_DBG_CMD_FUNC(host->mmc,
2158 " list is not empty. run the request in list. [%s]",
2159 mmc_hostname(host->mmc));
2160 dw_mci_start_request(host, slot);
2162 dev_vdbg(host->dev, "list empty\n");
2163 host->state = STATE_IDLE;
2166 spin_unlock(&host->lock);
2167 mmc_request_done(prev_mmc, mrq);
2168 spin_lock(&host->lock);
2171 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2173 u32 status = host->cmd_status;
2175 host->cmd_status = 0;
2177 /* Read the response from the card (up to 16 bytes) */
2178 if (cmd->flags & MMC_RSP_PRESENT) {
2179 if (cmd->flags & MMC_RSP_136) {
2180 cmd->resp[3] = mci_readl(host, RESP0);
2181 cmd->resp[2] = mci_readl(host, RESP1);
2182 cmd->resp[1] = mci_readl(host, RESP2);
2183 cmd->resp[0] = mci_readl(host, RESP3);
2185 MMC_DBG_INFO_FUNC(host->mmc,
2186 "Command complete cmd=%d, "
2187 "resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]",
2188 cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0],
2189 mmc_hostname(host->mmc));
2191 cmd->resp[0] = mci_readl(host, RESP0);
2195 MMC_DBG_INFO_FUNC(host->mmc,
2196 "Command complete cmd=%d,resp[0]=0x%x. [%s]",
2197 cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2201 if (status & SDMMC_INT_RTO)
2203 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2206 cmd->error = -ETIMEDOUT;
2207 }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2208 cmd->error = -EILSEQ;
2209 }else if (status & SDMMC_INT_RESP_ERR){
2215 MMC_DBG_CMD_FUNC(host->mmc,
2216 "Command complete, cmd=%d,cmdError=%d [%s]",
2217 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2220 if(MMC_SEND_STATUS != cmd->opcode)
2221 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2222 MMC_DBG_CMD_FUNC(host->mmc,
2223 "Command complete, cmd=%d,cmdError=%d [%s]",
2224 cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2228 /* newer ip versions need a delay between retries */
2229 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2234 static void dw_mci_tasklet_func(unsigned long priv)
2236 struct dw_mci *host = (struct dw_mci *)priv;
2237 struct dw_mci_slot *slot = mmc_priv(host->mmc);
2238 struct mmc_data *data;
2239 struct mmc_command *cmd;
2240 enum dw_mci_state state;
2241 enum dw_mci_state prev_state;
2242 u32 status, cmd_flags;
2243 unsigned long timeout = 0;
2246 spin_lock(&host->lock);
2248 state = host->state;
2258 case STATE_SENDING_CMD:
2259 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2260 &host->pending_events))
2265 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2266 dw_mci_command_complete(host, cmd);
2267 if (cmd == host->mrq->sbc && !cmd->error) {
2268 prev_state = state = STATE_SENDING_CMD;
2269 __dw_mci_start_request(host, host->cur_slot,
2274 if (cmd->data && cmd->error) {
2275 dw_mci_stop_dma(host);
2278 send_stop_cmd(host, data);
2279 state = STATE_SENDING_STOP;
2282 /* host->data = NULL; */
2285 send_stop_abort(host, data);
2286 state = STATE_SENDING_STOP;
2289 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2292 if (!host->mrq->data || cmd->error) {
2293 dw_mci_request_end(host, host->mrq);
2297 prev_state = state = STATE_SENDING_DATA;
2300 case STATE_SENDING_DATA:
2301 if (test_and_clear_bit(EVENT_DATA_ERROR,
2302 &host->pending_events)) {
2303 dw_mci_stop_dma(host);
2306 send_stop_cmd(host, data);
2308 /*single block read/write, send stop cmd
2309 manually to prevent host controller halt*/
2310 MMC_DBG_INFO_FUNC(host->mmc,
2311 "%s status 1 0x%08x [%s]\n",
2312 __func__, mci_readl(host, STATUS),
2313 mmc_hostname(host->mmc));
2315 mci_writel(host, CMDARG, 0);
2317 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2318 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2320 if(host->mmc->hold_reg_flag)
2321 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2323 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2325 timeout = jiffies + msecs_to_jiffies(500);
2328 ret = time_before(jiffies, timeout);
2329 if (!(mci_readl(host, CMD) & SDMMC_CMD_START))
2333 MMC_DBG_ERR_FUNC(host->mmc,
2334 "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2335 __func__, mmc_hostname(host->mmc));
2338 send_stop_abort(host, data);
2340 state = STATE_DATA_ERROR;
2344 MMC_DBG_CMD_FUNC(host->mmc,
2345 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2346 "wait for EVENT_XFER_COMPLETE.[%s]",
2347 prev_state, state, mmc_hostname(host->mmc));
2349 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2350 &host->pending_events))
2352 MMC_DBG_INFO_FUNC(host->mmc,
2353 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2354 "wait for EVENT_DATA_COMPLETE. [%s]",
2355 prev_state, state, mmc_hostname(host->mmc));
2357 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2358 prev_state = state = STATE_DATA_BUSY;
2361 case STATE_DATA_BUSY:
2362 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2363 &host->pending_events))
2366 dw_mci_deal_data_end(host, host->mrq);
2367 MMC_DBG_INFO_FUNC(host->mmc,
2368 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, "
2369 "after EVENT_DATA_COMPLETE. [%s]",
2370 prev_state, state, mmc_hostname(host->mmc));
2372 /* host->data = NULL; */
2373 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2374 status = host->data_status;
2376 if (status & DW_MCI_DATA_ERROR_FLAGS) {
2377 if((SDMMC_CTYPE_1BIT != slot->ctype) &&
2378 (MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2379 MMC_DBG_ERR_FUNC(host->mmc,
2380 "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,"
2381 "datastatus=0x%x [%s]",
2382 prev_state, state, status, mmc_hostname(host->mmc));
2384 if (status & SDMMC_INT_DRTO) {
2385 data->error = -ETIMEDOUT;
2386 } else if (status & SDMMC_INT_DCRC) {
2387 data->error = -EILSEQ;
2388 } else if (status & SDMMC_INT_EBE &&
2389 host->dir_status == DW_MCI_SEND_STATUS){
2391 * No data CRC status was returned.
2392 * The number of bytes transferred will
2393 * be exaggerated in PIO mode.
2395 data->bytes_xfered = 0;
2396 data->error = -ETIMEDOUT;
2405 * After an error, there may be data lingering
2406 * in the FIFO, so reset it - doing so
2407 * generates a block interrupt, hence setting
2408 * the scatter-gather pointer to NULL.
2410 dw_mci_fifo_reset(host);
2412 data->bytes_xfered = data->blocks * data->blksz;
2417 MMC_DBG_CMD_FUNC(host->mmc,
2418 "Pre-state[%d]-->NowState[%d]: "
2419 "no stop and no dataerr, exit [%s]",
2420 prev_state, state, mmc_hostname(host->mmc));
2421 dw_mci_request_end(host, host->mrq);
2424 MMC_DBG_CMD_FUNC(host->mmc,
2425 "Pre-state[%d]-->NowState[%d]: begin to stop [%s]",
2426 prev_state, state, mmc_hostname(host->mmc));
2428 if (host->mrq->sbc && !data->error) {
2429 data->stop->error = 0;
2431 MMC_DBG_CMD_FUNC(host->mmc,
2432 "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit [%s]",
2433 prev_state,state,mmc_hostname(host->mmc));
2435 dw_mci_request_end(host, host->mrq);
2439 prev_state = state = STATE_SENDING_STOP;
2441 send_stop_cmd(host, data);
2443 MMC_DBG_CMD_FUNC(host->mmc,
2444 "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP [%s]",
2445 prev_state, state, mmc_hostname(host->mmc));
2447 case STATE_SENDING_STOP:
2448 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2449 &host->pending_events))
2452 MMC_DBG_CMD_FUNC(host->mmc,
2453 "Pre-state[%d]-->NowState[%d]: begin to send cmd12 [%s]",
2454 prev_state, state, mmc_hostname(host->mmc));
2456 /* CMD error in data command */
2457 if (host->mrq->cmd->error && host->mrq->data) {
2458 dw_mci_fifo_reset(host);
2466 dw_mci_command_complete(host, host->mrq->stop);
2468 if (host->mrq->stop)
2469 dw_mci_command_complete(host, host->mrq->stop);
2471 host->cmd_status = 0;
2474 dw_mci_request_end(host, host->mrq);
2477 case STATE_DATA_ERROR:
2478 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2479 &host->pending_events))
2482 state = STATE_DATA_BUSY;
2485 } while (state != prev_state);
2487 host->state = state;
2489 spin_unlock(&host->lock);
2492 /* push final bytes to part_buf, only use during push */
2493 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2495 memcpy((void *)&host->part_buf, buf, cnt);
2496 host->part_buf_count = cnt;
2499 /* append bytes to part_buf, only use during push */
2500 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2502 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2503 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2504 host->part_buf_count += cnt;
2508 /* pull first bytes from part_buf, only use during pull */
2509 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2511 cnt = min(cnt, (int)host->part_buf_count);
2513 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2515 host->part_buf_count -= cnt;
2516 host->part_buf_start += cnt;
2521 /* pull final bytes from the part_buf, assuming it's just been filled */
2522 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2524 memcpy(buf, &host->part_buf, cnt);
2525 host->part_buf_start = cnt;
2526 host->part_buf_count = (1 << host->data_shift) - cnt;
2529 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2531 struct mmc_data *data = host->data;
2534 /* try and push anything in the part_buf */
2535 if (unlikely(host->part_buf_count)) {
2536 int len = dw_mci_push_part_bytes(host, buf, cnt);
2539 if (host->part_buf_count == 2) {
2540 mci_writew(host, DATA(host->data_offset),
2542 host->part_buf_count = 0;
2545 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2546 if (unlikely((unsigned long)buf & 0x1)) {
2548 u16 aligned_buf[64];
2549 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2550 int items = len >> 1;
2552 /* memcpy from input buffer into aligned buffer */
2553 memcpy(aligned_buf, buf, len);
2556 /* push data from aligned buffer into fifo */
2557 for (i = 0; i < items; ++i)
2558 mci_writew(host, DATA(host->data_offset),
2565 for (; cnt >= 2; cnt -= 2)
2566 mci_writew(host, DATA(host->data_offset), *pdata++);
2569 /* put anything remaining in the part_buf */
2571 dw_mci_set_part_bytes(host, buf, cnt);
2572 /* Push data if we have reached the expected data length */
2573 if ((data->bytes_xfered + init_cnt) ==
2574 (data->blksz * data->blocks))
2575 mci_writew(host, DATA(host->data_offset),
2580 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2582 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2583 if (unlikely((unsigned long)buf & 0x1)) {
2585 /* pull data from fifo into aligned buffer */
2586 u16 aligned_buf[64];
2587 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2588 int items = len >> 1;
2590 for (i = 0; i < items; ++i)
2591 aligned_buf[i] = mci_readw(host,
2592 DATA(host->data_offset));
2593 /* memcpy from aligned buffer into output buffer */
2594 memcpy(buf, aligned_buf, len);
2602 for (; cnt >= 2; cnt -= 2)
2603 *pdata++ = mci_readw(host, DATA(host->data_offset));
2607 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2608 dw_mci_pull_final_bytes(host, buf, cnt);
2612 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2614 struct mmc_data *data = host->data;
2617 /* try and push anything in the part_buf */
2618 if (unlikely(host->part_buf_count)) {
2619 int len = dw_mci_push_part_bytes(host, buf, cnt);
2622 if (host->part_buf_count == 4) {
2623 mci_writel(host, DATA(host->data_offset),
2625 host->part_buf_count = 0;
2628 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2629 if (unlikely((unsigned long)buf & 0x3)) {
2631 u32 aligned_buf[32];
2632 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2633 int items = len >> 2;
2635 /* memcpy from input buffer into aligned buffer */
2636 memcpy(aligned_buf, buf, len);
2639 /* push data from aligned buffer into fifo */
2640 for (i = 0; i < items; ++i)
2641 mci_writel(host, DATA(host->data_offset),
2648 for (; cnt >= 4; cnt -= 4)
2649 mci_writel(host, DATA(host->data_offset), *pdata++);
2652 /* put anything remaining in the part_buf */
2654 dw_mci_set_part_bytes(host, buf, cnt);
2655 /* Push data if we have reached the expected data length */
2656 if ((data->bytes_xfered + init_cnt) ==
2657 (data->blksz * data->blocks))
2658 mci_writel(host, DATA(host->data_offset),
2663 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2665 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2666 if (unlikely((unsigned long)buf & 0x3)) {
2668 /* pull data from fifo into aligned buffer */
2669 u32 aligned_buf[32];
2670 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2671 int items = len >> 2;
2673 for (i = 0; i < items; ++i)
2674 aligned_buf[i] = mci_readl(host,
2675 DATA(host->data_offset));
2676 /* memcpy from aligned buffer into output buffer */
2677 memcpy(buf, aligned_buf, len);
2685 for (; cnt >= 4; cnt -= 4)
2686 *pdata++ = mci_readl(host, DATA(host->data_offset));
2690 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2691 dw_mci_pull_final_bytes(host, buf, cnt);
2695 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2697 struct mmc_data *data = host->data;
2700 /* try and push anything in the part_buf */
2701 if (unlikely(host->part_buf_count)) {
2702 int len = dw_mci_push_part_bytes(host, buf, cnt);
2706 if (host->part_buf_count == 8) {
2707 mci_writeq(host, DATA(host->data_offset),
2709 host->part_buf_count = 0;
2712 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2713 if (unlikely((unsigned long)buf & 0x7)) {
2715 u64 aligned_buf[16];
2716 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2717 int items = len >> 3;
2719 /* memcpy from input buffer into aligned buffer */
2720 memcpy(aligned_buf, buf, len);
2723 /* push data from aligned buffer into fifo */
2724 for (i = 0; i < items; ++i)
2725 mci_writeq(host, DATA(host->data_offset),
2732 for (; cnt >= 8; cnt -= 8)
2733 mci_writeq(host, DATA(host->data_offset), *pdata++);
2736 /* put anything remaining in the part_buf */
2738 dw_mci_set_part_bytes(host, buf, cnt);
2739 /* Push data if we have reached the expected data length */
2740 if ((data->bytes_xfered + init_cnt) ==
2741 (data->blksz * data->blocks))
2742 mci_writeq(host, DATA(host->data_offset),
2747 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2749 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2750 if (unlikely((unsigned long)buf & 0x7)) {
2752 /* pull data from fifo into aligned buffer */
2753 u64 aligned_buf[16];
2754 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2755 int items = len >> 3;
2757 for (i = 0; i < items; ++i)
2758 aligned_buf[i] = mci_readq(host,
2759 DATA(host->data_offset));
2760 /* memcpy from aligned buffer into output buffer */
2761 memcpy(buf, aligned_buf, len);
2769 for (; cnt >= 8; cnt -= 8)
2770 *pdata++ = mci_readq(host, DATA(host->data_offset));
2774 host->part_buf = mci_readq(host, DATA(host->data_offset));
2775 dw_mci_pull_final_bytes(host, buf, cnt);
2779 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2783 /* get remaining partial bytes */
2784 len = dw_mci_pull_part_bytes(host, buf, cnt);
2785 if (unlikely(len == cnt))
2790 /* get the rest of the data */
2791 host->pull_data(host, buf, cnt);
2794 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2796 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2798 unsigned int offset;
2799 struct mmc_data *data = host->data;
2800 int shift = host->data_shift;
2803 unsigned int remain, fcnt;
2805 if(!host->mmc->bus_refs){
2806 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2810 if (!sg_miter_next(sg_miter))
2813 host->sg = sg_miter->piter.sg;
2814 buf = sg_miter->addr;
2815 remain = sg_miter->length;
2819 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2820 << shift) + host->part_buf_count;
2821 len = min(remain, fcnt);
2824 dw_mci_pull_data(host, (void *)(buf + offset), len);
2825 data->bytes_xfered += len;
2830 sg_miter->consumed = offset;
2831 status = mci_readl(host, MINTSTS);
2832 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2833 /* if the RXDR is ready read again */
2834 } while ((status & SDMMC_INT_RXDR) ||
2835 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2838 if (!sg_miter_next(sg_miter))
2840 sg_miter->consumed = 0;
2842 sg_miter_stop(sg_miter);
2846 sg_miter_stop(sg_miter);
2850 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2853 static void dw_mci_write_data_pio(struct dw_mci *host)
2855 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2857 unsigned int offset;
2858 struct mmc_data *data = host->data;
2859 int shift = host->data_shift;
2862 unsigned int fifo_depth = host->fifo_depth;
2863 unsigned int remain, fcnt;
2865 if (!host->mmc->bus_refs){
2866 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2871 if (!sg_miter_next(sg_miter))
2874 host->sg = sg_miter->piter.sg;
2875 buf = sg_miter->addr;
2876 remain = sg_miter->length;
2880 fcnt = ((fifo_depth -
2881 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2882 << shift) - host->part_buf_count;
2883 len = min(remain, fcnt);
2886 host->push_data(host, (void *)(buf + offset), len);
2887 data->bytes_xfered += len;
2892 sg_miter->consumed = offset;
2893 status = mci_readl(host, MINTSTS);
2894 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2895 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2898 if (!sg_miter_next(sg_miter))
2900 sg_miter->consumed = 0;
2902 sg_miter_stop(sg_miter);
2906 sg_miter_stop(sg_miter);
2910 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2913 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2915 if (!host->cmd_status)
2916 host->cmd_status = status;
2923 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2924 tasklet_schedule(&host->tasklet);
2927 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2929 struct dw_mci *host = dev_id;
2930 u32 pending, sdio_int;
2933 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2936 * DTO fix - version 2.10a and below, and only if internal DMA
2939 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2941 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2942 pending |= SDMMC_INT_DATA_OVER;
2946 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2947 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2948 host->cmd_status = pending;
2950 MMC_DBG_INFO_FUNC(host->mmc,
2951 "%s cmd_status INT=0x%x,[%s]",
2952 __FUNCTION__, host->cmd_status,
2953 mmc_hostname(host->mmc));
2955 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2958 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2959 /* if there is an error report DATA_ERROR */
2960 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2961 host->data_status = pending;
2963 printk(KERN_ERR "[%s] Data transmission error !!!! MINTSTS: [0x%08x]\n",
2964 mmc_hostname(host->mmc), pending);
2965 mmc_retune_needed(host->mmc);
2966 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2968 MMC_DBG_INFO_FUNC(host->mmc,
2969 "%s data_status INT=0x%x,[%s]",
2970 __FUNCTION__, host->data_status,
2971 mmc_hostname(host->mmc));
2972 tasklet_schedule(&host->tasklet);
2975 if (pending & SDMMC_INT_DATA_OVER) {
2976 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2977 MMC_DBG_CMD_FUNC(host->mmc,
2978 "SDMMC_INT_DATA_OVER, INT-pending=0x%x [%s]",
2979 pending, mmc_hostname(host->mmc));
2980 if (!host->data_status)
2981 host->data_status = pending;
2983 if (host->dir_status == DW_MCI_RECV_STATUS) {
2984 if (host->sg != NULL)
2985 dw_mci_read_data_pio(host, true);
2987 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2988 tasklet_schedule(&host->tasklet);
2991 if (pending & SDMMC_INT_RXDR) {
2992 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2993 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2994 dw_mci_read_data_pio(host, false);
2997 if (pending & SDMMC_INT_TXDR) {
2998 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2999 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
3000 dw_mci_write_data_pio(host);
3003 if (pending & SDMMC_INT_VSI) {
3004 MMC_DBG_SW_VOL_FUNC(host->mmc,
3005 "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",
3006 pending, mmc_hostname(host->mmc));
3007 mci_writel(host, RINTSTS, SDMMC_INT_VSI);
3008 dw_mci_cmd_interrupt(host, pending);
3011 if (pending & SDMMC_INT_CMD_DONE) {
3012 MMC_DBG_CMD_FUNC(host->mmc,
3013 "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",
3014 mci_readl(host, CMD), pending, mmc_hostname(host->mmc));
3015 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
3016 dw_mci_cmd_interrupt(host, pending);
3019 if (pending & SDMMC_INT_CD) {
3020 mci_writel(host, RINTSTS, SDMMC_INT_CD);
3021 MMC_DBG_INFO_FUNC(host->mmc,
3022 "SDMMC_INT_CD, INT-pending=0x%x. [%s]",
3023 pending, mmc_hostname(host->mmc));
3024 wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
3025 queue_work(host->card_workqueue, &host->card_work);
3028 if (pending & SDMMC_INT_HLE) {
3029 mci_writel(host, RINTSTS, SDMMC_INT_HLE);
3030 MMC_DBG_CMD_FUNC(host->mmc,
3031 "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",
3032 pending, mmc_hostname(host->mmc));
3036 /* Handle SDIO Interrupts */
3037 for (i = 0; i < host->num_slots; i++) {
3038 struct dw_mci_slot *slot = host->slot[i];
3040 if (host->verid < DW_MMC_240A)
3041 sdio_int = SDMMC_INT_SDIO(i);
3043 sdio_int = SDMMC_INT_SDIO(i + 8);
3045 if (pending & sdio_int) {
3046 mci_writel(host, RINTSTS, sdio_int);
3047 mmc_signal_sdio_irq(slot->mmc);
3053 #ifdef CONFIG_MMC_DW_IDMAC
3054 /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3055 if (!(cpu_is_rk3036() || cpu_is_rk312x())){
3056 /* Handle DMA interrupts */
3057 pending = mci_readl(host, IDSTS);
3058 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3059 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3060 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3061 host->dma_ops->complete((void *)host);
3069 static void dw_mci_work_routine_card(struct work_struct *work)
3071 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3074 for (i = 0; i < host->num_slots; i++) {
3075 struct dw_mci_slot *slot = host->slot[i];
3076 struct mmc_host *mmc = slot->mmc;
3077 struct mmc_request *mrq;
3080 present = dw_mci_get_cd(mmc);
3082 /* Card insert, switch data line to uart function, and vice verse.
3083 ONLY audi chip need switched by software, using udbg tag in dts!
3085 if (!(IS_ERR(host->pins_udbg)) &&
3086 !(IS_ERR(host->pins_default))) {
3088 if (pinctrl_select_state(host->pinctrl,
3089 host->pins_default) < 0)
3091 "%s: Default pinctrl setting failed!\n",
3092 mmc_hostname(host->mmc));
3094 if (pinctrl_select_state(host->pinctrl,
3095 host->pins_udbg) < 0)
3097 "%s: Udbg pinctrl setting failed!\n",
3098 mmc_hostname(host->mmc));
3102 while (present != slot->last_detect_state) {
3103 dev_dbg(&slot->mmc->class_dev, "card %s\n",
3104 present ? "inserted" : "removed");
3105 MMC_DBG_BOOT_FUNC(mmc, " The card is %s. ===!!!!!!==[%s]\n",
3106 present ? "inserted" : "removed.", mmc_hostname(mmc));
3108 dw_mci_ctrl_all_reset(host);
3109 /* Stop edma when rountine card triggered */
3110 if(cpu_is_rk3036() || cpu_is_rk312x())
3111 if(host->dma_ops && host->dma_ops->stop)
3112 host->dma_ops->stop(host);
3113 rk_send_wakeup_key();//wake up system
3114 spin_lock_bh(&host->lock);
3116 /* Card change detected */
3117 slot->last_detect_state = present;
3119 /* Clean up queue if present */
3122 if (mrq == host->mrq) {
3126 switch (host->state) {
3129 case STATE_SENDING_CMD:
3130 mrq->cmd->error = -ENOMEDIUM;
3134 case STATE_SENDING_DATA:
3135 mrq->data->error = -ENOMEDIUM;
3136 dw_mci_stop_dma(host);
3138 case STATE_DATA_BUSY:
3139 case STATE_DATA_ERROR:
3140 if (mrq->data->error == -EINPROGRESS)
3141 mrq->data->error = -ENOMEDIUM;
3145 case STATE_SENDING_STOP:
3146 mrq->stop->error = -ENOMEDIUM;
3150 dw_mci_request_end(host, mrq);
3152 list_del(&slot->queue_node);
3153 mrq->cmd->error = -ENOMEDIUM;
3155 mrq->data->error = -ENOMEDIUM;
3157 mrq->stop->error = -ENOMEDIUM;
3159 MMC_DBG_CMD_FUNC(host->mmc,
3160 "dw_mci_work--reqeuest done, cmd=%d [%s]",
3161 mrq->cmd->opcode, mmc_hostname(mmc));
3163 spin_unlock(&host->lock);
3164 mmc_request_done(slot->mmc, mrq);
3165 spin_lock(&host->lock);
3169 /* Power down slot */
3171 /* Clear down the FIFO */
3172 dw_mci_fifo_reset(host);
3173 #ifdef CONFIG_MMC_DW_IDMAC
3174 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
3175 dw_mci_idmac_reset(host);
3179 spin_unlock_bh(&host->lock);
3181 present = dw_mci_get_cd(mmc);
3184 mmc_detect_change(slot->mmc,
3185 msecs_to_jiffies(host->pdata->detect_delay_ms));
3190 /* given a slot id, find out the device node representing that slot */
3191 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3193 struct device_node *np;
3197 if (!dev || !dev->of_node)
3200 for_each_child_of_node(dev->of_node, np) {
3201 addr = of_get_property(np, "reg", &len);
3202 if (!addr || (len < sizeof(int)))
3204 if (be32_to_cpup(addr) == slot)
3210 static struct dw_mci_of_slot_quirks {
3213 } of_slot_quirks[] = {
3215 .quirk = "disable-wp",
3216 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3220 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3222 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3227 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3228 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3229 quirks |= of_slot_quirks[idx].id;
3234 /* find out bus-width for a given slot */
3235 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3237 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3243 if (of_property_read_u32(np, "bus-width", &bus_wd))
3244 dev_err(dev, "bus-width property not found, assuming width"
3250 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3251 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3253 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3259 gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3261 /* Having a missing entry is valid; return silently */
3262 if (!gpio_is_valid(gpio))
3265 if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3266 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3270 gpio_direction_output(gpio, 0);//set 0 to pwr-en
3276 /* find the write protect gpio for a given slot; or -1 if none specified */
3277 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3279 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3285 gpio = of_get_named_gpio(np, "wp-gpios", 0);
3287 /* Having a missing entry is valid; return silently */
3288 if (!gpio_is_valid(gpio))
3291 if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3292 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3299 /* find the cd gpio for a given slot */
3300 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3301 struct mmc_host *mmc)
3303 struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3309 gpio = of_get_named_gpio(np, "cd-gpios", 0);
3311 /* Having a missing entry is valid; return silently */
3312 if (!gpio_is_valid(gpio))
3315 if (mmc_gpio_request_cd(mmc, gpio, 0))
3316 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3319 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3321 struct mmc_host *mmc = dev_id;
3322 struct dw_mci_slot *slot = mmc_priv(mmc);
3323 struct dw_mci *host = slot->host;
3324 int gpio_cd = slot->cd_gpio;
3326 (gpio_get_value(gpio_cd) == 0) ?
3327 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT) :
3328 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3330 /* wakeup system whether gpio debounce or not */
3331 rk_send_wakeup_key();
3333 /* no need to trigger detect flow when rescan is disabled.
3334 This case happended in dpm, that we just wakeup system and
3335 let suspend_post notify callback handle it.
3337 if(mmc->rescan_disable == 0)
3338 queue_work(host->card_workqueue, &host->card_work);
3340 printk("%s: rescan been disabled!\n", __FUNCTION__);
3345 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3346 struct mmc_host *mmc)
3348 struct dw_mci_slot *slot = mmc_priv(mmc);
3349 struct dw_mci *host = slot->host;
3353 /* Having a missing entry is valid; return silently */
3354 if (!gpio_is_valid(gpio))
3357 irq = gpio_to_irq(gpio);
3359 ret = devm_request_threaded_irq(
3360 &mmc->class_dev, irq,
3361 NULL, dw_mci_gpio_cd_irqt,
3362 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3367 "Request cd-gpio %d interrupt error!\n", gpio);
3369 /* enable wakeup event for gpio-cd in idle or deep suspend*/
3370 enable_irq_wake(irq);
3373 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3377 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3378 struct mmc_host *mmc)
3380 if (!gpio_is_valid(gpio))
3383 if (gpio_to_irq(gpio) >= 0) {
3384 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3385 devm_gpio_free(&mmc->class_dev, gpio);
3388 #else /* CONFIG_OF */
3389 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3393 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3397 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3401 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3405 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3406 struct mmc_host *mmc)
3410 #endif /* CONFIG_OF */
3412 /* @host: dw_mci host prvdata
3413 * Init pinctrl for each platform. Usually we assign
3414 * "defalut" tag for functional usage, "idle" tag for gpio
3415 * state and "udbg" tag for uart_dbg if any.
3417 static void dw_mci_init_pinctrl(struct dw_mci *host)
3419 /* Fixme: DON'T TOUCH EMMC SETTING! */
3420 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3423 /* Get pinctrl for DTS */
3424 host->pinctrl = devm_pinctrl_get(host->dev);
3425 if (IS_ERR(host->pinctrl)) {
3426 dev_err(host->dev, "%s: No pinctrl used!\n",
3427 mmc_hostname(host->mmc));
3431 /* Lookup idle state */
3433 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_IDLE);
3434 if (IS_ERR(host->pins_idle)) {
3435 dev_err(host->dev, "%s: No idle tag found!\n",
3436 mmc_hostname(host->mmc));
3438 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3440 "%s: Idle pinctrl setting failed!\n",
3441 mmc_hostname(host->mmc));
3444 /* Lookup default state */
3445 host->pins_default =
3446 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_DEFAULT);
3447 if (IS_ERR(host->pins_default)) {
3448 dev_err(host->dev, "%s: No default pinctrl found!\n",
3449 mmc_hostname(host->mmc));
3451 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3453 "%s: Default pinctrl setting failed!\n",
3454 mmc_hostname(host->mmc));
3457 /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3458 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3459 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3460 if (IS_ERR(host->pins_udbg)) {
3461 dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3462 mmc_hostname(host->mmc));
3464 if (!dw_mci_get_cd(host->mmc))
3465 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3466 dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3467 mmc_hostname(host->mmc));
3472 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3473 unsigned long mode, void *unused)
3475 struct mmc_host *host = container_of(
3476 notify_block, struct mmc_host, pm_notify);
3477 unsigned long flags;
3480 case PM_HIBERNATION_PREPARE:
3481 case PM_SUSPEND_PREPARE:
3482 dev_err(host->parent,
3483 "dw_mci_pm_notify: suspend prepare\n");
3484 spin_lock_irqsave(&host->lock, flags);
3485 host->rescan_disable = 1;
3486 spin_unlock_irqrestore(&host->lock, flags);
3487 if (cancel_delayed_work(&host->detect))
3488 wake_unlock(&host->detect_wake_lock);
3491 case PM_POST_SUSPEND:
3492 case PM_POST_HIBERNATION:
3493 case PM_POST_RESTORE:
3494 dev_err(host->parent,
3495 "dw_mci_pm_notify: post suspend\n");
3496 spin_lock_irqsave(&host->lock, flags);
3497 host->rescan_disable = 0;
3498 spin_unlock_irqrestore(&host->lock, flags);
3499 mmc_detect_change(host, 10);
3505 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3507 struct mmc_host *mmc;
3508 struct dw_mci_slot *slot;
3509 const struct dw_mci_drv_data *drv_data = host->drv_data;
3514 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3518 slot = mmc_priv(mmc);
3522 host->slot[id] = slot;
3525 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3527 mmc->ops = &dw_mci_ops;
3529 if (of_property_read_u32_array(host->dev->of_node,
3530 "clock-freq-min-max", freq, 2)) {
3531 mmc->f_min = DW_MCI_FREQ_MIN;
3532 mmc->f_max = DW_MCI_FREQ_MAX;
3534 printk("%s: fmin=%d, fmax=%d [%s]\n",
3535 __FUNCTION__, mmc->f_min,
3536 mmc->f_max, mmc_hostname(mmc));
3538 mmc->f_min = freq[0];
3539 mmc->f_max = freq[1];
3541 printk("%s: fmin=%d, fmax=%d [%s]\n",
3542 __FUNCTION__, mmc->f_min,
3543 mmc->f_max, mmc_hostname(mmc));
3546 if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3547 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3548 if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3549 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3550 if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3551 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3553 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3554 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3555 if (register_pm_notifier(&mmc->pm_notify)) {
3556 pr_err("dw_mci: register_pm_notifier failed\n");
3557 goto err_pm_notifier;
3561 if (host->cid == DW_MCI_TYPE_RK3368) {
3562 if (IS_ERR(host->grf))
3563 pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3565 /* Disable force_jtag */
3566 regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3567 } else if (cpu_is_rk3288()) {
3568 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3569 } else if (host->cid == DW_MCI_TYPE_RK3228) {
3570 grf_writel(((1 << 8) << 16) | (0 << 8), RK3228_GRF_SOC_CON6);
3573 /* We assume only low-level chip use gpio_cd */
3574 if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3575 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3576 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3577 if (gpio_is_valid(slot->cd_gpio)) {
3578 /* Request gpio int for card detection */
3579 dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3581 slot->cd_gpio = -ENODEV;
3582 dev_err(host->dev, "failed to get your cd-gpios!\n");
3586 if (host->pdata->get_ocr)
3587 mmc->ocr_avail = host->pdata->get_ocr(id);
3590 mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
3591 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33|
3592 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36 |
3593 MMC_VDD_26_27 | MMC_VDD_25_26 | MMC_VDD_24_25 |
3594 MMC_VDD_23_24 | MMC_VDD_22_23 | MMC_VDD_21_22 |
3595 MMC_VDD_20_21 | MMC_VDD_165_195;
3599 * Start with slot power disabled, it will be enabled when a card
3602 if (host->pdata->setpower)
3603 host->pdata->setpower(id, 0);
3605 if (host->pdata->caps)
3606 mmc->caps = host->pdata->caps;
3608 if (host->pdata->pm_caps)
3609 mmc->pm_caps = host->pdata->pm_caps;
3611 if (host->dev->of_node) {
3612 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3616 ctrl_id = to_platform_device(host->dev)->id;
3618 if (drv_data && drv_data->caps)
3619 mmc->caps |= drv_data->caps[ctrl_id];
3620 if (drv_data && drv_data->hold_reg_flag)
3621 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3623 /* set the compatibility of driver. */
3624 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3625 | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3627 if (host->pdata->caps2)
3628 mmc->caps2 = host->pdata->caps2;
3630 if (host->pdata->get_bus_wd)
3631 bus_width = host->pdata->get_bus_wd(slot->id);
3632 else if (host->dev->of_node)
3633 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3637 switch (bus_width) {
3639 mmc->caps |= MMC_CAP_8_BIT_DATA;
3641 mmc->caps |= MMC_CAP_4_BIT_DATA;
3644 if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3645 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3646 if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3647 mmc->caps |= MMC_CAP_SDIO_IRQ;
3648 if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3649 mmc->caps |= MMC_CAP_HW_RESET;
3650 if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3651 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3652 if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3653 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3654 if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3655 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3656 if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3657 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3659 /*Assign pm_caps pass to pm_flags*/
3660 mmc->pm_flags = mmc->pm_caps;
3662 if (host->pdata->blk_settings) {
3663 mmc->max_segs = host->pdata->blk_settings->max_segs;
3664 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3665 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3666 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3667 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3669 /* Useful defaults if platform data is unset. */
3670 #ifdef CONFIG_MMC_DW_IDMAC
3671 mmc->max_segs = host->ring_size;
3672 mmc->max_blk_size = 65536;
3673 mmc->max_seg_size = 0x1000;
3674 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
3675 mmc->max_blk_count = mmc->max_req_size / 512;
3677 if(cpu_is_rk3036() || cpu_is_rk312x()){
3678 /* fixup for external dmac setting */
3680 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3681 mmc->max_blk_count = 65535;
3682 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3683 mmc->max_seg_size = mmc->max_req_size;
3687 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3688 mmc->max_blk_count = 512;
3689 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3690 mmc->max_seg_size = mmc->max_req_size;
3691 #endif /* CONFIG_MMC_DW_IDMAC */
3695 slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3697 if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3702 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3703 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3707 if (IS_ERR(host->vmmc)) {
3708 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3711 ret = regulator_enable(host->vmmc);
3714 "failed to enable regulator: %d\n", ret);
3721 slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3723 if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3724 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3726 dw_mci_init_pinctrl(host);
3727 ret = mmc_add_host(mmc);
3731 #if defined(CONFIG_DEBUG_FS)
3732 dw_mci_init_debugfs(slot);
3735 /* Card initially undetected */
3736 slot->last_detect_state = 1;
3740 unregister_pm_notifier(&mmc->pm_notify);
3743 if (gpio_is_valid(slot->cd_gpio))
3744 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3749 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3751 /* Shutdown detect IRQ */
3752 if (slot->host->pdata->exit)
3753 slot->host->pdata->exit(id);
3755 /* Debugfs stuff is cleaned up by mmc core */
3756 mmc_remove_host(slot->mmc);
3757 slot->host->slot[id] = NULL;
3758 mmc_free_host(slot->mmc);
3761 static void dw_mci_init_dma(struct dw_mci *host)
3763 /* Alloc memory for sg translation */
3764 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3765 &host->sg_dma, GFP_KERNEL);
3766 if (!host->sg_cpu) {
3767 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3772 /* Determine which DMA interface to use */
3773 #if defined(CONFIG_MMC_DW_IDMAC)
3774 if(cpu_is_rk3036() || cpu_is_rk312x()){
3775 host->dma_ops = &dw_mci_edmac_ops;
3776 dev_info(host->dev, "Using external DMA controller.\n");
3778 host->dma_ops = &dw_mci_idmac_ops;
3779 dev_info(host->dev, "Using internal DMA controller.\n");
3786 if (host->dma_ops->init && host->dma_ops->start &&
3787 host->dma_ops->stop && host->dma_ops->cleanup) {
3788 if (host->dma_ops->init(host)) {
3789 dev_err(host->dev, "%s: Unable to initialize "
3790 "DMA Controller.\n", __func__);
3794 dev_err(host->dev, "DMA initialization not found.\n");
3802 dev_info(host->dev, "Using PIO mode.\n");
3807 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3809 unsigned long timeout = jiffies + msecs_to_jiffies(500);
3812 ctrl = mci_readl(host, CTRL);
3814 mci_writel(host, CTRL, ctrl);
3816 /* wait till resets clear */
3818 ctrl = mci_readl(host, CTRL);
3819 if (!(ctrl & reset))
3821 } while (time_before(jiffies, timeout));
3824 "Timeout resetting block (ctrl reset %#x)\n",
3830 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3833 * Reseting generates a block interrupt, hence setting
3834 * the scatter-gather pointer to NULL.
3837 sg_miter_stop(&host->sg_miter);
3841 return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3844 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3846 return dw_mci_ctrl_reset(host,
3847 SDMMC_CTRL_FIFO_RESET |
3849 SDMMC_CTRL_DMA_RESET);
3852 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3857 buffer = host->regs_buffer;
3859 for (index = 0; index < DW_REGS_NUM ; index++){
3860 *buffer = mci_readreg(host, index*4);
3861 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3862 dw_mci_regs[index].name, *buffer);
3866 *buffer = mci_readl(host,CDTHRCTL);
3867 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3870 static void dw_mci_rst_post_resume(struct dw_mci *host)
3875 buffer = host->regs_buffer;
3877 for (index = 0; index < DW_REGS_NUM; index++){
3878 mci_writereg(host, index*4, *buffer);
3881 mci_writel(host, CDTHRCTL, *buffer);
3884 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3885 .pre_suspend = dw_mci_rst_pre_suspend,
3886 .post_resume = dw_mci_rst_post_resume,
3891 static struct dw_mci_of_quirks {
3896 .quirk = "broken-cd",
3897 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3901 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3903 struct dw_mci_board *pdata;
3904 struct device *dev = host->dev;
3905 struct device_node *np = dev->of_node;
3906 const struct dw_mci_drv_data *drv_data = host->drv_data;
3908 u32 clock_frequency;
3910 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3912 dev_err(dev, "could not allocate memory for pdata\n");
3913 return ERR_PTR(-ENOMEM);
3916 /* find out number of slots supported */
3917 if (of_property_read_u32(dev->of_node, "num-slots",
3918 &pdata->num_slots)) {
3919 dev_info(dev, "num-slots property not found, "
3920 "assuming 1 slot is available\n");
3921 pdata->num_slots = 1;
3924 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3925 dev_info(dev, "fifo-depth property not found, using "
3926 "value of FIFOTH register as default\n");
3928 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3930 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3931 pdata->bus_hz = clock_frequency;
3933 if (drv_data && drv_data->parse_dt) {
3934 ret = drv_data->parse_dt(host);
3936 return ERR_PTR(ret);
3939 if (of_find_property(np, "keep-power-in-suspend", NULL))
3940 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3942 if (of_find_property(np, "enable-sdio-wakeup", NULL))
3943 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3945 if (of_find_property(np, "supports-highspeed", NULL))
3946 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3948 if (of_find_property(np, "supports-UHS_SDR104", NULL))
3949 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3951 if (of_find_property(np, "supports-DDR_MODE", NULL))
3952 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3954 if (of_find_property(np, "caps2-mmc-hs200", NULL))
3955 pdata->caps2 |= MMC_CAP2_HS200;
3957 if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3958 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3960 if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3961 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3963 if (of_get_property(np, "cd-inverted", NULL))
3964 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3966 if (of_get_property(np, "bootpart-no-access", NULL))
3967 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3969 if (of_get_property(np, "controller-power-down", NULL)) {
3971 (u32 *)devm_kzalloc(host->dev,
3972 DW_REGS_SIZE, GFP_KERNEL);
3973 if (!host->regs_buffer) {
3975 "could not allocate memory for regs_buffer\n");
3976 return ERR_PTR(-ENOMEM);
3979 host->rst_ops = &dw_mci_pdrst_ops;
3982 if (of_get_property(np, "assume_removable", NULL))
3983 mmc_assume_removable = 0;
3985 if (!of_property_read_u32(np, "cru_regsbase", &host->cru_regsbase)) {
3986 printk("dw cru_regsbase addr 0x%03x.\n", host->cru_regsbase);
3988 pr_err("dw cru_regsbase addr is missing!\n");
3992 if (!of_property_read_u32(np, "cru_reset_offset", &host->cru_reset_offset)) {
3993 printk("dw cru_reset_offset val %d.\n", host->cru_reset_offset);
3995 pr_err("dw cru_reset_offset val is missing!\n");
4002 #else /* CONFIG_OF */
4003 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
4005 return ERR_PTR(-EINVAL);
4007 #endif /* CONFIG_OF */
4009 int dw_mci_probe(struct dw_mci *host)
4011 const struct dw_mci_drv_data *drv_data = host->drv_data;
4012 int width, i, ret = 0;
4018 host->pdata = dw_mci_parse_dt(host);
4019 if (IS_ERR(host->pdata)) {
4020 dev_err(host->dev, "platform data not available\n");
4025 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4027 "Platform data must supply select_slot function\n");
4032 * In 2.40a spec, Data offset is changed.
4033 * Need to check the version-id and set data-offset for DATA register.
4035 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4036 dev_info(host->dev, "Version ID is %04x\n", host->verid);
4038 if (host->verid < DW_MMC_240A)
4039 host->data_offset = DATA_OFFSET;
4041 host->data_offset = DATA_240A_OFFSET;
4044 host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
4045 if (IS_ERR(host->hpclk_mmc)) {
4046 dev_err(host->dev, "failed to get hpclk_mmc\n");
4048 clk_prepare_enable(host->hpclk_mmc);
4052 host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
4053 if (IS_ERR(host->hclk_mmc)) {
4054 dev_err(host->dev, "failed to get hclk_mmc\n");
4055 ret = PTR_ERR(host->hclk_mmc);
4059 clk_prepare_enable(host->hclk_mmc);
4062 host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
4063 if (IS_ERR(host->clk_mmc)) {
4064 dev_err(host->dev, "failed to get clk mmc_per\n");
4065 ret = PTR_ERR(host->clk_mmc);
4069 host->bus_hz = host->pdata->bus_hz;
4070 if (!host->bus_hz) {
4071 dev_err(host->dev, "Platform data must supply bus speed\n");
4076 if (host->verid < DW_MMC_240A)
4077 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4079 //rockchip: fix divider 2 in clksum before controlller
4080 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4083 dev_err(host->dev, "failed to set clk mmc\n");
4086 clk_prepare_enable(host->clk_mmc);
4088 if (drv_data && drv_data->setup_clock) {
4089 ret = drv_data->setup_clock(host);
4092 "implementation specific clock setup failed\n");
4097 host->quirks = host->pdata->quirks;
4098 host->irq_state = true;
4099 host->set_speed = 0;
4101 host->svi_flags = 0;
4103 spin_lock_init(&host->lock);
4104 spin_lock_init(&host->slock);
4106 INIT_LIST_HEAD(&host->queue);
4108 * Get the host data width - this assumes that HCON has been set with
4109 * the correct values.
4111 i = (mci_readl(host, HCON) >> 7) & 0x7;
4113 host->push_data = dw_mci_push_data16;
4114 host->pull_data = dw_mci_pull_data16;
4116 host->data_shift = 1;
4117 } else if (i == 2) {
4118 host->push_data = dw_mci_push_data64;
4119 host->pull_data = dw_mci_pull_data64;
4121 host->data_shift = 3;
4123 /* Check for a reserved value, and warn if it is */
4125 "HCON reports a reserved host data width!\n"
4126 "Defaulting to 32-bit access.\n");
4127 host->push_data = dw_mci_push_data32;
4128 host->pull_data = dw_mci_pull_data32;
4130 host->data_shift = 2;
4133 /* Reset all blocks */
4134 if (!dw_mci_ctrl_all_reset(host))
4137 init_dma_attrs(&dw_mci_direct_attrs);
4138 dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &dw_mci_direct_attrs);
4140 host->dma_ops = host->pdata->dma_ops;
4141 dw_mci_init_dma(host);
4143 /* Clear the interrupts for the host controller */
4144 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4145 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4147 /* Put in max timeout */
4148 mci_writel(host, TMOUT, 0xFFFFFFFF);
4151 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
4152 * Tx Mark = fifo_size / 2 DMA Size = 8
4154 if (!host->pdata->fifo_depth) {
4156 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4157 * have been overwritten by the bootloader, just like we're
4158 * about to do, so if you know the value for your hardware, you
4159 * should put it in the platform data.
4161 fifo_size = mci_readl(host, FIFOTH);
4162 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4164 fifo_size = host->pdata->fifo_depth;
4166 host->fifo_depth = fifo_size;
4168 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4169 mci_writel(host, FIFOTH, host->fifoth_val);
4171 /* disable clock to CIU */
4172 mci_writel(host, CLKENA, 0);
4173 mci_writel(host, CLKSRC, 0);
4175 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4176 host->card_workqueue = alloc_workqueue("dw-mci-card",
4177 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4178 if (!host->card_workqueue) {
4182 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4183 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4184 host->irq_flags, "dw-mci", host);
4188 if (host->pdata->num_slots)
4189 host->num_slots = host->pdata->num_slots;
4191 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4193 /* We need at least one slot to succeed */
4194 for (i = 0; i < host->num_slots; i++) {
4195 ret = dw_mci_init_slot(host, i);
4197 dev_dbg(host->dev, "slot %d init failed\n", i);
4203 * Enable interrupts for command done, data over, data empty, card det,
4204 * receive ready and error such as transmit, receive timeout, crc error
4206 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4207 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4208 SDMMC_INT_VSI | SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4209 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4210 !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4211 regs |= SDMMC_INT_CD;
4213 mci_writel(host, INTMASK, regs);
4215 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4217 dev_info(host->dev, "DW MMC controller at irq %d, "
4218 "%d bit host data width, "
4220 host->irq, width, fifo_size);
4223 dev_info(host->dev, "%d slots initialized\n", init_slots);
4225 dev_dbg(host->dev, "attempted to initialize %d slots, "
4226 "but failed on all\n", host->num_slots);
4231 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4232 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4237 destroy_workqueue(host->card_workqueue);
4240 if (host->use_dma && host->dma_ops->exit)
4241 host->dma_ops->exit(host);
4244 regulator_disable(host->vmmc);
4245 regulator_put(host->vmmc);
4249 if (!IS_ERR(host->clk_mmc))
4250 clk_disable_unprepare(host->clk_mmc);
4252 if (!IS_ERR(host->hclk_mmc))
4253 clk_disable_unprepare(host->hclk_mmc);
4256 EXPORT_SYMBOL(dw_mci_probe);
4258 void dw_mci_remove(struct dw_mci *host)
4260 struct mmc_host *mmc = host->mmc;
4261 struct dw_mci_slot *slot = mmc_priv(mmc);
4264 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4265 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4267 for(i = 0; i < host->num_slots; i++){
4268 dev_dbg(host->dev, "remove slot %d\n", i);
4270 dw_mci_cleanup_slot(host->slot[i], i);
4273 /* disable clock to CIU */
4274 mci_writel(host, CLKENA, 0);
4275 mci_writel(host, CLKSRC, 0);
4277 destroy_workqueue(host->card_workqueue);
4278 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4279 unregister_pm_notifier(&host->mmc->pm_notify);
4281 if (host->use_dma && host->dma_ops->exit)
4282 host->dma_ops->exit(host);
4284 if (gpio_is_valid(slot->cd_gpio))
4285 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4288 regulator_disable(host->vmmc);
4289 regulator_put(host->vmmc);
4291 if (!IS_ERR(host->clk_mmc))
4292 clk_disable_unprepare(host->clk_mmc);
4294 if (!IS_ERR(host->hclk_mmc))
4295 clk_disable_unprepare(host->hclk_mmc);
4296 if (!IS_ERR(host->hpclk_mmc))
4297 clk_disable_unprepare(host->hpclk_mmc);
4299 EXPORT_SYMBOL(dw_mci_remove);
4303 #ifdef CONFIG_PM_SLEEP
4305 * TODO: we should probably disable the clock to the card in the suspend path.
4307 extern int get_wifi_chip_type(void);
4308 int dw_mci_suspend(struct dw_mci *host)
4310 int present = dw_mci_get_cd(host->mmc);
4312 if((host->mmc->restrict_caps &
4313 RESTRICT_CARD_TYPE_SDIO) &&
4314 (get_wifi_chip_type() == WIFI_ESP8089 ||
4315 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4319 regulator_disable(host->vmmc);
4321 /* Only for sdmmc controller */
4322 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4323 disable_irq(host->irq);
4325 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4326 MMC_DBG_ERR_FUNC(host->mmc,
4327 "Idle pinctrl setting failed! [%s]",
4328 mmc_hostname(host->mmc));
4331 /* Soc rk3126/3036 already in gpio_cd mode */
4332 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4333 dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4334 enable_irq_wake(host->mmc->slot.cd_irq);
4338 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4339 mci_writel(host, INTMASK, 0x00);
4340 mci_writel(host, CTRL, 0x00);
4342 if (host->rst_ops &&
4343 host->rst_ops->pre_suspend)
4344 host->rst_ops->pre_suspend(host);
4348 EXPORT_SYMBOL(dw_mci_suspend);
4350 int dw_mci_resume(struct dw_mci *host)
4354 struct dw_mci_slot *slot;
4355 int present = dw_mci_get_cd(host->mmc);
4357 if (host->rst_ops &&
4358 host->rst_ops->post_resume)
4359 host->rst_ops->post_resume(host);
4362 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4363 (get_wifi_chip_type() == WIFI_ESP8089 ||
4364 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4367 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4368 slot = mmc_priv(host->mmc);
4369 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4373 /*only for sdmmc controller*/
4374 if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4375 /* Soc rk3126/3036 already in gpio_cd mode */
4376 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4377 disable_irq_wake(host->mmc->slot.cd_irq);
4378 mmc_gpio_free_cd(host->mmc);
4382 if (!IS_ERR(host->pins_udbg)) {
4383 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4384 MMC_DBG_ERR_FUNC(host->mmc,
4385 "Idle pinctrl setting failed! [%s]",
4386 mmc_hostname(host->mmc));
4387 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4388 MMC_DBG_ERR_FUNC(host->mmc,
4389 "Udbg pinctrl setting failed! [%s]",
4390 mmc_hostname(host->mmc));
4392 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4393 MMC_DBG_ERR_FUNC(host->mmc,
4394 "Default pinctrl setting failed! [%s]",
4395 mmc_hostname(host->mmc));
4398 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4399 MMC_DBG_ERR_FUNC(host->mmc,
4400 "Default pinctrl setting failed! [%s]",
4401 mmc_hostname(host->mmc));
4405 if (cpu_is_rk3288())
4406 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4407 else if (cpu_is_rk3036())
4408 grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4409 else if (cpu_is_rk312x())
4410 /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4411 grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4414 ret = regulator_enable(host->vmmc);
4417 "failed to enable regulator: %d\n", ret);
4422 if (!dw_mci_ctrl_all_reset(host)){
4427 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
4428 if(host->use_dma && host->dma_ops->init)
4429 host->dma_ops->init(host);
4432 * Restore the initial value at FIFOTH register
4433 * And Invalidate the prev_blksz with zero
4435 mci_writel(host, FIFOTH, host->fifoth_val);
4436 host->prev_blksz = 0;
4437 /* Put in max timeout */
4438 mci_writel(host, TMOUT, 0xFFFFFFFF);
4440 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4441 regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4442 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4444 if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4445 regs |= SDMMC_INT_CD;
4447 mci_writel(host, INTMASK, regs);
4448 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4450 /* Only for sdmmc controller */
4451 if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
4452 enable_irq(host->irq);
4454 for (i = 0; i < host->num_slots; i++){
4455 struct dw_mci_slot *slot = host->slot[i];
4458 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4459 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4460 dw_mci_setup_bus(slot, true);
4466 EXPORT_SYMBOL(dw_mci_resume);
4467 #endif /* CONFIG_PM_SLEEP */
4469 static int __init dw_mci_init(void)
4471 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4472 pr_info("MHSC version = %s\n", RK_SDMMC_DRIVER_VERSION);
4476 static void __exit dw_mci_exit(void)
4480 module_init(dw_mci_init);
4481 module_exit(dw_mci_exit);
4483 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4484 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4485 MODULE_LICENSE("GPL v2");