drivers/mmc/host/rtsx_pci_sdmmc.c

   1 /* Realtek PCI-Express SD/MMC Card Interface driver
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/slab.h>
  24 #include <linux/highmem.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/sd.h>
  31 #include <linux/mmc/card.h>
  32 #include <linux/mfd/rtsx_pci.h>
  33 #include <asm/unaligned.h>
  34
  35 struct realtek_pci_sdmmc {
  36         struct platform_device  *pdev;
  37         struct rtsx_pcr         *pcr;
  38         struct mmc_host         *mmc;
  39         struct mmc_request      *mrq;
  40         struct workqueue_struct *workq;
  41 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  42
  43         struct work_struct      work;
  44         struct mutex            host_mutex;
  45
  46         u8                      ssc_depth;
  47         unsigned int            clock;
  48         bool                    vpclk;
  49         bool                    double_clk;
  50         bool                    eject;
  51         bool                    initial_mode;
  52         int                     power_state;
  53 #define SDMMC_POWER_ON          1
  54 #define SDMMC_POWER_OFF         0
  55
  56         unsigned int            sg_count;
  57         s32                     cookie;
  58         unsigned int            cookie_sg_count;
  59         bool                    using_cookie;
  60 };
  61
  62 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  63 {
  64         return &(host->pdev->dev);
  65 }
  66
  67 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  68 {
  69         rtsx_pci_write_register(host->pcr, CARD_STOP,
  70                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  71 }
  72
  73 #ifdef DEBUG
  74 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  75 {
  76         struct rtsx_pcr *pcr = host->pcr;
  77         u16 i;
  78         u8 *ptr;
  79
  80         /* Print SD host internal registers */
  81         rtsx_pci_init_cmd(pcr);
  82         for (i = 0xFDA0; i <= 0xFDAE; i++)
  83                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
  84         for (i = 0xFD52; i <= 0xFD69; i++)
  85                 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
  86         rtsx_pci_send_cmd(pcr, 100);
  87
  88         ptr = rtsx_pci_get_cmd_data(pcr);
  89         for (i = 0xFDA0; i <= 0xFDAE; i++)
  90                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
  91         for (i = 0xFD52; i <= 0xFD69; i++)
  92                 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
  93 }
  94 #else
  95 #define sd_print_debug_regs(host)
  96 #endif /* DEBUG */
  97
  98 /*
  99  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 100  *
 101  * @pre: if called in pre_req()
 102  * return:
 103  *      0 - do dma_map_sg()
 104  *      1 - using cookie
 105  */
 106 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 107                 struct mmc_data *data, bool pre)
 108 {
 109         struct rtsx_pcr *pcr = host->pcr;
 110         int read = data->flags & MMC_DATA_READ;
 111         int count = 0;
 112         int using_cookie = 0;
 113
 114         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 115                 dev_err(sdmmc_dev(host),
 116                         "error: data->host_cookie = %d, host->cookie = %d\n",
 117                         data->host_cookie, host->cookie);
 118                 data->host_cookie = 0;
 119         }
 120
 121         if (pre || data->host_cookie != host->cookie) {
 122                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 123         } else {
 124                 count = host->cookie_sg_count;
 125                 using_cookie = 1;
 126         }
 127
 128         if (pre) {
 129                 host->cookie_sg_count = count;
 130                 if (++host->cookie < 0)
 131                         host->cookie = 1;
 132                 data->host_cookie = host->cookie;
 133         } else {
 134                 host->sg_count = count;
 135         }
 136
 137         return using_cookie;
 138 }
 139
 140 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
 141                 bool is_first_req)
 142 {
 143         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 144         struct mmc_data *data = mrq->data;
 145
 146         if (data->host_cookie) {
 147                 dev_err(sdmmc_dev(host),
 148                         "error: reset data->host_cookie = %d\n",
 149                         data->host_cookie);
 150                 data->host_cookie = 0;
 151         }
 152
 153         sd_pre_dma_transfer(host, data, true);
 154         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 155 }
 156
 157 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 158                 int err)
 159 {
 160         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 161         struct rtsx_pcr *pcr = host->pcr;
 162         struct mmc_data *data = mrq->data;
 163         int read = data->flags & MMC_DATA_READ;
 164
 165         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 166         data->host_cookie = 0;
 167 }
 168
 169 static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
 170                 u8 *buf, int buf_len, int timeout)
 171 {
 172         struct rtsx_pcr *pcr = host->pcr;
 173         int err, i;
 174         u8 trans_mode;
 175
 176         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
 177
 178         if (!buf)
 179                 buf_len = 0;
 180
 181         if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
 182                 trans_mode = SD_TM_AUTO_TUNING;
 183         else
 184                 trans_mode = SD_TM_NORMAL_READ;
 185
 186         rtsx_pci_init_cmd(pcr);
 187
 188         for (i = 0; i < 5; i++)
 189                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
 190
 191         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 192         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
 193                         0xFF, (u8)(byte_cnt >> 8));
 194         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
 195         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
 196
 197         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 198                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 199                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 200         if (trans_mode != SD_TM_AUTO_TUNING)
 201                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 202                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 203
 204         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 205                         0xFF, trans_mode | SD_TRANSFER_START);
 206         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 207                         SD_TRANSFER_END, SD_TRANSFER_END);
 208
 209         err = rtsx_pci_send_cmd(pcr, timeout);
 210         if (err < 0) {
 211                 sd_print_debug_regs(host);
 212                 dev_dbg(sdmmc_dev(host),
 213                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 214                 return err;
 215         }
 216
 217         if (buf && buf_len) {
 218                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 219                 if (err < 0) {
 220                         dev_dbg(sdmmc_dev(host),
 221                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 222                         return err;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228
 229 static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
 230                 u8 *buf, int buf_len, int timeout)
 231 {
 232         struct rtsx_pcr *pcr = host->pcr;
 233         int err, i;
 234         u8 trans_mode;
 235
 236         if (!buf)
 237                 buf_len = 0;
 238
 239         if (buf && buf_len) {
 240                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 241                 if (err < 0) {
 242                         dev_dbg(sdmmc_dev(host),
 243                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 244                         return err;
 245                 }
 246         }
 247
 248         trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
 249         rtsx_pci_init_cmd(pcr);
 250
 251         if (cmd) {
 252                 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
 253                                 cmd[0] - 0x40);
 254
 255                 for (i = 0; i < 5; i++)
 256                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 257                                         SD_CMD0 + i, 0xFF, cmd[i]);
 258         }
 259
 260         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 261         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
 262                         0xFF, (u8)(byte_cnt >> 8));
 263         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
 264         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
 265
 266         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 267                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 268                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 269
 270         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 271                         trans_mode | SD_TRANSFER_START);
 272         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 273                         SD_TRANSFER_END, SD_TRANSFER_END);
 274
 275         err = rtsx_pci_send_cmd(pcr, timeout);
 276         if (err < 0) {
 277                 sd_print_debug_regs(host);
 278                 dev_dbg(sdmmc_dev(host),
 279                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 280                 return err;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 287                 struct mmc_command *cmd)
 288 {
 289         struct rtsx_pcr *pcr = host->pcr;
 290         u8 cmd_idx = (u8)cmd->opcode;
 291         u32 arg = cmd->arg;
 292         int err = 0;
 293         int timeout = 100;
 294         int i;
 295         u8 *ptr;
 296         int stat_idx = 0;
 297         u8 rsp_type;
 298         int rsp_len = 5;
 299         bool clock_toggled = false;
 300
 301         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 302                         __func__, cmd_idx, arg);
 303
 304         /* Response type:
 305          * R0
 306          * R1, R5, R6, R7
 307          * R1b
 308          * R2
 309          * R3, R4
 310          */
 311         switch (mmc_resp_type(cmd)) {
 312         case MMC_RSP_NONE:
 313                 rsp_type = SD_RSP_TYPE_R0;
 314                 rsp_len = 0;
 315                 break;
 316         case MMC_RSP_R1:
 317                 rsp_type = SD_RSP_TYPE_R1;
 318                 break;
 319         case MMC_RSP_R1 & ~MMC_RSP_CRC:
 320                 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 321                 break;
 322         case MMC_RSP_R1B:
 323                 rsp_type = SD_RSP_TYPE_R1b;
 324                 break;
 325         case MMC_RSP_R2:
 326                 rsp_type = SD_RSP_TYPE_R2;
 327                 rsp_len = 16;
 328                 break;
 329         case MMC_RSP_R3:
 330                 rsp_type = SD_RSP_TYPE_R3;
 331                 break;
 332         default:
 333                 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
 334                 err = -EINVAL;
 335                 goto out;
 336         }
 337
 338         if (rsp_type == SD_RSP_TYPE_R1b)
 339                 timeout = 3000;
 340
 341         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 342                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 343                                 0xFF, SD_CLK_TOGGLE_EN);
 344                 if (err < 0)
 345                         goto out;
 346
 347                 clock_toggled = true;
 348         }
 349
 350         rtsx_pci_init_cmd(pcr);
 351
 352         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
 353         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
 354         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
 355         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
 356         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
 357
 358         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 359         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 360                         0x01, PINGPONG_BUFFER);
 361         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 362                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 363         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 364                      SD_TRANSFER_END | SD_STAT_IDLE,
 365                      SD_TRANSFER_END | SD_STAT_IDLE);
 366
 367         if (rsp_type == SD_RSP_TYPE_R2) {
 368                 /* Read data from ping-pong buffer */
 369                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 370                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 371                 stat_idx = 16;
 372         } else if (rsp_type != SD_RSP_TYPE_R0) {
 373                 /* Read data from SD_CMDx registers */
 374                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 375                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 376                 stat_idx = 5;
 377         }
 378
 379         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 380
 381         err = rtsx_pci_send_cmd(pcr, timeout);
 382         if (err < 0) {
 383                 sd_print_debug_regs(host);
 384                 sd_clear_error(host);
 385                 dev_dbg(sdmmc_dev(host),
 386                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 387                 goto out;
 388         }
 389
 390         if (rsp_type == SD_RSP_TYPE_R0) {
 391                 err = 0;
 392                 goto out;
 393         }
 394
 395         /* Eliminate returned value of CHECK_REG_CMD */
 396         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 397
 398         /* Check (Start,Transmission) bit of Response */
 399         if ((ptr[0] & 0xC0) != 0) {
 400                 err = -EILSEQ;
 401                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 402                 goto out;
 403         }
 404
 405         /* Check CRC7 */
 406         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 407                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 408                         err = -EILSEQ;
 409                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 410                         goto out;
 411                 }
 412         }
 413
 414         if (rsp_type == SD_RSP_TYPE_R2) {
 415                 for (i = 0; i < 4; i++) {
 416                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 417                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 418                                         i, cmd->resp[i]);
 419                 }
 420         } else {
 421                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 422                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 423                                 cmd->resp[0]);
 424         }
 425
 426 out:
 427         cmd->error = err;
 428
 429         if (err && clock_toggled)
 430                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 431                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 432 }
 433
 434 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 435 {
 436         struct rtsx_pcr *pcr = host->pcr;
 437         struct mmc_host *mmc = host->mmc;
 438         struct mmc_card *card = mmc->card;
 439         struct mmc_data *data = mrq->data;
 440         int uhs = mmc_card_uhs(card);
 441         int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
 442         u8 cfg2, trans_mode;
 443         int err;
 444         size_t data_len = data->blksz * data->blocks;
 445
 446         if (read) {
 447                 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 448                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
 449                 trans_mode = SD_TM_AUTO_READ_3;
 450         } else {
 451                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 452                         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 453                 trans_mode = SD_TM_AUTO_WRITE_3;
 454         }
 455
 456         if (!uhs)
 457                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 458
 459         rtsx_pci_init_cmd(pcr);
 460
 461         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
 462         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
 463         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
 464                         0xFF, (u8)data->blocks);
 465         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
 466                         0xFF, (u8)(data->blocks >> 8));
 467
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 469                         DMA_DONE_INT, DMA_DONE_INT);
 470         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 471                         0xFF, (u8)(data_len >> 24));
 472         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 473                         0xFF, (u8)(data_len >> 16));
 474         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 475                         0xFF, (u8)(data_len >> 8));
 476         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 477         if (read) {
 478                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 479                                 0x03 | DMA_PACK_SIZE_MASK,
 480                                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 481         } else {
 482                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 483                                 0x03 | DMA_PACK_SIZE_MASK,
 484                                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 485         }
 486
 487         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 488                         0x01, RING_BUFFER);
 489
 490         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 491         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 492                         trans_mode | SD_TRANSFER_START);
 493         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 494                         SD_TRANSFER_END, SD_TRANSFER_END);
 495
 496         rtsx_pci_send_cmd_no_wait(pcr);
 497
 498         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000);
 499         if (err < 0) {
 500                 sd_clear_error(host);
 501                 return err;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 508 {
 509         rtsx_pci_write_register(host->pcr, SD_CFG1,
 510                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 511 }
 512
 513 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 514 {
 515         rtsx_pci_write_register(host->pcr, SD_CFG1,
 516                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 517 }
 518
 519 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 520                 struct mmc_request *mrq)
 521 {
 522         struct mmc_command *cmd = mrq->cmd;
 523         struct mmc_data *data = mrq->data;
 524         u8 _cmd[5], *buf;
 525
 526         _cmd[0] = 0x40 | (u8)cmd->opcode;
 527         put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
 528
 529         buf = kzalloc(data->blksz, GFP_NOIO);
 530         if (!buf) {
 531                 cmd->error = -ENOMEM;
 532                 return;
 533         }
 534
 535         if (data->flags & MMC_DATA_READ) {
 536                 if (host->initial_mode)
 537                         sd_disable_initial_mode(host);
 538
 539                 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
 540                                 data->blksz, 200);
 541
 542                 if (host->initial_mode)
 543                         sd_enable_initial_mode(host);
 544
 545                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 546         } else {
 547                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 548
 549                 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
 550                                 data->blksz, 200);
 551         }
 552
 553         kfree(buf);
 554 }
 555
 556 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 557                 u8 sample_point, bool rx)
 558 {
 559         struct rtsx_pcr *pcr = host->pcr;
 560         int err;
 561
 562         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 563                         __func__, rx ? "RX" : "TX", sample_point);
 564
 565         rtsx_pci_init_cmd(pcr);
 566
 567         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 568         if (rx)
 569                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 570                                 SD_VPRX_CTL, 0x1F, sample_point);
 571         else
 572                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 573                                 SD_VPTX_CTL, 0x1F, sample_point);
 574         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 575         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 576                         PHASE_NOT_RESET, PHASE_NOT_RESET);
 577         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
 578         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 579
 580         err = rtsx_pci_send_cmd(pcr, 100);
 581         if (err < 0)
 582                 return err;
 583
 584         return 0;
 585 }
 586
 587 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 588 {
 589         bit %= RTSX_PHASE_MAX;
 590         return phase_map & (1 << bit);
 591 }
 592
 593 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 594 {
 595         int i;
 596
 597         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 598                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 599                         return i;
 600         }
 601         return RTSX_PHASE_MAX;
 602 }
 603
 604 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 605 {
 606         int start = 0, len = 0;
 607         int start_final = 0, len_final = 0;
 608         u8 final_phase = 0xFF;
 609
 610         if (phase_map == 0) {
 611                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 612                 return final_phase;
 613         }
 614
 615         while (start < RTSX_PHASE_MAX) {
 616                 len = sd_get_phase_len(phase_map, start);
 617                 if (len_final < len) {
 618                         start_final = start;
 619                         len_final = len;
 620                 }
 621                 start += len ? len : 1;
 622         }
 623
 624         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 625         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 626                 phase_map, len_final, final_phase);
 627
 628         return final_phase;
 629 }
 630
 631 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 632 {
 633         int err, i;
 634         u8 val = 0;
 635
 636         for (i = 0; i < 100; i++) {
 637                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 638                 if (val & SD_DATA_IDLE)
 639                         return;
 640
 641                 udelay(100);
 642         }
 643 }
 644
 645 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 646                 u8 opcode, u8 sample_point)
 647 {
 648         int err;
 649         u8 cmd[5] = {0};
 650
 651         err = sd_change_phase(host, sample_point, true);
 652         if (err < 0)
 653                 return err;
 654
 655         cmd[0] = 0x40 | opcode;
 656         err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
 657         if (err < 0) {
 658                 /* Wait till SD DATA IDLE */
 659                 sd_wait_data_idle(host);
 660                 sd_clear_error(host);
 661                 return err;
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 668                 u8 opcode, u32 *phase_map)
 669 {
 670         int err, i;
 671         u32 raw_phase_map = 0;
 672
 673         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 674                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 675                 if (err == 0)
 676                         raw_phase_map |= 1 << i;
 677         }
 678
 679         if (phase_map)
 680                 *phase_map = raw_phase_map;
 681
 682         return 0;
 683 }
 684
 685 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 686 {
 687         int err, i;
 688         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 689         u8 final_phase;
 690
 691         for (i = 0; i < RX_TUNING_CNT; i++) {
 692                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 693                 if (err < 0)
 694                         return err;
 695
 696                 if (raw_phase_map[i] == 0)
 697                         break;
 698         }
 699
 700         phase_map = 0xFFFFFFFF;
 701         for (i = 0; i < RX_TUNING_CNT; i++) {
 702                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 703                                 i, raw_phase_map[i]);
 704                 phase_map &= raw_phase_map[i];
 705         }
 706         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 707
 708         if (phase_map) {
 709                 final_phase = sd_search_final_phase(host, phase_map);
 710                 if (final_phase == 0xFF)
 711                         return -EINVAL;
 712
 713                 err = sd_change_phase(host, final_phase, true);
 714                 if (err < 0)
 715                         return err;
 716         } else {
 717                 return -EINVAL;
 718         }
 719
 720         return 0;
 721 }
 722
 723 static inline int sd_rw_cmd(struct mmc_command *cmd)
 724 {
 725         return mmc_op_multi(cmd->opcode) ||
 726                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 727                 (cmd->opcode == MMC_WRITE_BLOCK);
 728 }
 729
 730 static void sd_request(struct work_struct *work)
 731 {
 732         struct realtek_pci_sdmmc *host = container_of(work,
 733                         struct realtek_pci_sdmmc, work);
 734         struct rtsx_pcr *pcr = host->pcr;
 735
 736         struct mmc_host *mmc = host->mmc;
 737         struct mmc_request *mrq = host->mrq;
 738         struct mmc_command *cmd = mrq->cmd;
 739         struct mmc_data *data = mrq->data;
 740
 741         unsigned int data_size = 0;
 742         int err;
 743
 744         if (host->eject) {
 745                 cmd->error = -ENOMEDIUM;
 746                 goto finish;
 747         }
 748
 749         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 750         if (err) {
 751                 cmd->error = err;
 752                 goto finish;
 753         }
 754
 755         mutex_lock(&pcr->pcr_mutex);
 756
 757         rtsx_pci_start_run(pcr);
 758
 759         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 760                         host->initial_mode, host->double_clk, host->vpclk);
 761         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 762         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 763                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 764
 765         mutex_lock(&host->host_mutex);
 766         host->mrq = mrq;
 767         mutex_unlock(&host->host_mutex);
 768
 769         if (mrq->data)
 770                 data_size = data->blocks * data->blksz;
 771
 772         if (!data_size || sd_rw_cmd(cmd)) {
 773                 sd_send_cmd_get_rsp(host, cmd);
 774
 775                 if (!cmd->error && data_size) {
 776                         sd_rw_multi(host, mrq);
 777                         if (!host->using_cookie)
 778                                 sdmmc_post_req(host->mmc, host->mrq, 0);
 779
 780                         if (mmc_op_multi(cmd->opcode) && mrq->stop)
 781                                 sd_send_cmd_get_rsp(host, mrq->stop);
 782                 }
 783         } else {
 784                 sd_normal_rw(host, mrq);
 785         }
 786
 787         if (mrq->data) {
 788                 if (cmd->error || data->error)
 789                         data->bytes_xfered = 0;
 790                 else
 791                         data->bytes_xfered = data->blocks * data->blksz;
 792         }
 793
 794         mutex_unlock(&pcr->pcr_mutex);
 795
 796 finish:
 797         if (cmd->error)
 798                 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
 799
 800         mutex_lock(&host->host_mutex);
 801         host->mrq = NULL;
 802         mutex_unlock(&host->host_mutex);
 803
 804         mmc_request_done(mmc, mrq);
 805 }
 806
 807 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 808 {
 809         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 810         struct mmc_data *data = mrq->data;
 811
 812         mutex_lock(&host->host_mutex);
 813         host->mrq = mrq;
 814         mutex_unlock(&host->host_mutex);
 815
 816         if (sd_rw_cmd(mrq->cmd))
 817                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 818
 819         queue_work(host->workq, &host->work);
 820 }
 821
 822 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 823                 unsigned char bus_width)
 824 {
 825         int err = 0;
 826         u8 width[] = {
 827                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 828                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 829                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 830         };
 831
 832         if (bus_width <= MMC_BUS_WIDTH_8)
 833                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 834                                 0x03, width[bus_width]);
 835
 836         return err;
 837 }
 838
 839 static int sd_power_on(struct realtek_pci_sdmmc *host)
 840 {
 841         struct rtsx_pcr *pcr = host->pcr;
 842         int err;
 843
 844         if (host->power_state == SDMMC_POWER_ON)
 845                 return 0;
 846
 847         rtsx_pci_init_cmd(pcr);
 848         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 849         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 850                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 851         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 852                         SD_CLK_EN, SD_CLK_EN);
 853         err = rtsx_pci_send_cmd(pcr, 100);
 854         if (err < 0)
 855                 return err;
 856
 857         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 858         if (err < 0)
 859                 return err;
 860
 861         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 862         if (err < 0)
 863                 return err;
 864
 865         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 866         if (err < 0)
 867                 return err;
 868
 869         host->power_state = SDMMC_POWER_ON;
 870         return 0;
 871 }
 872
 873 static int sd_power_off(struct realtek_pci_sdmmc *host)
 874 {
 875         struct rtsx_pcr *pcr = host->pcr;
 876         int err;
 877
 878         host->power_state = SDMMC_POWER_OFF;
 879
 880         rtsx_pci_init_cmd(pcr);
 881
 882         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 883         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 884
 885         err = rtsx_pci_send_cmd(pcr, 100);
 886         if (err < 0)
 887                 return err;
 888
 889         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 890         if (err < 0)
 891                 return err;
 892
 893         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 894 }
 895
 896 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 897                 unsigned char power_mode)
 898 {
 899         int err;
 900
 901         if (power_mode == MMC_POWER_OFF)
 902                 err = sd_power_off(host);
 903         else
 904                 err = sd_power_on(host);
 905
 906         return err;
 907 }
 908
 909 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 910 {
 911         struct rtsx_pcr *pcr = host->pcr;
 912         int err = 0;
 913
 914         rtsx_pci_init_cmd(pcr);
 915
 916         switch (timing) {
 917         case MMC_TIMING_UHS_SDR104:
 918         case MMC_TIMING_UHS_SDR50:
 919                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 920                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 921                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 922                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 923                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 924                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 925                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 926                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 927                 break;
 928
 929         case MMC_TIMING_MMC_DDR52:
 930         case MMC_TIMING_UHS_DDR50:
 931                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 932                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 933                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 934                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 935                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 936                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 937                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 938                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 939                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 940                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
 941                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 942                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 943                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 944                 break;
 945
 946         case MMC_TIMING_MMC_HS:
 947         case MMC_TIMING_SD_HS:
 948                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 949                                 0x0C, SD_20_MODE);
 950                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 951                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 952                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 953                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 954                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 955                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 956                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
 957                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 958                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
 959                 break;
 960
 961         default:
 962                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 963                                 SD_CFG1, 0x0C, SD_20_MODE);
 964                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 965                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 966                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 967                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 968                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 969                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 970                                 SD_PUSH_POINT_CTL, 0xFF, 0);
 971                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 972                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
 973                 break;
 974         }
 975
 976         err = rtsx_pci_send_cmd(pcr, 100);
 977
 978         return err;
 979 }
 980
 981 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 982 {
 983         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 984         struct rtsx_pcr *pcr = host->pcr;
 985
 986         if (host->eject)
 987                 return;
 988
 989         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
 990                 return;
 991
 992         mutex_lock(&pcr->pcr_mutex);
 993
 994         rtsx_pci_start_run(pcr);
 995
 996         sd_set_bus_width(host, ios->bus_width);
 997         sd_set_power_mode(host, ios->power_mode);
 998         sd_set_timing(host, ios->timing);
 999
1000         host->vpclk = false;
1001         host->double_clk = true;
1002
1003         switch (ios->timing) {
1004         case MMC_TIMING_UHS_SDR104:
1005         case MMC_TIMING_UHS_SDR50:
1006                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1007                 host->vpclk = true;
1008                 host->double_clk = false;
1009                 break;
1010         case MMC_TIMING_MMC_DDR52:
1011         case MMC_TIMING_UHS_DDR50:
1012         case MMC_TIMING_UHS_SDR25:
1013                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1014                 break;
1015         default:
1016                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1017                 break;
1018         }
1019
1020         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1021
1022         host->clock = ios->clock;
1023         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1024                         host->initial_mode, host->double_clk, host->vpclk);
1025
1026         mutex_unlock(&pcr->pcr_mutex);
1027 }
1028
1029 static int sdmmc_get_ro(struct mmc_host *mmc)
1030 {
1031         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1032         struct rtsx_pcr *pcr = host->pcr;
1033         int ro = 0;
1034         u32 val;
1035
1036         if (host->eject)
1037                 return -ENOMEDIUM;
1038
1039         mutex_lock(&pcr->pcr_mutex);
1040
1041         rtsx_pci_start_run(pcr);
1042
1043         /* Check SD mechanical write-protect switch */
1044         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1045         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1046         if (val & SD_WRITE_PROTECT)
1047                 ro = 1;
1048
1049         mutex_unlock(&pcr->pcr_mutex);
1050
1051         return ro;
1052 }
1053
1054 static int sdmmc_get_cd(struct mmc_host *mmc)
1055 {
1056         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1057         struct rtsx_pcr *pcr = host->pcr;
1058         int cd = 0;
1059         u32 val;
1060
1061         if (host->eject)
1062                 return -ENOMEDIUM;
1063
1064         mutex_lock(&pcr->pcr_mutex);
1065
1066         rtsx_pci_start_run(pcr);
1067
1068         /* Check SD card detect */
1069         val = rtsx_pci_card_exist(pcr);
1070         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1071         if (val & SD_EXIST)
1072                 cd = 1;
1073
1074         mutex_unlock(&pcr->pcr_mutex);
1075
1076         return cd;
1077 }
1078
1079 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1080 {
1081         struct rtsx_pcr *pcr = host->pcr;
1082         int err;
1083         u8 stat;
1084
1085         /* Reference to Signal Voltage Switch Sequence in SD spec.
1086          * Wait for a period of time so that the card can drive SD_CMD and
1087          * SD_DAT[3:0] to low after sending back CMD11 response.
1088          */
1089         mdelay(1);
1090
1091         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1092          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1093          * abort the voltage switch sequence;
1094          */
1095         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1096         if (err < 0)
1097                 return err;
1098
1099         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1100                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1101                 return -EINVAL;
1102
1103         /* Stop toggle SD clock */
1104         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1105                         0xFF, SD_CLK_FORCE_STOP);
1106         if (err < 0)
1107                 return err;
1108
1109         return 0;
1110 }
1111
1112 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1113 {
1114         struct rtsx_pcr *pcr = host->pcr;
1115         int err;
1116         u8 stat, mask, val;
1117
1118         /* Wait 1.8V output of voltage regulator in card stable */
1119         msleep(50);
1120
1121         /* Toggle SD clock again */
1122         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1123         if (err < 0)
1124                 return err;
1125
1126         /* Wait for a period of time so that the card can drive
1127          * SD_DAT[3:0] to high at 1.8V
1128          */
1129         msleep(20);
1130
1131         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1132         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1133         if (err < 0)
1134                 return err;
1135
1136         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1137                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1138         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1139                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1140         if ((stat & mask) != val) {
1141                 dev_dbg(sdmmc_dev(host),
1142                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1143                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1144                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1145                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1146                 return -EINVAL;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1153 {
1154         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1155         struct rtsx_pcr *pcr = host->pcr;
1156         int err = 0;
1157         u8 voltage;
1158
1159         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1160                         __func__, ios->signal_voltage);
1161
1162         if (host->eject)
1163                 return -ENOMEDIUM;
1164
1165         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1166         if (err)
1167                 return err;
1168
1169         mutex_lock(&pcr->pcr_mutex);
1170
1171         rtsx_pci_start_run(pcr);
1172
1173         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1174                 voltage = OUTPUT_3V3;
1175         else
1176                 voltage = OUTPUT_1V8;
1177
1178         if (voltage == OUTPUT_1V8) {
1179                 err = sd_wait_voltage_stable_1(host);
1180                 if (err < 0)
1181                         goto out;
1182         }
1183
1184         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1185         if (err < 0)
1186                 goto out;
1187
1188         if (voltage == OUTPUT_1V8) {
1189                 err = sd_wait_voltage_stable_2(host);
1190                 if (err < 0)
1191                         goto out;
1192         }
1193
1194 out:
1195         /* Stop toggle SD clock in idle */
1196         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1197                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1198
1199         mutex_unlock(&pcr->pcr_mutex);
1200
1201         return err;
1202 }
1203
1204 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1205 {
1206         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1207         struct rtsx_pcr *pcr = host->pcr;
1208         int err = 0;
1209
1210         if (host->eject)
1211                 return -ENOMEDIUM;
1212
1213         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1214         if (err)
1215                 return err;
1216
1217         mutex_lock(&pcr->pcr_mutex);
1218
1219         rtsx_pci_start_run(pcr);
1220
1221         /* Set initial TX phase */
1222         switch (mmc->ios.timing) {
1223         case MMC_TIMING_UHS_SDR104:
1224                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1225                 break;
1226
1227         case MMC_TIMING_UHS_SDR50:
1228                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1229                 break;
1230
1231         case MMC_TIMING_UHS_DDR50:
1232                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1233                 break;
1234
1235         default:
1236                 err = 0;
1237         }
1238
1239         if (err)
1240                 goto out;
1241
1242         /* Tuning RX phase */
1243         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1244                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1245                 err = sd_tuning_rx(host, opcode);
1246         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1247                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1248
1249 out:
1250         mutex_unlock(&pcr->pcr_mutex);
1251
1252         return err;
1253 }
1254
1255 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1256         .pre_req = sdmmc_pre_req,
1257         .post_req = sdmmc_post_req,
1258         .request = sdmmc_request,
1259         .set_ios = sdmmc_set_ios,
1260         .get_ro = sdmmc_get_ro,
1261         .get_cd = sdmmc_get_cd,
1262         .start_signal_voltage_switch = sdmmc_switch_voltage,
1263         .execute_tuning = sdmmc_execute_tuning,
1264 };
1265
1266 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1267 {
1268         struct mmc_host *mmc = host->mmc;
1269         struct rtsx_pcr *pcr = host->pcr;
1270
1271         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1272
1273         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1274                 mmc->caps |= MMC_CAP_UHS_SDR50;
1275         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1276                 mmc->caps |= MMC_CAP_UHS_SDR104;
1277         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1278                 mmc->caps |= MMC_CAP_UHS_DDR50;
1279         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1280                 mmc->caps |= MMC_CAP_1_8V_DDR;
1281         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1282                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1283 }
1284
1285 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1286 {
1287         struct mmc_host *mmc = host->mmc;
1288
1289         mmc->f_min = 250000;
1290         mmc->f_max = 208000000;
1291         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1292         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1293                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1294                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1295         mmc->max_current_330 = 400;
1296         mmc->max_current_180 = 800;
1297         mmc->ops = &realtek_pci_sdmmc_ops;
1298
1299         init_extra_caps(host);
1300
1301         mmc->max_segs = 256;
1302         mmc->max_seg_size = 65536;
1303         mmc->max_blk_size = 512;
1304         mmc->max_blk_count = 65535;
1305         mmc->max_req_size = 524288;
1306 }
1307
1308 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1309 {
1310         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1311
1312         mmc_detect_change(host->mmc, 0);
1313 }
1314
1315 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1316 {
1317         struct mmc_host *mmc;
1318         struct realtek_pci_sdmmc *host;
1319         struct rtsx_pcr *pcr;
1320         struct pcr_handle *handle = pdev->dev.platform_data;
1321
1322         if (!handle)
1323                 return -ENXIO;
1324
1325         pcr = handle->pcr;
1326         if (!pcr)
1327                 return -ENXIO;
1328
1329         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1330
1331         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1332         if (!mmc)
1333                 return -ENOMEM;
1334
1335         host = mmc_priv(mmc);
1336         host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME);
1337         if (!host->workq) {
1338                 mmc_free_host(mmc);
1339                 return -ENOMEM;
1340         }
1341         host->pcr = pcr;
1342         host->mmc = mmc;
1343         host->pdev = pdev;
1344         host->power_state = SDMMC_POWER_OFF;
1345         INIT_WORK(&host->work, sd_request);
1346         platform_set_drvdata(pdev, host);
1347         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1348         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1349
1350         mutex_init(&host->host_mutex);
1351
1352         realtek_init_host(host);
1353
1354         mmc_add_host(mmc);
1355
1356         return 0;
1357 }
1358
1359 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1360 {
1361         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1362         struct rtsx_pcr *pcr;
1363         struct mmc_host *mmc;
1364
1365         if (!host)
1366                 return 0;
1367
1368         pcr = host->pcr;
1369         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1370         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1371         mmc = host->mmc;
1372
1373         cancel_work_sync(&host->work);
1374
1375         mutex_lock(&host->host_mutex);
1376         if (host->mrq) {
1377                 dev_dbg(&(pdev->dev),
1378                         "%s: Controller removed during transfer\n",
1379                         mmc_hostname(mmc));
1380
1381                 rtsx_pci_complete_unfinished_transfer(pcr);
1382
1383                 host->mrq->cmd->error = -ENOMEDIUM;
1384                 if (host->mrq->stop)
1385                         host->mrq->stop->error = -ENOMEDIUM;
1386                 mmc_request_done(mmc, host->mrq);
1387         }
1388         mutex_unlock(&host->host_mutex);
1389
1390         mmc_remove_host(mmc);
1391         host->eject = true;
1392
1393         flush_workqueue(host->workq);
1394         destroy_workqueue(host->workq);
1395         host->workq = NULL;
1396
1397         mmc_free_host(mmc);
1398
1399         dev_dbg(&(pdev->dev),
1400                 ": Realtek PCI-E SDMMC controller has been removed\n");
1401
1402         return 0;
1403 }
1404
1405 static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1406         {
1407                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1408         }, {
1409                 /* sentinel */
1410         }
1411 };
1412 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1413
1414 static struct platform_driver rtsx_pci_sdmmc_driver = {
1415         .probe          = rtsx_pci_sdmmc_drv_probe,
1416         .remove         = rtsx_pci_sdmmc_drv_remove,
1417         .id_table       = rtsx_pci_sdmmc_ids,
1418         .driver         = {
1419                 .owner  = THIS_MODULE,
1420                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1421         },
1422 };
1423 module_platform_driver(rtsx_pci_sdmmc_driver);
1424
1425 MODULE_LICENSE("GPL");
1426 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1427 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");