2 * Copyright (C) 2013 BayHub Technology Ltd.
4 * Authors: Peter Guo <peter.guo@bayhubtech.com>
5 * Adam Lee <adam.lee@canonical.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/pci.h>
21 #include "sdhci-pci.h"
22 #include "sdhci-pci-o2micro.h"
24 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
27 pci_read_config_dword(chip->pdev,
28 O2_SD_PLL_SETTING, &scratch_32);
30 scratch_32 &= 0x0000FFFF;
33 pci_write_config_dword(chip->pdev,
34 O2_SD_PLL_SETTING, scratch_32);
37 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
42 /* Set led of SD host function enable */
43 ret = pci_read_config_dword(chip->pdev,
44 O2_SD_FUNC_REG0, &scratch_32);
48 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
49 pci_write_config_dword(chip->pdev,
50 O2_SD_FUNC_REG0, scratch_32);
52 ret = pci_read_config_dword(chip->pdev,
53 O2_SD_TEST_REG, &scratch_32);
57 scratch_32 |= O2_SD_LED_ENABLE;
58 pci_write_config_dword(chip->pdev,
59 O2_SD_TEST_REG, scratch_32);
63 void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
67 /* Improve write performance for SD3.0 */
68 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
71 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
72 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
74 /* Enable Link abnormal reset generating Reset */
75 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
78 scratch_32 &= ~((1 << 19) | (1 << 11));
79 scratch_32 |= (1 << 10);
80 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
82 /* set card power over current protection */
83 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
86 scratch_32 |= (1 << 4);
87 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
89 /* adjust the output delay for SD mode */
90 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
92 /* Set the output voltage setting of Aux 1.2v LDO */
93 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
96 scratch_32 &= ~(3 << 12);
97 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
99 /* Set Max power supply capability of SD host */
100 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
103 scratch_32 &= ~(0x01FE);
104 scratch_32 |= 0x00CC;
105 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
106 /* Set DLL Tuning Window */
107 ret = pci_read_config_dword(chip->pdev,
108 O2_SD_TUNING_CTRL, &scratch_32);
111 scratch_32 &= ~(0x000000FF);
112 scratch_32 |= 0x00000066;
113 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
115 /* Set UHS2 T_EIDLE */
116 ret = pci_read_config_dword(chip->pdev,
117 O2_SD_UHS2_L1_CTRL, &scratch_32);
120 scratch_32 &= ~(0x000000FC);
121 scratch_32 |= 0x00000084;
122 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
124 /* Set UHS2 Termination */
125 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
128 scratch_32 &= ~((1 << 21) | (1 << 30));
130 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
132 /* Set L1 Entrance Timer */
133 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
136 scratch_32 &= ~(0xf0000000);
137 scratch_32 |= 0x30000000;
138 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
140 ret = pci_read_config_dword(chip->pdev,
141 O2_SD_MISC_CTRL4, &scratch_32);
144 scratch_32 &= ~(0x000f0000);
145 scratch_32 |= 0x00080000;
146 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
148 EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
150 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
152 struct sdhci_pci_chip *chip;
153 struct sdhci_host *host;
158 switch (chip->pdev->device) {
159 case PCI_DEVICE_ID_O2_SDS0:
160 case PCI_DEVICE_ID_O2_SEABIRD0:
161 case PCI_DEVICE_ID_O2_SEABIRD1:
162 case PCI_DEVICE_ID_O2_SDS1:
163 case PCI_DEVICE_ID_O2_FUJIN2:
164 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
166 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
168 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
170 /* set dll watch dog timer */
171 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
173 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
182 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
184 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
190 switch (chip->pdev->device) {
191 case PCI_DEVICE_ID_O2_8220:
192 case PCI_DEVICE_ID_O2_8221:
193 case PCI_DEVICE_ID_O2_8320:
194 case PCI_DEVICE_ID_O2_8321:
195 /* This extra setup is required due to broken ADMA. */
196 ret = pci_read_config_byte(chip->pdev,
197 O2_SD_LOCK_WP, &scratch);
201 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
203 /* Set Multi 3 to VCC3V# */
204 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
206 /* Disable CLK_REQ# support after media DET */
207 ret = pci_read_config_byte(chip->pdev,
208 O2_SD_CLKREQ, &scratch);
212 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
214 /* Choose capabilities, enable SDMA. We have to write 0x01
215 * to the capabilities register first to unlock it.
217 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
221 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
222 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
224 /* Disable ADMA1/2 */
225 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
226 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
228 /* Disable the infinite transfer mode */
229 ret = pci_read_config_byte(chip->pdev,
230 O2_SD_INF_MOD, &scratch);
234 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
237 ret = pci_read_config_byte(chip->pdev,
238 O2_SD_LOCK_WP, &scratch);
242 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
244 case PCI_DEVICE_ID_O2_SDS0:
245 case PCI_DEVICE_ID_O2_SDS1:
246 case PCI_DEVICE_ID_O2_FUJIN2:
248 ret = pci_read_config_byte(chip->pdev,
249 O2_SD_LOCK_WP, &scratch);
254 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
256 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
257 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
258 ret = pci_read_config_dword(chip->pdev,
261 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
263 /* Check Whether subId is 0x11 or 0x12 */
264 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
265 scratch_32 = 0x2c280000;
267 /* Set Base Clock to 208MZ */
268 o2_pci_set_baseclk(chip, scratch_32);
269 ret = pci_read_config_dword(chip->pdev,
273 /* Enable Base Clk setting change */
274 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
275 pci_write_config_dword(chip->pdev,
279 /* Set Tuning Window to 4 */
280 pci_write_config_byte(chip->pdev,
281 O2_SD_TUNING_CTRL, 0x44);
287 /* Enable 8520 led function */
288 o2_pci_led_enable(chip);
290 /* Set timeout CLK */
291 ret = pci_read_config_dword(chip->pdev,
292 O2_SD_CLK_SETTING, &scratch_32);
296 scratch_32 &= ~(0xFF00);
297 scratch_32 |= 0x07E0C800;
298 pci_write_config_dword(chip->pdev,
299 O2_SD_CLK_SETTING, scratch_32);
301 ret = pci_read_config_dword(chip->pdev,
302 O2_SD_CLKREQ, &scratch_32);
306 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
308 ret = pci_read_config_dword(chip->pdev,
309 O2_SD_PLL_SETTING, &scratch_32);
313 scratch_32 &= ~(0x1F3F070E);
314 scratch_32 |= 0x18270106;
315 pci_write_config_dword(chip->pdev,
316 O2_SD_PLL_SETTING, scratch_32);
318 /* Disable UHS1 funciton */
319 ret = pci_read_config_dword(chip->pdev,
320 O2_SD_CAP_REG2, &scratch_32);
323 scratch_32 &= ~(0xE0);
324 pci_write_config_dword(chip->pdev,
325 O2_SD_CAP_REG2, scratch_32);
327 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
328 sdhci_pci_o2_fujin2_pci_init(chip);
331 ret = pci_read_config_byte(chip->pdev,
332 O2_SD_LOCK_WP, &scratch);
336 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
338 case PCI_DEVICE_ID_O2_SEABIRD0:
339 case PCI_DEVICE_ID_O2_SEABIRD1:
341 ret = pci_read_config_byte(chip->pdev,
342 O2_SD_LOCK_WP, &scratch);
347 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
349 ret = pci_read_config_dword(chip->pdev,
350 O2_SD_PLL_SETTING, &scratch_32);
352 if ((scratch_32 & 0xff000000) == 0x01000000) {
353 scratch_32 &= 0x0000FFFF;
354 scratch_32 |= 0x1F340000;
356 pci_write_config_dword(chip->pdev,
357 O2_SD_PLL_SETTING, scratch_32);
359 scratch_32 &= 0x0000FFFF;
360 scratch_32 |= 0x2c280000;
362 pci_write_config_dword(chip->pdev,
363 O2_SD_PLL_SETTING, scratch_32);
365 ret = pci_read_config_dword(chip->pdev,
368 scratch_32 |= (1 << 22);
369 pci_write_config_dword(chip->pdev,
370 O2_SD_FUNC_REG4, scratch_32);
373 /* Set Tuning Windows to 5 */
374 pci_write_config_byte(chip->pdev,
375 O2_SD_TUNING_CTRL, 0x55);
377 ret = pci_read_config_byte(chip->pdev,
378 O2_SD_LOCK_WP, &scratch);
382 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
388 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
390 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
392 sdhci_pci_o2_probe(chip);
395 EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);