1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/scatterlist.h>
26 #include <linux/gpio.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mmc/sdhci-pci-data.h>
32 #include "sdhci-pci.h"
33 #include "sdhci-pci-o2micro.h"
35 /*****************************************************************************\
37 * Hardware specific quirk handling *
39 \*****************************************************************************/
41 static int ricoh_probe(struct sdhci_pci_chip *chip)
43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
58 SDHCI_TIMEOUT_CLK_UNIT |
65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
74 static const struct sdhci_pci_fixes sdhci_ricoh = {
76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
90 static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
95 static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
101 static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 SDHCI_QUIRK_NO_BUSY_IRQ |
104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
108 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
119 * ADMA operation is disabled for Moorestown platform due to
122 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
151 int err, irq, gpio = slot->cd_gpio;
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
156 if (!gpio_is_valid(gpio))
159 err = gpio_request(gpio, "sd_cd");
163 err = gpio_direction_input(gpio);
167 irq = gpio_to_irq(gpio);
171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
176 slot->cd_gpio = gpio;
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 .probe_slot = mrst_hc_probe_slot,
226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 .probe = mrst_hc_probe,
231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 .allow_runtime_pm = true,
234 .own_cd_for_runtime_pm = true,
237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 .allow_runtime_pm = true,
241 .probe_slot = mfd_sdio_probe_slot,
244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .allow_runtime_pm = true,
247 .probe_slot = mfd_emmc_probe_slot,
250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
270 static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
280 drive_strength = 1; /* 33-ohm */
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
285 return drive_strength;
288 /* Try to read the drive strength from the card */
289 static void spt_read_drive_strength(struct sdhci_host *host)
294 if (sdhci_pci_spt_drive_strength)
297 sdhci_pci_spt_drive_strength = -1;
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
327 if (t != 0x200 && t != 0x300)
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
333 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
336 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
337 MMC_CAP_BUS_WIDTH_TEST |
338 MMC_CAP_WAIT_WHILE_BUSY;
339 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
340 slot->hw_reset = sdhci_pci_int_hw_reset;
341 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
342 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
343 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
344 spt_read_drive_strength(slot->host);
345 slot->select_drive_strength = spt_select_drive_strength;
350 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
352 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
353 MMC_CAP_BUS_WIDTH_TEST |
354 MMC_CAP_WAIT_WHILE_BUSY;
358 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
360 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
361 MMC_CAP_WAIT_WHILE_BUSY;
362 slot->cd_con_id = NULL;
364 slot->cd_override_level = true;
368 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
369 .allow_runtime_pm = true,
370 .probe_slot = byt_emmc_probe_slot,
371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
373 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
374 SDHCI_QUIRK2_STOP_WITH_TC,
377 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
380 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
381 .allow_runtime_pm = true,
382 .probe_slot = byt_sdio_probe_slot,
385 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
388 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
389 SDHCI_QUIRK2_STOP_WITH_TC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 .probe_slot = byt_sd_probe_slot,
395 /* Define Host controllers for Intel Merrifield platform */
396 #define INTEL_MRFL_EMMC_0 0
397 #define INTEL_MRFL_EMMC_1 1
399 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
401 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
402 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
403 /* SD support is not ready yet */
406 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
412 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
414 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
416 .allow_runtime_pm = true,
417 .probe_slot = intel_mrfl_mmc_probe_slot,
420 /* O2Micro extra registers */
421 #define O2_SD_LOCK_WP 0xD3
422 #define O2_SD_MULTI_VCC3V 0xEE
423 #define O2_SD_CLKREQ 0xEC
424 #define O2_SD_CAPS 0xE0
425 #define O2_SD_ADMA1 0xE2
426 #define O2_SD_ADMA2 0xE7
427 #define O2_SD_INF_MOD 0xF1
429 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
434 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
439 * Turn PMOS on [bit 0], set over current detection to 2.4 V
440 * [bit 1:2] and enable over current debouncing [bit 6].
447 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
454 static int jmicron_probe(struct sdhci_pci_chip *chip)
459 if (chip->pdev->revision == 0) {
460 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
461 SDHCI_QUIRK_32BIT_DMA_SIZE |
462 SDHCI_QUIRK_32BIT_ADMA_SIZE |
463 SDHCI_QUIRK_RESET_AFTER_REQUEST |
464 SDHCI_QUIRK_BROKEN_SMALL_PIO;
468 * JMicron chips can have two interfaces to the same hardware
469 * in order to work around limitations in Microsoft's driver.
470 * We need to make sure we only bind to one of them.
472 * This code assumes two things:
474 * 1. The PCI code adds subfunctions in order.
476 * 2. The MMC interface has a lower subfunction number
477 * than the SD interface.
479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
481 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
482 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
485 struct pci_dev *sd_dev;
488 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
489 mmcdev, sd_dev)) != NULL) {
490 if ((PCI_SLOT(chip->pdev->devfn) ==
491 PCI_SLOT(sd_dev->devfn)) &&
492 (chip->pdev->bus == sd_dev->bus))
498 dev_info(&chip->pdev->dev, "Refusing to bind to "
499 "secondary interface.\n");
505 * JMicron chips need a bit of a nudge to enable the power
508 ret = jmicron_pmos(chip, 1);
510 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
514 /* quirk for unsable RO-detection on JM388 chips */
515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
517 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
522 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
526 scratch = readb(host->ioaddr + 0xC0);
533 writeb(scratch, host->ioaddr + 0xC0);
536 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
538 if (slot->chip->pdev->revision == 0) {
541 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
542 version = (version & SDHCI_VENDOR_VER_MASK) >>
543 SDHCI_VENDOR_VER_SHIFT;
546 * Older versions of the chip have lots of nasty glitches
547 * in the ADMA engine. It's best just to avoid it
551 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
554 /* JM388 MMC doesn't support 1.8V while SD supports it */
555 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
556 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
557 MMC_VDD_29_30 | MMC_VDD_30_31 |
558 MMC_VDD_165_195; /* allow 1.8V */
559 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
560 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
564 * The secondary interface requires a bit set to get the
567 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
568 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
569 jmicron_enable_mmc(slot->host, 1);
571 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
576 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
581 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
582 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
583 jmicron_enable_mmc(slot->host, 0);
586 static int jmicron_suspend(struct sdhci_pci_chip *chip)
590 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
591 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
592 for (i = 0; i < chip->num_slots; i++)
593 jmicron_enable_mmc(chip->slots[i]->host, 0);
599 static int jmicron_resume(struct sdhci_pci_chip *chip)
603 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
604 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
605 for (i = 0; i < chip->num_slots; i++)
606 jmicron_enable_mmc(chip->slots[i]->host, 1);
609 ret = jmicron_pmos(chip, 1);
611 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
618 static const struct sdhci_pci_fixes sdhci_o2 = {
619 .probe = sdhci_pci_o2_probe,
620 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
621 .probe_slot = sdhci_pci_o2_probe_slot,
622 .resume = sdhci_pci_o2_resume,
625 static const struct sdhci_pci_fixes sdhci_jmicron = {
626 .probe = jmicron_probe,
628 .probe_slot = jmicron_probe_slot,
629 .remove_slot = jmicron_remove_slot,
631 .suspend = jmicron_suspend,
632 .resume = jmicron_resume,
635 /* SysKonnect CardBus2SDIO extra registers */
636 #define SYSKT_CTRL 0x200
637 #define SYSKT_RDFIFO_STAT 0x204
638 #define SYSKT_WRFIFO_STAT 0x208
639 #define SYSKT_POWER_DATA 0x20c
640 #define SYSKT_POWER_330 0xef
641 #define SYSKT_POWER_300 0xf8
642 #define SYSKT_POWER_184 0xcc
643 #define SYSKT_POWER_CMD 0x20d
644 #define SYSKT_POWER_START (1 << 7)
645 #define SYSKT_POWER_STATUS 0x20e
646 #define SYSKT_POWER_STATUS_OK (1 << 0)
647 #define SYSKT_BOARD_REV 0x210
648 #define SYSKT_CHIP_REV 0x211
649 #define SYSKT_CONF_DATA 0x212
650 #define SYSKT_CONF_DATA_1V8 (1 << 2)
651 #define SYSKT_CONF_DATA_2V5 (1 << 1)
652 #define SYSKT_CONF_DATA_3V3 (1 << 0)
654 static int syskt_probe(struct sdhci_pci_chip *chip)
656 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
657 chip->pdev->class &= ~0x0000FF;
658 chip->pdev->class |= PCI_SDHCI_IFDMA;
663 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
667 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
668 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
669 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
670 "board rev %d.%d, chip rev %d.%d\n",
671 board_rev >> 4, board_rev & 0xf,
672 chip_rev >> 4, chip_rev & 0xf);
673 if (chip_rev >= 0x20)
674 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
676 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
677 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
679 tm = 10; /* Wait max 1 ms */
681 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
682 if (ps & SYSKT_POWER_STATUS_OK)
687 dev_err(&slot->chip->pdev->dev,
688 "power regulator never stabilized");
689 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
696 static const struct sdhci_pci_fixes sdhci_syskt = {
697 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
698 .probe = syskt_probe,
699 .probe_slot = syskt_probe_slot,
702 static int via_probe(struct sdhci_pci_chip *chip)
704 if (chip->pdev->revision == 0x10)
705 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
710 static const struct sdhci_pci_fixes sdhci_via = {
714 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
716 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
720 static const struct sdhci_pci_fixes sdhci_rtsx = {
721 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
722 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
723 SDHCI_QUIRK2_BROKEN_DDR50,
724 .probe_slot = rtsx_probe_slot,
727 static int amd_probe(struct sdhci_pci_chip *chip)
729 struct pci_dev *smbus_dev;
731 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
732 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
734 if (smbus_dev && (smbus_dev->revision < 0x51)) {
735 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
736 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
742 static const struct sdhci_pci_fixes sdhci_amd = {
746 static const struct pci_device_id pci_ids[] = {
748 .vendor = PCI_VENDOR_ID_RICOH,
749 .device = PCI_DEVICE_ID_RICOH_R5C822,
750 .subvendor = PCI_ANY_ID,
751 .subdevice = PCI_ANY_ID,
752 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
756 .vendor = PCI_VENDOR_ID_RICOH,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
764 .vendor = PCI_VENDOR_ID_RICOH,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
772 .vendor = PCI_VENDOR_ID_RICOH,
774 .subvendor = PCI_ANY_ID,
775 .subdevice = PCI_ANY_ID,
776 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
780 .vendor = PCI_VENDOR_ID_ENE,
781 .device = PCI_DEVICE_ID_ENE_CB712_SD,
782 .subvendor = PCI_ANY_ID,
783 .subdevice = PCI_ANY_ID,
784 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
788 .vendor = PCI_VENDOR_ID_ENE,
789 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
790 .subvendor = PCI_ANY_ID,
791 .subdevice = PCI_ANY_ID,
792 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
796 .vendor = PCI_VENDOR_ID_ENE,
797 .device = PCI_DEVICE_ID_ENE_CB714_SD,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
804 .vendor = PCI_VENDOR_ID_ENE,
805 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
806 .subvendor = PCI_ANY_ID,
807 .subdevice = PCI_ANY_ID,
808 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
812 .vendor = PCI_VENDOR_ID_MARVELL,
813 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
816 .driver_data = (kernel_ulong_t)&sdhci_cafe,
820 .vendor = PCI_VENDOR_ID_JMICRON,
821 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
822 .subvendor = PCI_ANY_ID,
823 .subdevice = PCI_ANY_ID,
824 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
828 .vendor = PCI_VENDOR_ID_JMICRON,
829 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
836 .vendor = PCI_VENDOR_ID_JMICRON,
837 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
838 .subvendor = PCI_ANY_ID,
839 .subdevice = PCI_ANY_ID,
840 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
844 .vendor = PCI_VENDOR_ID_JMICRON,
845 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
846 .subvendor = PCI_ANY_ID,
847 .subdevice = PCI_ANY_ID,
848 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
852 .vendor = PCI_VENDOR_ID_SYSKONNECT,
854 .subvendor = PCI_ANY_ID,
855 .subdevice = PCI_ANY_ID,
856 .driver_data = (kernel_ulong_t)&sdhci_syskt,
860 .vendor = PCI_VENDOR_ID_VIA,
862 .subvendor = PCI_ANY_ID,
863 .subdevice = PCI_ANY_ID,
864 .driver_data = (kernel_ulong_t)&sdhci_via,
868 .vendor = PCI_VENDOR_ID_REALTEK,
870 .subvendor = PCI_ANY_ID,
871 .subdevice = PCI_ANY_ID,
872 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
876 .vendor = PCI_VENDOR_ID_INTEL,
877 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
878 .subvendor = PCI_ANY_ID,
879 .subdevice = PCI_ANY_ID,
880 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
884 .vendor = PCI_VENDOR_ID_INTEL,
885 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
886 .subvendor = PCI_ANY_ID,
887 .subdevice = PCI_ANY_ID,
888 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
892 .vendor = PCI_VENDOR_ID_INTEL,
893 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
894 .subvendor = PCI_ANY_ID,
895 .subdevice = PCI_ANY_ID,
896 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
900 .vendor = PCI_VENDOR_ID_INTEL,
901 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
902 .subvendor = PCI_ANY_ID,
903 .subdevice = PCI_ANY_ID,
904 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
908 .vendor = PCI_VENDOR_ID_INTEL,
909 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
910 .subvendor = PCI_ANY_ID,
911 .subdevice = PCI_ANY_ID,
912 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
916 .vendor = PCI_VENDOR_ID_INTEL,
917 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
918 .subvendor = PCI_ANY_ID,
919 .subdevice = PCI_ANY_ID,
920 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
924 .vendor = PCI_VENDOR_ID_INTEL,
925 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
926 .subvendor = PCI_ANY_ID,
927 .subdevice = PCI_ANY_ID,
928 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
932 .vendor = PCI_VENDOR_ID_INTEL,
933 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
940 .vendor = PCI_VENDOR_ID_INTEL,
941 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
942 .subvendor = PCI_ANY_ID,
943 .subdevice = PCI_ANY_ID,
944 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
948 .vendor = PCI_VENDOR_ID_INTEL,
949 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
950 .subvendor = PCI_ANY_ID,
951 .subdevice = PCI_ANY_ID,
952 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
956 .vendor = PCI_VENDOR_ID_INTEL,
957 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
958 .subvendor = PCI_ANY_ID,
959 .subdevice = PCI_ANY_ID,
960 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
964 .vendor = PCI_VENDOR_ID_INTEL,
965 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
966 .subvendor = PCI_ANY_ID,
967 .subdevice = PCI_ANY_ID,
968 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
972 .vendor = PCI_VENDOR_ID_INTEL,
973 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
974 .subvendor = PCI_ANY_ID,
975 .subdevice = PCI_ANY_ID,
976 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
980 .vendor = PCI_VENDOR_ID_INTEL,
981 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
982 .subvendor = PCI_ANY_ID,
983 .subdevice = PCI_ANY_ID,
984 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
988 .vendor = PCI_VENDOR_ID_INTEL,
989 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
990 .subvendor = PCI_ANY_ID,
991 .subdevice = PCI_ANY_ID,
992 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
996 .vendor = PCI_VENDOR_ID_INTEL,
997 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
998 .subvendor = PCI_ANY_ID,
999 .subdevice = PCI_ANY_ID,
1000 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1004 .vendor = PCI_VENDOR_ID_INTEL,
1005 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1006 .subvendor = PCI_ANY_ID,
1007 .subdevice = PCI_ANY_ID,
1008 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1012 .vendor = PCI_VENDOR_ID_INTEL,
1013 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1014 .subvendor = PCI_ANY_ID,
1015 .subdevice = PCI_ANY_ID,
1016 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1020 .vendor = PCI_VENDOR_ID_INTEL,
1021 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1022 .subvendor = PCI_ANY_ID,
1023 .subdevice = PCI_ANY_ID,
1024 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1028 .vendor = PCI_VENDOR_ID_INTEL,
1029 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1030 .subvendor = PCI_ANY_ID,
1031 .subdevice = PCI_ANY_ID,
1032 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1036 .vendor = PCI_VENDOR_ID_INTEL,
1037 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1038 .subvendor = PCI_ANY_ID,
1039 .subdevice = PCI_ANY_ID,
1040 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1044 .vendor = PCI_VENDOR_ID_INTEL,
1045 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1046 .subvendor = PCI_ANY_ID,
1047 .subdevice = PCI_ANY_ID,
1048 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1052 .vendor = PCI_VENDOR_ID_INTEL,
1053 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1054 .subvendor = PCI_ANY_ID,
1055 .subdevice = PCI_ANY_ID,
1056 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1060 .vendor = PCI_VENDOR_ID_INTEL,
1061 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1062 .subvendor = PCI_ANY_ID,
1063 .subdevice = PCI_ANY_ID,
1064 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1068 .vendor = PCI_VENDOR_ID_INTEL,
1069 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1070 .subvendor = PCI_ANY_ID,
1071 .subdevice = PCI_ANY_ID,
1072 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1076 .vendor = PCI_VENDOR_ID_INTEL,
1077 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1078 .subvendor = PCI_ANY_ID,
1079 .subdevice = PCI_ANY_ID,
1080 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1084 .vendor = PCI_VENDOR_ID_INTEL,
1085 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1086 .subvendor = PCI_ANY_ID,
1087 .subdevice = PCI_ANY_ID,
1088 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1092 .vendor = PCI_VENDOR_ID_O2,
1093 .device = PCI_DEVICE_ID_O2_8120,
1094 .subvendor = PCI_ANY_ID,
1095 .subdevice = PCI_ANY_ID,
1096 .driver_data = (kernel_ulong_t)&sdhci_o2,
1100 .vendor = PCI_VENDOR_ID_O2,
1101 .device = PCI_DEVICE_ID_O2_8220,
1102 .subvendor = PCI_ANY_ID,
1103 .subdevice = PCI_ANY_ID,
1104 .driver_data = (kernel_ulong_t)&sdhci_o2,
1108 .vendor = PCI_VENDOR_ID_O2,
1109 .device = PCI_DEVICE_ID_O2_8221,
1110 .subvendor = PCI_ANY_ID,
1111 .subdevice = PCI_ANY_ID,
1112 .driver_data = (kernel_ulong_t)&sdhci_o2,
1116 .vendor = PCI_VENDOR_ID_O2,
1117 .device = PCI_DEVICE_ID_O2_8320,
1118 .subvendor = PCI_ANY_ID,
1119 .subdevice = PCI_ANY_ID,
1120 .driver_data = (kernel_ulong_t)&sdhci_o2,
1124 .vendor = PCI_VENDOR_ID_O2,
1125 .device = PCI_DEVICE_ID_O2_8321,
1126 .subvendor = PCI_ANY_ID,
1127 .subdevice = PCI_ANY_ID,
1128 .driver_data = (kernel_ulong_t)&sdhci_o2,
1132 .vendor = PCI_VENDOR_ID_O2,
1133 .device = PCI_DEVICE_ID_O2_FUJIN2,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .driver_data = (kernel_ulong_t)&sdhci_o2,
1140 .vendor = PCI_VENDOR_ID_O2,
1141 .device = PCI_DEVICE_ID_O2_SDS0,
1142 .subvendor = PCI_ANY_ID,
1143 .subdevice = PCI_ANY_ID,
1144 .driver_data = (kernel_ulong_t)&sdhci_o2,
1148 .vendor = PCI_VENDOR_ID_O2,
1149 .device = PCI_DEVICE_ID_O2_SDS1,
1150 .subvendor = PCI_ANY_ID,
1151 .subdevice = PCI_ANY_ID,
1152 .driver_data = (kernel_ulong_t)&sdhci_o2,
1156 .vendor = PCI_VENDOR_ID_O2,
1157 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1158 .subvendor = PCI_ANY_ID,
1159 .subdevice = PCI_ANY_ID,
1160 .driver_data = (kernel_ulong_t)&sdhci_o2,
1164 .vendor = PCI_VENDOR_ID_O2,
1165 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1166 .subvendor = PCI_ANY_ID,
1167 .subdevice = PCI_ANY_ID,
1168 .driver_data = (kernel_ulong_t)&sdhci_o2,
1171 .vendor = PCI_VENDOR_ID_AMD,
1172 .device = PCI_ANY_ID,
1173 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1174 .class_mask = 0xFFFF00,
1175 .subvendor = PCI_ANY_ID,
1176 .subdevice = PCI_ANY_ID,
1177 .driver_data = (kernel_ulong_t)&sdhci_amd,
1179 { /* Generic SD host controller */
1180 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1183 { /* end: all zeroes */ },
1186 MODULE_DEVICE_TABLE(pci, pci_ids);
1188 /*****************************************************************************\
1190 * SDHCI core callbacks *
1192 \*****************************************************************************/
1194 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1196 struct sdhci_pci_slot *slot;
1197 struct pci_dev *pdev;
1200 slot = sdhci_priv(host);
1201 pdev = slot->chip->pdev;
1203 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1204 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1205 (host->flags & SDHCI_USE_SDMA)) {
1206 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1207 "doesn't fully claim to support it.\n");
1210 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1211 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1212 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1214 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1216 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1220 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1224 pci_set_master(pdev);
1229 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1233 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1236 case MMC_BUS_WIDTH_8:
1237 ctrl |= SDHCI_CTRL_8BITBUS;
1238 ctrl &= ~SDHCI_CTRL_4BITBUS;
1240 case MMC_BUS_WIDTH_4:
1241 ctrl |= SDHCI_CTRL_4BITBUS;
1242 ctrl &= ~SDHCI_CTRL_8BITBUS;
1245 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1252 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1254 struct sdhci_pci_slot *slot = sdhci_priv(host);
1255 int rst_n_gpio = slot->rst_n_gpio;
1257 if (!gpio_is_valid(rst_n_gpio))
1259 gpio_set_value_cansleep(rst_n_gpio, 0);
1260 /* For eMMC, minimum is 1us but give it 10us for good measure */
1262 gpio_set_value_cansleep(rst_n_gpio, 1);
1263 /* For eMMC, minimum is 200us but give it 300us for good measure */
1264 usleep_range(300, 1000);
1267 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1269 struct sdhci_pci_slot *slot = sdhci_priv(host);
1272 slot->hw_reset(host);
1275 static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1276 struct mmc_card *card,
1277 unsigned int max_dtr, int host_drv,
1278 int card_drv, int *drv_type)
1280 struct sdhci_pci_slot *slot = sdhci_priv(host);
1282 if (!slot->select_drive_strength)
1285 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1286 card_drv, drv_type);
1289 static const struct sdhci_ops sdhci_pci_ops = {
1290 .set_clock = sdhci_set_clock,
1291 .enable_dma = sdhci_pci_enable_dma,
1292 .set_bus_width = sdhci_pci_set_bus_width,
1293 .reset = sdhci_reset,
1294 .set_uhs_signaling = sdhci_set_uhs_signaling,
1295 .hw_reset = sdhci_pci_hw_reset,
1296 .select_drive_strength = sdhci_pci_select_drive_strength,
1299 /*****************************************************************************\
1303 \*****************************************************************************/
1307 static int sdhci_pci_suspend(struct device *dev)
1309 struct pci_dev *pdev = to_pci_dev(dev);
1310 struct sdhci_pci_chip *chip;
1311 struct sdhci_pci_slot *slot;
1312 mmc_pm_flag_t slot_pm_flags;
1313 mmc_pm_flag_t pm_flags = 0;
1316 chip = pci_get_drvdata(pdev);
1320 for (i = 0; i < chip->num_slots; i++) {
1321 slot = chip->slots[i];
1325 ret = sdhci_suspend_host(slot->host);
1328 goto err_pci_suspend;
1330 slot_pm_flags = slot->host->mmc->pm_flags;
1331 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1332 sdhci_enable_irq_wakeups(slot->host);
1334 pm_flags |= slot_pm_flags;
1337 if (chip->fixes && chip->fixes->suspend) {
1338 ret = chip->fixes->suspend(chip);
1340 goto err_pci_suspend;
1343 if (pm_flags & MMC_PM_KEEP_POWER) {
1344 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1345 device_init_wakeup(dev, true);
1347 device_init_wakeup(dev, false);
1349 device_init_wakeup(dev, false);
1355 sdhci_resume_host(chip->slots[i]->host);
1359 static int sdhci_pci_resume(struct device *dev)
1361 struct pci_dev *pdev = to_pci_dev(dev);
1362 struct sdhci_pci_chip *chip;
1363 struct sdhci_pci_slot *slot;
1366 chip = pci_get_drvdata(pdev);
1370 if (chip->fixes && chip->fixes->resume) {
1371 ret = chip->fixes->resume(chip);
1376 for (i = 0; i < chip->num_slots; i++) {
1377 slot = chip->slots[i];
1381 ret = sdhci_resume_host(slot->host);
1389 static int sdhci_pci_runtime_suspend(struct device *dev)
1391 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1392 struct sdhci_pci_chip *chip;
1393 struct sdhci_pci_slot *slot;
1396 chip = pci_get_drvdata(pdev);
1400 for (i = 0; i < chip->num_slots; i++) {
1401 slot = chip->slots[i];
1405 ret = sdhci_runtime_suspend_host(slot->host);
1408 goto err_pci_runtime_suspend;
1411 if (chip->fixes && chip->fixes->suspend) {
1412 ret = chip->fixes->suspend(chip);
1414 goto err_pci_runtime_suspend;
1419 err_pci_runtime_suspend:
1421 sdhci_runtime_resume_host(chip->slots[i]->host);
1425 static int sdhci_pci_runtime_resume(struct device *dev)
1427 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1428 struct sdhci_pci_chip *chip;
1429 struct sdhci_pci_slot *slot;
1432 chip = pci_get_drvdata(pdev);
1436 if (chip->fixes && chip->fixes->resume) {
1437 ret = chip->fixes->resume(chip);
1442 for (i = 0; i < chip->num_slots; i++) {
1443 slot = chip->slots[i];
1447 ret = sdhci_runtime_resume_host(slot->host);
1455 #else /* CONFIG_PM */
1457 #define sdhci_pci_suspend NULL
1458 #define sdhci_pci_resume NULL
1460 #endif /* CONFIG_PM */
1462 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1463 .suspend = sdhci_pci_suspend,
1464 .resume = sdhci_pci_resume,
1465 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1466 sdhci_pci_runtime_resume, NULL)
1469 /*****************************************************************************\
1471 * Device probing/removal *
1473 \*****************************************************************************/
1475 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1476 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1479 struct sdhci_pci_slot *slot;
1480 struct sdhci_host *host;
1481 int ret, bar = first_bar + slotno;
1483 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1484 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1485 return ERR_PTR(-ENODEV);
1488 if (pci_resource_len(pdev, bar) < 0x100) {
1489 dev_err(&pdev->dev, "Invalid iomem size. You may "
1490 "experience problems.\n");
1493 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1494 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1495 return ERR_PTR(-ENODEV);
1498 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1499 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1500 return ERR_PTR(-ENODEV);
1503 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1505 dev_err(&pdev->dev, "cannot allocate host\n");
1506 return ERR_CAST(host);
1509 slot = sdhci_priv(host);
1513 slot->pci_bar = bar;
1514 slot->rst_n_gpio = -EINVAL;
1515 slot->cd_gpio = -EINVAL;
1518 /* Retrieve platform data if there is any */
1519 if (*sdhci_pci_get_data)
1520 slot->data = sdhci_pci_get_data(pdev, slotno);
1523 if (slot->data->setup) {
1524 ret = slot->data->setup(slot->data);
1526 dev_err(&pdev->dev, "platform setup failed\n");
1530 slot->rst_n_gpio = slot->data->rst_n_gpio;
1531 slot->cd_gpio = slot->data->cd_gpio;
1534 host->hw_name = "PCI";
1535 host->ops = &sdhci_pci_ops;
1536 host->quirks = chip->quirks;
1537 host->quirks2 = chip->quirks2;
1539 host->irq = pdev->irq;
1541 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1543 dev_err(&pdev->dev, "cannot request region\n");
1547 host->ioaddr = pci_ioremap_bar(pdev, bar);
1548 if (!host->ioaddr) {
1549 dev_err(&pdev->dev, "failed to remap registers\n");
1554 if (chip->fixes && chip->fixes->probe_slot) {
1555 ret = chip->fixes->probe_slot(slot);
1560 if (gpio_is_valid(slot->rst_n_gpio)) {
1561 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1562 gpio_direction_output(slot->rst_n_gpio, 1);
1563 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1564 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1566 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1567 slot->rst_n_gpio = -EINVAL;
1571 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1572 host->mmc->slotno = slotno;
1573 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1575 if (slot->cd_idx >= 0 &&
1576 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1577 slot->cd_override_level, 0, NULL)) {
1578 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1582 ret = sdhci_add_host(host);
1586 sdhci_pci_add_own_cd(slot);
1589 * Check if the chip needs a separate GPIO for card detect to wake up
1590 * from runtime suspend. If it is not there, don't allow runtime PM.
1591 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1593 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1594 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1595 chip->allow_runtime_pm = false;
1600 if (gpio_is_valid(slot->rst_n_gpio))
1601 gpio_free(slot->rst_n_gpio);
1603 if (chip->fixes && chip->fixes->remove_slot)
1604 chip->fixes->remove_slot(slot, 0);
1607 iounmap(host->ioaddr);
1610 pci_release_region(pdev, bar);
1613 if (slot->data && slot->data->cleanup)
1614 slot->data->cleanup(slot->data);
1617 sdhci_free_host(host);
1619 return ERR_PTR(ret);
1622 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1627 sdhci_pci_remove_own_cd(slot);
1630 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1631 if (scratch == (u32)-1)
1634 sdhci_remove_host(slot->host, dead);
1636 if (gpio_is_valid(slot->rst_n_gpio))
1637 gpio_free(slot->rst_n_gpio);
1639 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1640 slot->chip->fixes->remove_slot(slot, dead);
1642 if (slot->data && slot->data->cleanup)
1643 slot->data->cleanup(slot->data);
1645 pci_release_region(slot->chip->pdev, slot->pci_bar);
1647 sdhci_free_host(slot->host);
1650 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1652 pm_runtime_put_noidle(dev);
1653 pm_runtime_allow(dev);
1654 pm_runtime_set_autosuspend_delay(dev, 50);
1655 pm_runtime_use_autosuspend(dev);
1656 pm_suspend_ignore_children(dev, 1);
1659 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1661 pm_runtime_forbid(dev);
1662 pm_runtime_get_noresume(dev);
1665 static int sdhci_pci_probe(struct pci_dev *pdev,
1666 const struct pci_device_id *ent)
1668 struct sdhci_pci_chip *chip;
1669 struct sdhci_pci_slot *slot;
1671 u8 slots, first_bar;
1674 BUG_ON(pdev == NULL);
1675 BUG_ON(ent == NULL);
1677 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1678 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1680 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1684 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1685 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1689 BUG_ON(slots > MAX_SLOTS);
1691 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1695 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1697 if (first_bar > 5) {
1698 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1702 ret = pci_enable_device(pdev);
1706 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1713 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1715 chip->quirks = chip->fixes->quirks;
1716 chip->quirks2 = chip->fixes->quirks2;
1717 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1719 chip->num_slots = slots;
1721 pci_set_drvdata(pdev, chip);
1723 if (chip->fixes && chip->fixes->probe) {
1724 ret = chip->fixes->probe(chip);
1729 slots = chip->num_slots; /* Quirk may have changed this */
1731 for (i = 0; i < slots; i++) {
1732 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1734 for (i--; i >= 0; i--)
1735 sdhci_pci_remove_slot(chip->slots[i]);
1736 ret = PTR_ERR(slot);
1740 chip->slots[i] = slot;
1743 if (chip->allow_runtime_pm)
1744 sdhci_pci_runtime_pm_allow(&pdev->dev);
1749 pci_set_drvdata(pdev, NULL);
1753 pci_disable_device(pdev);
1757 static void sdhci_pci_remove(struct pci_dev *pdev)
1760 struct sdhci_pci_chip *chip;
1762 chip = pci_get_drvdata(pdev);
1765 if (chip->allow_runtime_pm)
1766 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1768 for (i = 0; i < chip->num_slots; i++)
1769 sdhci_pci_remove_slot(chip->slots[i]);
1771 pci_set_drvdata(pdev, NULL);
1775 pci_disable_device(pdev);
1778 static struct pci_driver sdhci_driver = {
1779 .name = "sdhci-pci",
1780 .id_table = pci_ids,
1781 .probe = sdhci_pci_probe,
1782 .remove = sdhci_pci_remove,
1784 .pm = &sdhci_pci_pm_ops
1788 module_pci_driver(sdhci_driver);
1790 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1791 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1792 MODULE_LICENSE("GPL");