1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/scatterlist.h>
26 #include <linux/gpio.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mmc/sdhci-pci-data.h>
32 #include "sdhci-pci.h"
33 #include "sdhci-pci-o2micro.h"
35 /*****************************************************************************\
37 * Hardware specific quirk handling *
39 \*****************************************************************************/
41 static int ricoh_probe(struct sdhci_pci_chip *chip)
43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
58 SDHCI_TIMEOUT_CLK_UNIT |
65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
74 static const struct sdhci_pci_fixes sdhci_ricoh = {
76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
90 static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
95 static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
101 static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 SDHCI_QUIRK_NO_BUSY_IRQ |
104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
108 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
119 * ADMA operation is disabled for Moorestown platform due to
122 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
151 int err, irq, gpio = slot->cd_gpio;
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
156 if (!gpio_is_valid(gpio))
159 err = gpio_request(gpio, "sd_cd");
163 err = gpio_direction_input(gpio);
167 irq = gpio_to_irq(gpio);
171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
176 slot->cd_gpio = gpio;
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 .probe_slot = mrst_hc_probe_slot,
226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 .probe = mrst_hc_probe,
231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 .allow_runtime_pm = true,
234 .own_cd_for_runtime_pm = true,
237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 .allow_runtime_pm = true,
241 .probe_slot = mfd_sdio_probe_slot,
244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .allow_runtime_pm = true,
247 .probe_slot = mfd_emmc_probe_slot,
250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
270 static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
280 drive_strength = 1; /* 33-ohm */
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
285 return drive_strength;
288 /* Try to read the drive strength from the card */
289 static void spt_read_drive_strength(struct sdhci_host *host)
294 if (sdhci_pci_spt_drive_strength)
297 sdhci_pci_spt_drive_strength = -1;
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
327 if (t != 0x200 && t != 0x300)
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
333 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
336 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
337 MMC_CAP_BUS_WIDTH_TEST |
338 MMC_CAP_WAIT_WHILE_BUSY;
339 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
340 slot->hw_reset = sdhci_pci_int_hw_reset;
341 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
342 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
343 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
344 spt_read_drive_strength(slot->host);
345 slot->select_drive_strength = spt_select_drive_strength;
350 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
352 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
353 MMC_CAP_BUS_WIDTH_TEST |
354 MMC_CAP_WAIT_WHILE_BUSY;
358 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
360 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
361 MMC_CAP_WAIT_WHILE_BUSY;
362 slot->cd_con_id = NULL;
364 slot->cd_override_level = true;
368 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
369 .allow_runtime_pm = true,
370 .probe_slot = byt_emmc_probe_slot,
371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
373 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
374 SDHCI_QUIRK2_STOP_WITH_TC,
377 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
380 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
381 .allow_runtime_pm = true,
382 .probe_slot = byt_sdio_probe_slot,
385 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
388 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
389 SDHCI_QUIRK2_STOP_WITH_TC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 .probe_slot = byt_sd_probe_slot,
395 /* Define Host controllers for Intel Merrifield platform */
396 #define INTEL_MRFL_EMMC_0 0
397 #define INTEL_MRFL_EMMC_1 1
399 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
401 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
402 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
403 /* SD support is not ready yet */
406 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
412 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
414 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
416 .allow_runtime_pm = true,
417 .probe_slot = intel_mrfl_mmc_probe_slot,
420 /* O2Micro extra registers */
421 #define O2_SD_LOCK_WP 0xD3
422 #define O2_SD_MULTI_VCC3V 0xEE
423 #define O2_SD_CLKREQ 0xEC
424 #define O2_SD_CAPS 0xE0
425 #define O2_SD_ADMA1 0xE2
426 #define O2_SD_ADMA2 0xE7
427 #define O2_SD_INF_MOD 0xF1
429 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
434 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
439 * Turn PMOS on [bit 0], set over current detection to 2.4 V
440 * [bit 1:2] and enable over current debouncing [bit 6].
447 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
454 static int jmicron_probe(struct sdhci_pci_chip *chip)
459 if (chip->pdev->revision == 0) {
460 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
461 SDHCI_QUIRK_32BIT_DMA_SIZE |
462 SDHCI_QUIRK_32BIT_ADMA_SIZE |
463 SDHCI_QUIRK_RESET_AFTER_REQUEST |
464 SDHCI_QUIRK_BROKEN_SMALL_PIO;
468 * JMicron chips can have two interfaces to the same hardware
469 * in order to work around limitations in Microsoft's driver.
470 * We need to make sure we only bind to one of them.
472 * This code assumes two things:
474 * 1. The PCI code adds subfunctions in order.
476 * 2. The MMC interface has a lower subfunction number
477 * than the SD interface.
479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
481 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
482 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
485 struct pci_dev *sd_dev;
488 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
489 mmcdev, sd_dev)) != NULL) {
490 if ((PCI_SLOT(chip->pdev->devfn) ==
491 PCI_SLOT(sd_dev->devfn)) &&
492 (chip->pdev->bus == sd_dev->bus))
498 dev_info(&chip->pdev->dev, "Refusing to bind to "
499 "secondary interface.\n");
505 * JMicron chips need a bit of a nudge to enable the power
508 ret = jmicron_pmos(chip, 1);
510 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
514 /* quirk for unsable RO-detection on JM388 chips */
515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
517 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
522 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
526 scratch = readb(host->ioaddr + 0xC0);
533 writeb(scratch, host->ioaddr + 0xC0);
536 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
538 if (slot->chip->pdev->revision == 0) {
541 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
542 version = (version & SDHCI_VENDOR_VER_MASK) >>
543 SDHCI_VENDOR_VER_SHIFT;
546 * Older versions of the chip have lots of nasty glitches
547 * in the ADMA engine. It's best just to avoid it
551 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
554 /* JM388 MMC doesn't support 1.8V while SD supports it */
555 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
556 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
557 MMC_VDD_29_30 | MMC_VDD_30_31 |
558 MMC_VDD_165_195; /* allow 1.8V */
559 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
560 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
564 * The secondary interface requires a bit set to get the
567 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
568 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
569 jmicron_enable_mmc(slot->host, 1);
571 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
576 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
581 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
582 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
583 jmicron_enable_mmc(slot->host, 0);
586 static int jmicron_suspend(struct sdhci_pci_chip *chip)
590 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
591 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
592 for (i = 0; i < chip->num_slots; i++)
593 jmicron_enable_mmc(chip->slots[i]->host, 0);
599 static int jmicron_resume(struct sdhci_pci_chip *chip)
603 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
604 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
605 for (i = 0; i < chip->num_slots; i++)
606 jmicron_enable_mmc(chip->slots[i]->host, 1);
609 ret = jmicron_pmos(chip, 1);
611 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
618 static const struct sdhci_pci_fixes sdhci_o2 = {
619 .probe = sdhci_pci_o2_probe,
620 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
621 .probe_slot = sdhci_pci_o2_probe_slot,
622 .resume = sdhci_pci_o2_resume,
625 static const struct sdhci_pci_fixes sdhci_jmicron = {
626 .probe = jmicron_probe,
628 .probe_slot = jmicron_probe_slot,
629 .remove_slot = jmicron_remove_slot,
631 .suspend = jmicron_suspend,
632 .resume = jmicron_resume,
635 /* SysKonnect CardBus2SDIO extra registers */
636 #define SYSKT_CTRL 0x200
637 #define SYSKT_RDFIFO_STAT 0x204
638 #define SYSKT_WRFIFO_STAT 0x208
639 #define SYSKT_POWER_DATA 0x20c
640 #define SYSKT_POWER_330 0xef
641 #define SYSKT_POWER_300 0xf8
642 #define SYSKT_POWER_184 0xcc
643 #define SYSKT_POWER_CMD 0x20d
644 #define SYSKT_POWER_START (1 << 7)
645 #define SYSKT_POWER_STATUS 0x20e
646 #define SYSKT_POWER_STATUS_OK (1 << 0)
647 #define SYSKT_BOARD_REV 0x210
648 #define SYSKT_CHIP_REV 0x211
649 #define SYSKT_CONF_DATA 0x212
650 #define SYSKT_CONF_DATA_1V8 (1 << 2)
651 #define SYSKT_CONF_DATA_2V5 (1 << 1)
652 #define SYSKT_CONF_DATA_3V3 (1 << 0)
654 static int syskt_probe(struct sdhci_pci_chip *chip)
656 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
657 chip->pdev->class &= ~0x0000FF;
658 chip->pdev->class |= PCI_SDHCI_IFDMA;
663 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
667 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
668 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
669 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
670 "board rev %d.%d, chip rev %d.%d\n",
671 board_rev >> 4, board_rev & 0xf,
672 chip_rev >> 4, chip_rev & 0xf);
673 if (chip_rev >= 0x20)
674 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
676 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
677 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
679 tm = 10; /* Wait max 1 ms */
681 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
682 if (ps & SYSKT_POWER_STATUS_OK)
687 dev_err(&slot->chip->pdev->dev,
688 "power regulator never stabilized");
689 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
696 static const struct sdhci_pci_fixes sdhci_syskt = {
697 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
698 .probe = syskt_probe,
699 .probe_slot = syskt_probe_slot,
702 static int via_probe(struct sdhci_pci_chip *chip)
704 if (chip->pdev->revision == 0x10)
705 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
710 static const struct sdhci_pci_fixes sdhci_via = {
714 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
716 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
720 static const struct sdhci_pci_fixes sdhci_rtsx = {
721 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
722 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
723 SDHCI_QUIRK2_BROKEN_DDR50,
724 .probe_slot = rtsx_probe_slot,
727 /*AMD chipset generation*/
728 enum amd_chipset_gen {
729 AMD_CHIPSET_BEFORE_ML,
735 static int amd_probe(struct sdhci_pci_chip *chip)
737 struct pci_dev *smbus_dev;
738 enum amd_chipset_gen gen;
740 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
741 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
743 gen = AMD_CHIPSET_BEFORE_ML;
745 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
746 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
748 if (smbus_dev->revision < 0x51)
749 gen = AMD_CHIPSET_CZ;
751 gen = AMD_CHIPSET_NL;
753 gen = AMD_CHIPSET_UNKNOWN;
757 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
758 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
759 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
765 static const struct sdhci_pci_fixes sdhci_amd = {
769 static const struct pci_device_id pci_ids[] = {
771 .vendor = PCI_VENDOR_ID_RICOH,
772 .device = PCI_DEVICE_ID_RICOH_R5C822,
773 .subvendor = PCI_ANY_ID,
774 .subdevice = PCI_ANY_ID,
775 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
779 .vendor = PCI_VENDOR_ID_RICOH,
781 .subvendor = PCI_ANY_ID,
782 .subdevice = PCI_ANY_ID,
783 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
787 .vendor = PCI_VENDOR_ID_RICOH,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
791 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
795 .vendor = PCI_VENDOR_ID_RICOH,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
803 .vendor = PCI_VENDOR_ID_ENE,
804 .device = PCI_DEVICE_ID_ENE_CB712_SD,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
811 .vendor = PCI_VENDOR_ID_ENE,
812 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
815 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
819 .vendor = PCI_VENDOR_ID_ENE,
820 .device = PCI_DEVICE_ID_ENE_CB714_SD,
821 .subvendor = PCI_ANY_ID,
822 .subdevice = PCI_ANY_ID,
823 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
827 .vendor = PCI_VENDOR_ID_ENE,
828 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
831 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
835 .vendor = PCI_VENDOR_ID_MARVELL,
836 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
837 .subvendor = PCI_ANY_ID,
838 .subdevice = PCI_ANY_ID,
839 .driver_data = (kernel_ulong_t)&sdhci_cafe,
843 .vendor = PCI_VENDOR_ID_JMICRON,
844 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
847 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
851 .vendor = PCI_VENDOR_ID_JMICRON,
852 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
853 .subvendor = PCI_ANY_ID,
854 .subdevice = PCI_ANY_ID,
855 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
859 .vendor = PCI_VENDOR_ID_JMICRON,
860 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
861 .subvendor = PCI_ANY_ID,
862 .subdevice = PCI_ANY_ID,
863 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
867 .vendor = PCI_VENDOR_ID_JMICRON,
868 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
869 .subvendor = PCI_ANY_ID,
870 .subdevice = PCI_ANY_ID,
871 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
875 .vendor = PCI_VENDOR_ID_SYSKONNECT,
877 .subvendor = PCI_ANY_ID,
878 .subdevice = PCI_ANY_ID,
879 .driver_data = (kernel_ulong_t)&sdhci_syskt,
883 .vendor = PCI_VENDOR_ID_VIA,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .driver_data = (kernel_ulong_t)&sdhci_via,
891 .vendor = PCI_VENDOR_ID_REALTEK,
893 .subvendor = PCI_ANY_ID,
894 .subdevice = PCI_ANY_ID,
895 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
899 .vendor = PCI_VENDOR_ID_INTEL,
900 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
901 .subvendor = PCI_ANY_ID,
902 .subdevice = PCI_ANY_ID,
903 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
907 .vendor = PCI_VENDOR_ID_INTEL,
908 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
909 .subvendor = PCI_ANY_ID,
910 .subdevice = PCI_ANY_ID,
911 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
915 .vendor = PCI_VENDOR_ID_INTEL,
916 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
917 .subvendor = PCI_ANY_ID,
918 .subdevice = PCI_ANY_ID,
919 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
923 .vendor = PCI_VENDOR_ID_INTEL,
924 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
925 .subvendor = PCI_ANY_ID,
926 .subdevice = PCI_ANY_ID,
927 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
931 .vendor = PCI_VENDOR_ID_INTEL,
932 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
933 .subvendor = PCI_ANY_ID,
934 .subdevice = PCI_ANY_ID,
935 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
939 .vendor = PCI_VENDOR_ID_INTEL,
940 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
941 .subvendor = PCI_ANY_ID,
942 .subdevice = PCI_ANY_ID,
943 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
947 .vendor = PCI_VENDOR_ID_INTEL,
948 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
949 .subvendor = PCI_ANY_ID,
950 .subdevice = PCI_ANY_ID,
951 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
955 .vendor = PCI_VENDOR_ID_INTEL,
956 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
963 .vendor = PCI_VENDOR_ID_INTEL,
964 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
965 .subvendor = PCI_ANY_ID,
966 .subdevice = PCI_ANY_ID,
967 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
971 .vendor = PCI_VENDOR_ID_INTEL,
972 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
973 .subvendor = PCI_ANY_ID,
974 .subdevice = PCI_ANY_ID,
975 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
979 .vendor = PCI_VENDOR_ID_INTEL,
980 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
981 .subvendor = PCI_ANY_ID,
982 .subdevice = PCI_ANY_ID,
983 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
987 .vendor = PCI_VENDOR_ID_INTEL,
988 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
989 .subvendor = PCI_ANY_ID,
990 .subdevice = PCI_ANY_ID,
991 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
995 .vendor = PCI_VENDOR_ID_INTEL,
996 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
997 .subvendor = PCI_ANY_ID,
998 .subdevice = PCI_ANY_ID,
999 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1003 .vendor = PCI_VENDOR_ID_INTEL,
1004 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1011 .vendor = PCI_VENDOR_ID_INTEL,
1012 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1013 .subvendor = PCI_ANY_ID,
1014 .subdevice = PCI_ANY_ID,
1015 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1019 .vendor = PCI_VENDOR_ID_INTEL,
1020 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1021 .subvendor = PCI_ANY_ID,
1022 .subdevice = PCI_ANY_ID,
1023 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1027 .vendor = PCI_VENDOR_ID_INTEL,
1028 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1029 .subvendor = PCI_ANY_ID,
1030 .subdevice = PCI_ANY_ID,
1031 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1035 .vendor = PCI_VENDOR_ID_INTEL,
1036 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1037 .subvendor = PCI_ANY_ID,
1038 .subdevice = PCI_ANY_ID,
1039 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1043 .vendor = PCI_VENDOR_ID_INTEL,
1044 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1045 .subvendor = PCI_ANY_ID,
1046 .subdevice = PCI_ANY_ID,
1047 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1051 .vendor = PCI_VENDOR_ID_INTEL,
1052 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1053 .subvendor = PCI_ANY_ID,
1054 .subdevice = PCI_ANY_ID,
1055 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1059 .vendor = PCI_VENDOR_ID_INTEL,
1060 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1061 .subvendor = PCI_ANY_ID,
1062 .subdevice = PCI_ANY_ID,
1063 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1067 .vendor = PCI_VENDOR_ID_INTEL,
1068 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1069 .subvendor = PCI_ANY_ID,
1070 .subdevice = PCI_ANY_ID,
1071 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1075 .vendor = PCI_VENDOR_ID_INTEL,
1076 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1077 .subvendor = PCI_ANY_ID,
1078 .subdevice = PCI_ANY_ID,
1079 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1083 .vendor = PCI_VENDOR_ID_INTEL,
1084 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1085 .subvendor = PCI_ANY_ID,
1086 .subdevice = PCI_ANY_ID,
1087 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1091 .vendor = PCI_VENDOR_ID_INTEL,
1092 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1093 .subvendor = PCI_ANY_ID,
1094 .subdevice = PCI_ANY_ID,
1095 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1099 .vendor = PCI_VENDOR_ID_INTEL,
1100 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1101 .subvendor = PCI_ANY_ID,
1102 .subdevice = PCI_ANY_ID,
1103 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1107 .vendor = PCI_VENDOR_ID_INTEL,
1108 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1109 .subvendor = PCI_ANY_ID,
1110 .subdevice = PCI_ANY_ID,
1111 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1115 .vendor = PCI_VENDOR_ID_O2,
1116 .device = PCI_DEVICE_ID_O2_8120,
1117 .subvendor = PCI_ANY_ID,
1118 .subdevice = PCI_ANY_ID,
1119 .driver_data = (kernel_ulong_t)&sdhci_o2,
1123 .vendor = PCI_VENDOR_ID_O2,
1124 .device = PCI_DEVICE_ID_O2_8220,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .driver_data = (kernel_ulong_t)&sdhci_o2,
1131 .vendor = PCI_VENDOR_ID_O2,
1132 .device = PCI_DEVICE_ID_O2_8221,
1133 .subvendor = PCI_ANY_ID,
1134 .subdevice = PCI_ANY_ID,
1135 .driver_data = (kernel_ulong_t)&sdhci_o2,
1139 .vendor = PCI_VENDOR_ID_O2,
1140 .device = PCI_DEVICE_ID_O2_8320,
1141 .subvendor = PCI_ANY_ID,
1142 .subdevice = PCI_ANY_ID,
1143 .driver_data = (kernel_ulong_t)&sdhci_o2,
1147 .vendor = PCI_VENDOR_ID_O2,
1148 .device = PCI_DEVICE_ID_O2_8321,
1149 .subvendor = PCI_ANY_ID,
1150 .subdevice = PCI_ANY_ID,
1151 .driver_data = (kernel_ulong_t)&sdhci_o2,
1155 .vendor = PCI_VENDOR_ID_O2,
1156 .device = PCI_DEVICE_ID_O2_FUJIN2,
1157 .subvendor = PCI_ANY_ID,
1158 .subdevice = PCI_ANY_ID,
1159 .driver_data = (kernel_ulong_t)&sdhci_o2,
1163 .vendor = PCI_VENDOR_ID_O2,
1164 .device = PCI_DEVICE_ID_O2_SDS0,
1165 .subvendor = PCI_ANY_ID,
1166 .subdevice = PCI_ANY_ID,
1167 .driver_data = (kernel_ulong_t)&sdhci_o2,
1171 .vendor = PCI_VENDOR_ID_O2,
1172 .device = PCI_DEVICE_ID_O2_SDS1,
1173 .subvendor = PCI_ANY_ID,
1174 .subdevice = PCI_ANY_ID,
1175 .driver_data = (kernel_ulong_t)&sdhci_o2,
1179 .vendor = PCI_VENDOR_ID_O2,
1180 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1181 .subvendor = PCI_ANY_ID,
1182 .subdevice = PCI_ANY_ID,
1183 .driver_data = (kernel_ulong_t)&sdhci_o2,
1187 .vendor = PCI_VENDOR_ID_O2,
1188 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1189 .subvendor = PCI_ANY_ID,
1190 .subdevice = PCI_ANY_ID,
1191 .driver_data = (kernel_ulong_t)&sdhci_o2,
1194 .vendor = PCI_VENDOR_ID_AMD,
1195 .device = PCI_ANY_ID,
1196 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1197 .class_mask = 0xFFFF00,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .driver_data = (kernel_ulong_t)&sdhci_amd,
1202 { /* Generic SD host controller */
1203 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1206 { /* end: all zeroes */ },
1209 MODULE_DEVICE_TABLE(pci, pci_ids);
1211 /*****************************************************************************\
1213 * SDHCI core callbacks *
1215 \*****************************************************************************/
1217 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1219 struct sdhci_pci_slot *slot;
1220 struct pci_dev *pdev;
1223 slot = sdhci_priv(host);
1224 pdev = slot->chip->pdev;
1226 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1227 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1228 (host->flags & SDHCI_USE_SDMA)) {
1229 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1230 "doesn't fully claim to support it.\n");
1233 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1234 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1235 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1237 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1239 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1243 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1247 pci_set_master(pdev);
1252 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1259 case MMC_BUS_WIDTH_8:
1260 ctrl |= SDHCI_CTRL_8BITBUS;
1261 ctrl &= ~SDHCI_CTRL_4BITBUS;
1263 case MMC_BUS_WIDTH_4:
1264 ctrl |= SDHCI_CTRL_4BITBUS;
1265 ctrl &= ~SDHCI_CTRL_8BITBUS;
1268 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1275 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1277 struct sdhci_pci_slot *slot = sdhci_priv(host);
1278 int rst_n_gpio = slot->rst_n_gpio;
1280 if (!gpio_is_valid(rst_n_gpio))
1282 gpio_set_value_cansleep(rst_n_gpio, 0);
1283 /* For eMMC, minimum is 1us but give it 10us for good measure */
1285 gpio_set_value_cansleep(rst_n_gpio, 1);
1286 /* For eMMC, minimum is 200us but give it 300us for good measure */
1287 usleep_range(300, 1000);
1290 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1292 struct sdhci_pci_slot *slot = sdhci_priv(host);
1295 slot->hw_reset(host);
1298 static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1299 struct mmc_card *card,
1300 unsigned int max_dtr, int host_drv,
1301 int card_drv, int *drv_type)
1303 struct sdhci_pci_slot *slot = sdhci_priv(host);
1305 if (!slot->select_drive_strength)
1308 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1309 card_drv, drv_type);
1312 static const struct sdhci_ops sdhci_pci_ops = {
1313 .set_clock = sdhci_set_clock,
1314 .enable_dma = sdhci_pci_enable_dma,
1315 .set_bus_width = sdhci_pci_set_bus_width,
1316 .reset = sdhci_reset,
1317 .set_uhs_signaling = sdhci_set_uhs_signaling,
1318 .hw_reset = sdhci_pci_hw_reset,
1319 .select_drive_strength = sdhci_pci_select_drive_strength,
1322 /*****************************************************************************\
1326 \*****************************************************************************/
1330 static int sdhci_pci_suspend(struct device *dev)
1332 struct pci_dev *pdev = to_pci_dev(dev);
1333 struct sdhci_pci_chip *chip;
1334 struct sdhci_pci_slot *slot;
1335 mmc_pm_flag_t slot_pm_flags;
1336 mmc_pm_flag_t pm_flags = 0;
1339 chip = pci_get_drvdata(pdev);
1343 for (i = 0; i < chip->num_slots; i++) {
1344 slot = chip->slots[i];
1348 ret = sdhci_suspend_host(slot->host);
1351 goto err_pci_suspend;
1353 slot_pm_flags = slot->host->mmc->pm_flags;
1354 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1355 sdhci_enable_irq_wakeups(slot->host);
1357 pm_flags |= slot_pm_flags;
1360 if (chip->fixes && chip->fixes->suspend) {
1361 ret = chip->fixes->suspend(chip);
1363 goto err_pci_suspend;
1366 if (pm_flags & MMC_PM_KEEP_POWER) {
1367 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1368 device_init_wakeup(dev, true);
1370 device_init_wakeup(dev, false);
1372 device_init_wakeup(dev, false);
1378 sdhci_resume_host(chip->slots[i]->host);
1382 static int sdhci_pci_resume(struct device *dev)
1384 struct pci_dev *pdev = to_pci_dev(dev);
1385 struct sdhci_pci_chip *chip;
1386 struct sdhci_pci_slot *slot;
1389 chip = pci_get_drvdata(pdev);
1393 if (chip->fixes && chip->fixes->resume) {
1394 ret = chip->fixes->resume(chip);
1399 for (i = 0; i < chip->num_slots; i++) {
1400 slot = chip->slots[i];
1404 ret = sdhci_resume_host(slot->host);
1412 static int sdhci_pci_runtime_suspend(struct device *dev)
1414 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1415 struct sdhci_pci_chip *chip;
1416 struct sdhci_pci_slot *slot;
1419 chip = pci_get_drvdata(pdev);
1423 for (i = 0; i < chip->num_slots; i++) {
1424 slot = chip->slots[i];
1428 ret = sdhci_runtime_suspend_host(slot->host);
1431 goto err_pci_runtime_suspend;
1434 if (chip->fixes && chip->fixes->suspend) {
1435 ret = chip->fixes->suspend(chip);
1437 goto err_pci_runtime_suspend;
1442 err_pci_runtime_suspend:
1444 sdhci_runtime_resume_host(chip->slots[i]->host);
1448 static int sdhci_pci_runtime_resume(struct device *dev)
1450 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1451 struct sdhci_pci_chip *chip;
1452 struct sdhci_pci_slot *slot;
1455 chip = pci_get_drvdata(pdev);
1459 if (chip->fixes && chip->fixes->resume) {
1460 ret = chip->fixes->resume(chip);
1465 for (i = 0; i < chip->num_slots; i++) {
1466 slot = chip->slots[i];
1470 ret = sdhci_runtime_resume_host(slot->host);
1478 #else /* CONFIG_PM */
1480 #define sdhci_pci_suspend NULL
1481 #define sdhci_pci_resume NULL
1483 #endif /* CONFIG_PM */
1485 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1486 .suspend = sdhci_pci_suspend,
1487 .resume = sdhci_pci_resume,
1488 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1489 sdhci_pci_runtime_resume, NULL)
1492 /*****************************************************************************\
1494 * Device probing/removal *
1496 \*****************************************************************************/
1498 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1499 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1502 struct sdhci_pci_slot *slot;
1503 struct sdhci_host *host;
1504 int ret, bar = first_bar + slotno;
1506 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1507 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1508 return ERR_PTR(-ENODEV);
1511 if (pci_resource_len(pdev, bar) < 0x100) {
1512 dev_err(&pdev->dev, "Invalid iomem size. You may "
1513 "experience problems.\n");
1516 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1517 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1518 return ERR_PTR(-ENODEV);
1521 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1522 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1523 return ERR_PTR(-ENODEV);
1526 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1528 dev_err(&pdev->dev, "cannot allocate host\n");
1529 return ERR_CAST(host);
1532 slot = sdhci_priv(host);
1536 slot->pci_bar = bar;
1537 slot->rst_n_gpio = -EINVAL;
1538 slot->cd_gpio = -EINVAL;
1541 /* Retrieve platform data if there is any */
1542 if (*sdhci_pci_get_data)
1543 slot->data = sdhci_pci_get_data(pdev, slotno);
1546 if (slot->data->setup) {
1547 ret = slot->data->setup(slot->data);
1549 dev_err(&pdev->dev, "platform setup failed\n");
1553 slot->rst_n_gpio = slot->data->rst_n_gpio;
1554 slot->cd_gpio = slot->data->cd_gpio;
1557 host->hw_name = "PCI";
1558 host->ops = &sdhci_pci_ops;
1559 host->quirks = chip->quirks;
1560 host->quirks2 = chip->quirks2;
1562 host->irq = pdev->irq;
1564 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1566 dev_err(&pdev->dev, "cannot request region\n");
1570 host->ioaddr = pci_ioremap_bar(pdev, bar);
1571 if (!host->ioaddr) {
1572 dev_err(&pdev->dev, "failed to remap registers\n");
1577 if (chip->fixes && chip->fixes->probe_slot) {
1578 ret = chip->fixes->probe_slot(slot);
1583 if (gpio_is_valid(slot->rst_n_gpio)) {
1584 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1585 gpio_direction_output(slot->rst_n_gpio, 1);
1586 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1587 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1589 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1590 slot->rst_n_gpio = -EINVAL;
1594 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1595 host->mmc->slotno = slotno;
1596 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1598 if (slot->cd_idx >= 0 &&
1599 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1600 slot->cd_override_level, 0, NULL)) {
1601 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1605 ret = sdhci_add_host(host);
1609 sdhci_pci_add_own_cd(slot);
1612 * Check if the chip needs a separate GPIO for card detect to wake up
1613 * from runtime suspend. If it is not there, don't allow runtime PM.
1614 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1616 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1617 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1618 chip->allow_runtime_pm = false;
1623 if (gpio_is_valid(slot->rst_n_gpio))
1624 gpio_free(slot->rst_n_gpio);
1626 if (chip->fixes && chip->fixes->remove_slot)
1627 chip->fixes->remove_slot(slot, 0);
1630 iounmap(host->ioaddr);
1633 pci_release_region(pdev, bar);
1636 if (slot->data && slot->data->cleanup)
1637 slot->data->cleanup(slot->data);
1640 sdhci_free_host(host);
1642 return ERR_PTR(ret);
1645 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1650 sdhci_pci_remove_own_cd(slot);
1653 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1654 if (scratch == (u32)-1)
1657 sdhci_remove_host(slot->host, dead);
1659 if (gpio_is_valid(slot->rst_n_gpio))
1660 gpio_free(slot->rst_n_gpio);
1662 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1663 slot->chip->fixes->remove_slot(slot, dead);
1665 if (slot->data && slot->data->cleanup)
1666 slot->data->cleanup(slot->data);
1668 pci_release_region(slot->chip->pdev, slot->pci_bar);
1670 sdhci_free_host(slot->host);
1673 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1675 pm_runtime_put_noidle(dev);
1676 pm_runtime_allow(dev);
1677 pm_runtime_set_autosuspend_delay(dev, 50);
1678 pm_runtime_use_autosuspend(dev);
1679 pm_suspend_ignore_children(dev, 1);
1682 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1684 pm_runtime_forbid(dev);
1685 pm_runtime_get_noresume(dev);
1688 static int sdhci_pci_probe(struct pci_dev *pdev,
1689 const struct pci_device_id *ent)
1691 struct sdhci_pci_chip *chip;
1692 struct sdhci_pci_slot *slot;
1694 u8 slots, first_bar;
1697 BUG_ON(pdev == NULL);
1698 BUG_ON(ent == NULL);
1700 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1701 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1703 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1707 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1708 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1712 BUG_ON(slots > MAX_SLOTS);
1714 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1718 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1720 if (first_bar > 5) {
1721 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1725 ret = pci_enable_device(pdev);
1729 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1736 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1738 chip->quirks = chip->fixes->quirks;
1739 chip->quirks2 = chip->fixes->quirks2;
1740 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1742 chip->num_slots = slots;
1744 pci_set_drvdata(pdev, chip);
1746 if (chip->fixes && chip->fixes->probe) {
1747 ret = chip->fixes->probe(chip);
1752 slots = chip->num_slots; /* Quirk may have changed this */
1754 for (i = 0; i < slots; i++) {
1755 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1757 for (i--; i >= 0; i--)
1758 sdhci_pci_remove_slot(chip->slots[i]);
1759 ret = PTR_ERR(slot);
1763 chip->slots[i] = slot;
1766 if (chip->allow_runtime_pm)
1767 sdhci_pci_runtime_pm_allow(&pdev->dev);
1772 pci_set_drvdata(pdev, NULL);
1776 pci_disable_device(pdev);
1780 static void sdhci_pci_remove(struct pci_dev *pdev)
1783 struct sdhci_pci_chip *chip;
1785 chip = pci_get_drvdata(pdev);
1788 if (chip->allow_runtime_pm)
1789 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1791 for (i = 0; i < chip->num_slots; i++)
1792 sdhci_pci_remove_slot(chip->slots[i]);
1794 pci_set_drvdata(pdev, NULL);
1798 pci_disable_device(pdev);
1801 static struct pci_driver sdhci_driver = {
1802 .name = "sdhci-pci",
1803 .id_table = pci_ids,
1804 .probe = sdhci_pci_probe,
1805 .remove = sdhci_pci_remove,
1807 .pm = &sdhci_pci_pm_ops
1811 module_pci_driver(sdhci_driver);
1813 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1814 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1815 MODULE_LICENSE("GPL");