1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_gpio.h>
27 #include <linux/mmc/host.h>
29 #include <plat/sdhci.h>
30 #include <plat/regs-sdhci.h>
34 #define MAX_BUS_CLK (4)
37 * struct sdhci_s3c - S3C SDHCI instance
38 * @host: The SDHCI host created
39 * @pdev: The platform device we where created from.
40 * @ioarea: The resource created when we claimed the IO area.
41 * @pdata: The platform data for this controller.
42 * @cur_clk: The index of the current bus clock.
43 * @clk_io: The clock for the internal bus interface.
44 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
47 struct sdhci_host *host;
48 struct platform_device *pdev;
49 struct resource *ioarea;
50 struct s3c_sdhci_platdata *pdata;
56 struct clk *clk_bus[MAX_BUS_CLK];
60 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
61 * @sdhci_quirks: sdhci host specific quirks.
63 * Specifies platform specific configuration of sdhci controller.
64 * Note: A structure for driver specific platform data is used for future
65 * expansion of its usage.
67 struct sdhci_s3c_drv_data {
68 unsigned int sdhci_quirks;
71 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
73 return sdhci_priv(host);
77 * get_curclk - convert ctrl2 register to clock source number
78 * @ctrl2: Control2 register value.
80 static u32 get_curclk(u32 ctrl2)
82 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
83 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
88 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
90 struct sdhci_s3c *ourhost = to_s3c(host);
91 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
93 if (get_curclk(tmp) != ourhost->cur_clk) {
94 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
96 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
97 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
98 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
103 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
104 * @host: The SDHCI host instance.
106 * Callback to return the maximum clock rate acheivable by the controller.
108 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
110 struct sdhci_s3c *ourhost = to_s3c(host);
112 unsigned int rate, max;
115 /* note, a reset will reset the clock source */
117 sdhci_s3c_check_sclk(host);
119 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
120 busclk = ourhost->clk_bus[clk];
124 rate = clk_get_rate(busclk);
133 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
134 * @ourhost: Our SDHCI instance.
135 * @src: The source clock index.
136 * @wanted: The clock frequency wanted.
138 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
143 struct clk *clksrc = ourhost->clk_bus[src];
150 * If controller uses a non-standard clock division, find the best clock
151 * speed possible with selected clock source and skip the division.
153 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
154 rate = clk_round_rate(clksrc, wanted);
155 return wanted - rate;
158 rate = clk_get_rate(clksrc);
160 for (div = 1; div < 256; div *= 2) {
161 if ((rate / div) <= wanted)
165 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
166 src, rate, wanted, rate / div);
168 return (wanted - (rate / div));
172 * sdhci_s3c_set_clock - callback on clock change
173 * @host: The SDHCI host being changed
174 * @clock: The clock rate being requested.
176 * When the card's clock is going to be changed, look at the new frequency
177 * and find the best clock source to go with it.
179 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
181 struct sdhci_s3c *ourhost = to_s3c(host);
182 unsigned int best = UINT_MAX;
188 /* don't bother if the clock is going off. */
192 for (src = 0; src < MAX_BUS_CLK; src++) {
193 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
200 dev_dbg(&ourhost->pdev->dev,
201 "selected source %d, clock %d, delta %d\n",
202 best_src, clock, best);
204 /* select the new clock source */
206 if (ourhost->cur_clk != best_src) {
207 struct clk *clk = ourhost->clk_bus[best_src];
209 /* turn clock off to card before changing clock source */
210 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
212 ourhost->cur_clk = best_src;
213 host->max_clk = clk_get_rate(clk);
215 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
216 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
217 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
218 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
221 /* reprogram default hardware configuration */
222 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
223 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
225 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
226 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
227 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
228 S3C_SDHCI_CTRL2_ENFBCLKRX |
229 S3C_SDHCI_CTRL2_DFCNT_NONE |
230 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
231 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
233 /* reconfigure the controller for new clock rate */
234 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
235 if (clock < 25 * 1000000)
236 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
237 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
241 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
242 * @host: The SDHCI host being queried
244 * To init mmc host properly a minimal clock value is needed. For high system
245 * bus clock's values the standard formula gives values out of allowed range.
246 * The clock still can be set to lower values, if clock source other then
247 * system bus is selected.
249 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
251 struct sdhci_s3c *ourhost = to_s3c(host);
252 unsigned int delta, min = UINT_MAX;
255 for (src = 0; src < MAX_BUS_CLK; src++) {
256 delta = sdhci_s3c_consider_clock(ourhost, src, 0);
257 if (delta == UINT_MAX)
259 /* delta is a negative value in this case */
266 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
267 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
269 struct sdhci_s3c *ourhost = to_s3c(host);
271 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
274 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
275 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
277 struct sdhci_s3c *ourhost = to_s3c(host);
280 * initial clock can be in the frequency range of
281 * 100KHz-400KHz, so we set it as max value.
283 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
286 /* sdhci_cmu_set_clock - callback on clock change.*/
287 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
289 struct sdhci_s3c *ourhost = to_s3c(host);
290 unsigned long timeout;
293 /* don't bother if the clock is going off */
297 sdhci_s3c_set_clock(host, clock);
299 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
303 clk = SDHCI_CLOCK_INT_EN;
304 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
308 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
309 & SDHCI_CLOCK_INT_STABLE)) {
311 printk(KERN_ERR "%s: Internal clock never "
312 "stabilised.\n", mmc_hostname(host->mmc));
319 clk |= SDHCI_CLOCK_CARD_EN;
320 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
324 * sdhci_s3c_platform_8bit_width - support 8bit buswidth
325 * @host: The SDHCI host being queried
326 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
328 * We have 8-bit width support but is not a v3 controller.
329 * So we add platform_8bit_width() and support 8bit width.
331 static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
335 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
338 case MMC_BUS_WIDTH_8:
339 ctrl |= SDHCI_CTRL_8BITBUS;
340 ctrl &= ~SDHCI_CTRL_4BITBUS;
342 case MMC_BUS_WIDTH_4:
343 ctrl |= SDHCI_CTRL_4BITBUS;
344 ctrl &= ~SDHCI_CTRL_8BITBUS;
347 ctrl &= ~SDHCI_CTRL_4BITBUS;
348 ctrl &= ~SDHCI_CTRL_8BITBUS;
352 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
357 static struct sdhci_ops sdhci_s3c_ops = {
358 .get_max_clock = sdhci_s3c_get_max_clk,
359 .set_clock = sdhci_s3c_set_clock,
360 .get_min_clock = sdhci_s3c_get_min_clock,
361 .platform_8bit_width = sdhci_s3c_platform_8bit_width,
364 static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
366 struct sdhci_host *host = platform_get_drvdata(dev);
370 spin_lock_irqsave(&host->lock, flags);
372 dev_dbg(&dev->dev, "card inserted.\n");
373 host->flags &= ~SDHCI_DEVICE_DEAD;
374 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
376 dev_dbg(&dev->dev, "card removed.\n");
377 host->flags |= SDHCI_DEVICE_DEAD;
378 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
380 tasklet_schedule(&host->card_tasklet);
381 spin_unlock_irqrestore(&host->lock, flags);
385 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
387 struct sdhci_s3c *sc = dev_id;
388 int status = gpio_get_value(sc->ext_cd_gpio);
389 if (sc->pdata->ext_cd_gpio_invert)
391 sdhci_s3c_notify_change(sc->pdev, status);
395 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
397 struct s3c_sdhci_platdata *pdata = sc->pdata;
398 struct device *dev = &sc->pdev->dev;
400 if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
401 sc->ext_cd_gpio = pdata->ext_cd_gpio;
402 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
403 if (sc->ext_cd_irq &&
404 request_threaded_irq(sc->ext_cd_irq, NULL,
405 sdhci_s3c_gpio_card_detect_thread,
406 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
407 dev_name(dev), sc) == 0) {
408 int status = gpio_get_value(sc->ext_cd_gpio);
409 if (pdata->ext_cd_gpio_invert)
411 sdhci_s3c_notify_change(sc->pdev, status);
413 dev_warn(dev, "cannot request irq for card detect\n");
417 dev_err(dev, "cannot request gpio for card detect\n");
421 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
422 struct platform_device *pdev)
424 return (struct sdhci_s3c_drv_data *)
425 platform_get_device_id(pdev)->driver_data;
428 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
430 struct s3c_sdhci_platdata *pdata;
431 struct sdhci_s3c_drv_data *drv_data;
432 struct device *dev = &pdev->dev;
433 struct sdhci_host *host;
434 struct sdhci_s3c *sc;
435 struct resource *res;
436 int ret, irq, ptr, clks;
438 if (!pdev->dev.platform_data) {
439 dev_err(dev, "no device data specified\n");
443 irq = platform_get_irq(pdev, 0);
445 dev_err(dev, "no irq specified\n");
449 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
451 dev_err(dev, "sdhci_alloc_host() failed\n");
452 return PTR_ERR(host);
455 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
460 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
462 drv_data = sdhci_s3c_get_driver_data(pdev);
463 sc = sdhci_priv(host);
468 sc->ext_cd_gpio = -1; /* invalid gpio number */
470 platform_set_drvdata(pdev, host);
472 sc->clk_io = clk_get(dev, "hsmmc");
473 if (IS_ERR(sc->clk_io)) {
474 dev_err(dev, "failed to get io clock\n");
475 ret = PTR_ERR(sc->clk_io);
479 /* enable the local io clock and keep it running for the moment. */
480 clk_enable(sc->clk_io);
482 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
486 snprintf(name, 14, "mmc_busclk.%d", ptr);
487 clk = clk_get(dev, name);
493 sc->clk_bus[ptr] = clk;
496 * save current clock index to know which clock bus
497 * is used later in overriding functions.
503 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
504 ptr, name, clk_get_rate(clk));
508 dev_err(dev, "failed to find any bus clocks\n");
513 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
514 host->ioaddr = devm_request_and_ioremap(&pdev->dev, res);
516 dev_err(dev, "failed to map registers\n");
521 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
523 pdata->cfg_gpio(pdev, pdata->max_width);
525 host->hw_name = "samsung-hsmmc";
526 host->ops = &sdhci_s3c_ops;
530 /* Setup quirks for the controller */
531 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
532 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
534 host->quirks |= drv_data->sdhci_quirks;
536 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
538 /* we currently see overruns on errors, so disable the SDMA
539 * support as well. */
540 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
542 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
544 /* It seems we do not get an DATA transfer complete on non-busy
545 * transfers, not sure if this is a problem with this specific
546 * SDHCI block, or a missing configuration that needs to be set. */
547 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
549 /* This host supports the Auto CMD12 */
550 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
552 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
553 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
555 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
556 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
557 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
559 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
560 host->mmc->caps = MMC_CAP_NONREMOVABLE;
562 switch (pdata->max_width) {
564 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
566 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
571 host->mmc->pm_caps |= pdata->pm_caps;
573 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
574 SDHCI_QUIRK_32BIT_DMA_SIZE);
576 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
577 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
580 * If controller does not have internal clock divider,
581 * we can use overriding functions instead of default.
583 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
584 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
585 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
586 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
589 /* It supports additional host capabilities if needed */
590 if (pdata->host_caps)
591 host->mmc->caps |= pdata->host_caps;
593 if (pdata->host_caps2)
594 host->mmc->caps2 |= pdata->host_caps2;
596 ret = sdhci_add_host(host);
598 dev_err(dev, "sdhci_add_host() failed\n");
602 /* The following two methods of card detection might call
603 sdhci_s3c_notify_change() immediately, so they can be called
604 only after sdhci_add_host(). Setup errors are ignored. */
605 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
606 pdata->ext_cd_init(&sdhci_s3c_notify_change);
607 if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
608 gpio_is_valid(pdata->ext_cd_gpio))
609 sdhci_s3c_setup_card_detect_gpio(sc);
614 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
615 if (sc->clk_bus[ptr]) {
616 clk_disable(sc->clk_bus[ptr]);
617 clk_put(sc->clk_bus[ptr]);
622 clk_disable(sc->clk_io);
626 sdhci_free_host(host);
631 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
633 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
634 struct sdhci_host *host = platform_get_drvdata(pdev);
635 struct sdhci_s3c *sc = sdhci_priv(host);
638 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
639 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
642 free_irq(sc->ext_cd_irq, sc);
644 if (gpio_is_valid(sc->ext_cd_gpio))
645 gpio_free(sc->ext_cd_gpio);
647 sdhci_remove_host(host, 1);
649 for (ptr = 0; ptr < 3; ptr++) {
650 if (sc->clk_bus[ptr]) {
651 clk_disable(sc->clk_bus[ptr]);
652 clk_put(sc->clk_bus[ptr]);
655 clk_disable(sc->clk_io);
658 sdhci_free_host(host);
659 platform_set_drvdata(pdev, NULL);
664 #ifdef CONFIG_PM_SLEEP
665 static int sdhci_s3c_suspend(struct device *dev)
667 struct sdhci_host *host = dev_get_drvdata(dev);
669 return sdhci_suspend_host(host);
672 static int sdhci_s3c_resume(struct device *dev)
674 struct sdhci_host *host = dev_get_drvdata(dev);
676 return sdhci_resume_host(host);
681 static const struct dev_pm_ops sdhci_s3c_pmops = {
682 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
685 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
688 #define SDHCI_S3C_PMOPS NULL
691 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
692 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
693 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
695 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
697 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
700 static struct platform_device_id sdhci_s3c_driver_ids[] = {
703 .driver_data = (kernel_ulong_t)NULL,
705 .name = "exynos4-sdhci",
706 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
710 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
712 static struct platform_driver sdhci_s3c_driver = {
713 .probe = sdhci_s3c_probe,
714 .remove = __devexit_p(sdhci_s3c_remove),
715 .id_table = sdhci_s3c_driver_ids,
717 .owner = THIS_MODULE,
719 .pm = SDHCI_S3C_PMOPS,
723 module_platform_driver(sdhci_s3c_driver);
725 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
726 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
727 MODULE_LICENSE("GPL v2");
728 MODULE_ALIAS("platform:s3c-sdhci");