1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
24 #include <linux/mmc/host.h>
26 #include <plat/sdhci.h>
27 #include <plat/regs-sdhci.h>
31 #define MAX_BUS_CLK (4)
34 * struct sdhci_s3c - S3C SDHCI instance
35 * @host: The SDHCI host created
36 * @pdev: The platform device we where created from.
37 * @ioarea: The resource created when we claimed the IO area.
38 * @pdata: The platform data for this controller.
39 * @cur_clk: The index of the current bus clock.
40 * @clk_io: The clock for the internal bus interface.
41 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
44 struct sdhci_host *host;
45 struct platform_device *pdev;
46 struct resource *ioarea;
47 struct s3c_sdhci_platdata *pdata;
53 struct clk *clk_bus[MAX_BUS_CLK];
57 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
58 * @sdhci_quirks: sdhci host specific quirks.
60 * Specifies platform specific configuration of sdhci controller.
61 * Note: A structure for driver specific platform data is used for future
62 * expansion of its usage.
64 struct sdhci_s3c_drv_data {
65 unsigned int sdhci_quirks;
68 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
70 return sdhci_priv(host);
74 * get_curclk - convert ctrl2 register to clock source number
75 * @ctrl2: Control2 register value.
77 static u32 get_curclk(u32 ctrl2)
79 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
80 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
85 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
87 struct sdhci_s3c *ourhost = to_s3c(host);
88 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
90 if (get_curclk(tmp) != ourhost->cur_clk) {
91 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
93 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
94 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
95 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
100 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
101 * @host: The SDHCI host instance.
103 * Callback to return the maximum clock rate acheivable by the controller.
105 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
107 struct sdhci_s3c *ourhost = to_s3c(host);
109 unsigned int rate, max;
112 /* note, a reset will reset the clock source */
114 sdhci_s3c_check_sclk(host);
116 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
117 busclk = ourhost->clk_bus[clk];
121 rate = clk_get_rate(busclk);
130 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
131 * @ourhost: Our SDHCI instance.
132 * @src: The source clock index.
133 * @wanted: The clock frequency wanted.
135 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
140 struct clk *clksrc = ourhost->clk_bus[src];
147 * If controller uses a non-standard clock division, find the best clock
148 * speed possible with selected clock source and skip the division.
150 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
151 rate = clk_round_rate(clksrc, wanted);
152 return wanted - rate;
155 rate = clk_get_rate(clksrc);
157 for (div = 1; div < 256; div *= 2) {
158 if ((rate / div) <= wanted)
162 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
163 src, rate, wanted, rate / div);
165 return (wanted - (rate / div));
169 * sdhci_s3c_set_clock - callback on clock change
170 * @host: The SDHCI host being changed
171 * @clock: The clock rate being requested.
173 * When the card's clock is going to be changed, look at the new frequency
174 * and find the best clock source to go with it.
176 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
178 struct sdhci_s3c *ourhost = to_s3c(host);
179 unsigned int best = UINT_MAX;
185 /* don't bother if the clock is going off. */
189 for (src = 0; src < MAX_BUS_CLK; src++) {
190 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
197 dev_dbg(&ourhost->pdev->dev,
198 "selected source %d, clock %d, delta %d\n",
199 best_src, clock, best);
201 /* select the new clock source */
203 if (ourhost->cur_clk != best_src) {
204 struct clk *clk = ourhost->clk_bus[best_src];
206 /* turn clock off to card before changing clock source */
207 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
209 ourhost->cur_clk = best_src;
210 host->max_clk = clk_get_rate(clk);
212 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
213 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
214 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
215 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
218 /* reprogram default hardware configuration */
219 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
220 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
222 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
223 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
224 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
225 S3C_SDHCI_CTRL2_ENFBCLKRX |
226 S3C_SDHCI_CTRL2_DFCNT_NONE |
227 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
228 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
230 /* reconfigure the controller for new clock rate */
231 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
232 if (clock < 25 * 1000000)
233 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
234 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
238 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
239 * @host: The SDHCI host being queried
241 * To init mmc host properly a minimal clock value is needed. For high system
242 * bus clock's values the standard formula gives values out of allowed range.
243 * The clock still can be set to lower values, if clock source other then
244 * system bus is selected.
246 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
248 struct sdhci_s3c *ourhost = to_s3c(host);
249 unsigned int delta, min = UINT_MAX;
252 for (src = 0; src < MAX_BUS_CLK; src++) {
253 delta = sdhci_s3c_consider_clock(ourhost, src, 0);
254 if (delta == UINT_MAX)
256 /* delta is a negative value in this case */
263 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
264 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
266 struct sdhci_s3c *ourhost = to_s3c(host);
268 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
271 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
272 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
274 struct sdhci_s3c *ourhost = to_s3c(host);
277 * initial clock can be in the frequency range of
278 * 100KHz-400KHz, so we set it as max value.
280 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
283 /* sdhci_cmu_set_clock - callback on clock change.*/
284 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
286 struct sdhci_s3c *ourhost = to_s3c(host);
287 unsigned long timeout;
290 /* don't bother if the clock is going off */
294 sdhci_s3c_set_clock(host, clock);
296 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
300 clk = SDHCI_CLOCK_INT_EN;
301 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
305 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
306 & SDHCI_CLOCK_INT_STABLE)) {
308 printk(KERN_ERR "%s: Internal clock never "
309 "stabilised.\n", mmc_hostname(host->mmc));
316 clk |= SDHCI_CLOCK_CARD_EN;
317 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
321 * sdhci_s3c_platform_8bit_width - support 8bit buswidth
322 * @host: The SDHCI host being queried
323 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
325 * We have 8-bit width support but is not a v3 controller.
326 * So we add platform_8bit_width() and support 8bit width.
328 static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
332 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
335 case MMC_BUS_WIDTH_8:
336 ctrl |= SDHCI_CTRL_8BITBUS;
337 ctrl &= ~SDHCI_CTRL_4BITBUS;
339 case MMC_BUS_WIDTH_4:
340 ctrl |= SDHCI_CTRL_4BITBUS;
341 ctrl &= ~SDHCI_CTRL_8BITBUS;
344 ctrl &= ~SDHCI_CTRL_4BITBUS;
345 ctrl &= ~SDHCI_CTRL_8BITBUS;
349 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
354 static struct sdhci_ops sdhci_s3c_ops = {
355 .get_max_clock = sdhci_s3c_get_max_clk,
356 .set_clock = sdhci_s3c_set_clock,
357 .get_min_clock = sdhci_s3c_get_min_clock,
358 .platform_8bit_width = sdhci_s3c_platform_8bit_width,
361 static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
363 struct sdhci_host *host = platform_get_drvdata(dev);
367 spin_lock_irqsave(&host->lock, flags);
369 dev_dbg(&dev->dev, "card inserted.\n");
370 host->flags &= ~SDHCI_DEVICE_DEAD;
371 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
373 dev_dbg(&dev->dev, "card removed.\n");
374 host->flags |= SDHCI_DEVICE_DEAD;
375 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
377 tasklet_schedule(&host->card_tasklet);
378 spin_unlock_irqrestore(&host->lock, flags);
382 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
384 struct sdhci_s3c *sc = dev_id;
385 int status = gpio_get_value(sc->ext_cd_gpio);
386 if (sc->pdata->ext_cd_gpio_invert)
388 sdhci_s3c_notify_change(sc->pdev, status);
392 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
394 struct s3c_sdhci_platdata *pdata = sc->pdata;
395 struct device *dev = &sc->pdev->dev;
397 if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
398 sc->ext_cd_gpio = pdata->ext_cd_gpio;
399 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
400 if (sc->ext_cd_irq &&
401 request_threaded_irq(sc->ext_cd_irq, NULL,
402 sdhci_s3c_gpio_card_detect_thread,
403 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
404 dev_name(dev), sc) == 0) {
405 int status = gpio_get_value(sc->ext_cd_gpio);
406 if (pdata->ext_cd_gpio_invert)
408 sdhci_s3c_notify_change(sc->pdev, status);
410 dev_warn(dev, "cannot request irq for card detect\n");
414 dev_err(dev, "cannot request gpio for card detect\n");
418 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
419 struct platform_device *pdev)
421 return (struct sdhci_s3c_drv_data *)
422 platform_get_device_id(pdev)->driver_data;
425 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
427 struct s3c_sdhci_platdata *pdata;
428 struct sdhci_s3c_drv_data *drv_data;
429 struct device *dev = &pdev->dev;
430 struct sdhci_host *host;
431 struct sdhci_s3c *sc;
432 struct resource *res;
433 int ret, irq, ptr, clks;
435 if (!pdev->dev.platform_data) {
436 dev_err(dev, "no device data specified\n");
440 irq = platform_get_irq(pdev, 0);
442 dev_err(dev, "no irq specified\n");
446 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
448 dev_err(dev, "sdhci_alloc_host() failed\n");
449 return PTR_ERR(host);
452 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
457 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
459 drv_data = sdhci_s3c_get_driver_data(pdev);
460 sc = sdhci_priv(host);
465 sc->ext_cd_gpio = -1; /* invalid gpio number */
467 platform_set_drvdata(pdev, host);
469 sc->clk_io = clk_get(dev, "hsmmc");
470 if (IS_ERR(sc->clk_io)) {
471 dev_err(dev, "failed to get io clock\n");
472 ret = PTR_ERR(sc->clk_io);
476 /* enable the local io clock and keep it running for the moment. */
477 clk_enable(sc->clk_io);
479 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
483 snprintf(name, 14, "mmc_busclk.%d", ptr);
484 clk = clk_get(dev, name);
490 sc->clk_bus[ptr] = clk;
493 * save current clock index to know which clock bus
494 * is used later in overriding functions.
500 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
501 ptr, name, clk_get_rate(clk));
505 dev_err(dev, "failed to find any bus clocks\n");
510 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
511 host->ioaddr = devm_request_and_ioremap(&pdev->dev, res);
513 dev_err(dev, "failed to map registers\n");
518 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
520 pdata->cfg_gpio(pdev, pdata->max_width);
522 host->hw_name = "samsung-hsmmc";
523 host->ops = &sdhci_s3c_ops;
527 /* Setup quirks for the controller */
528 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
529 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
531 host->quirks |= drv_data->sdhci_quirks;
533 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
535 /* we currently see overruns on errors, so disable the SDMA
536 * support as well. */
537 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
539 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
541 /* It seems we do not get an DATA transfer complete on non-busy
542 * transfers, not sure if this is a problem with this specific
543 * SDHCI block, or a missing configuration that needs to be set. */
544 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
546 /* This host supports the Auto CMD12 */
547 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
549 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
550 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
552 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
553 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
554 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
556 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
557 host->mmc->caps = MMC_CAP_NONREMOVABLE;
559 switch (pdata->max_width) {
561 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
563 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
568 host->mmc->pm_caps |= pdata->pm_caps;
570 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
571 SDHCI_QUIRK_32BIT_DMA_SIZE);
573 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
574 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
577 * If controller does not have internal clock divider,
578 * we can use overriding functions instead of default.
580 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
581 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
582 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
583 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
586 /* It supports additional host capabilities if needed */
587 if (pdata->host_caps)
588 host->mmc->caps |= pdata->host_caps;
590 if (pdata->host_caps2)
591 host->mmc->caps2 |= pdata->host_caps2;
593 ret = sdhci_add_host(host);
595 dev_err(dev, "sdhci_add_host() failed\n");
599 /* The following two methods of card detection might call
600 sdhci_s3c_notify_change() immediately, so they can be called
601 only after sdhci_add_host(). Setup errors are ignored. */
602 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
603 pdata->ext_cd_init(&sdhci_s3c_notify_change);
604 if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
605 gpio_is_valid(pdata->ext_cd_gpio))
606 sdhci_s3c_setup_card_detect_gpio(sc);
611 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
612 if (sc->clk_bus[ptr]) {
613 clk_disable(sc->clk_bus[ptr]);
614 clk_put(sc->clk_bus[ptr]);
619 clk_disable(sc->clk_io);
623 sdhci_free_host(host);
628 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
630 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
631 struct sdhci_host *host = platform_get_drvdata(pdev);
632 struct sdhci_s3c *sc = sdhci_priv(host);
635 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
636 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
639 free_irq(sc->ext_cd_irq, sc);
641 if (gpio_is_valid(sc->ext_cd_gpio))
642 gpio_free(sc->ext_cd_gpio);
644 sdhci_remove_host(host, 1);
646 for (ptr = 0; ptr < 3; ptr++) {
647 if (sc->clk_bus[ptr]) {
648 clk_disable(sc->clk_bus[ptr]);
649 clk_put(sc->clk_bus[ptr]);
652 clk_disable(sc->clk_io);
655 sdhci_free_host(host);
656 platform_set_drvdata(pdev, NULL);
663 static int sdhci_s3c_suspend(struct device *dev)
665 struct sdhci_host *host = dev_get_drvdata(dev);
667 return sdhci_suspend_host(host);
670 static int sdhci_s3c_resume(struct device *dev)
672 struct sdhci_host *host = dev_get_drvdata(dev);
674 return sdhci_resume_host(host);
677 static const struct dev_pm_ops sdhci_s3c_pmops = {
678 .suspend = sdhci_s3c_suspend,
679 .resume = sdhci_s3c_resume,
682 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
685 #define SDHCI_S3C_PMOPS NULL
688 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
689 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
690 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
692 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
694 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
697 static struct platform_device_id sdhci_s3c_driver_ids[] = {
700 .driver_data = (kernel_ulong_t)NULL,
702 .name = "exynos4-sdhci",
703 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
707 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
709 static struct platform_driver sdhci_s3c_driver = {
710 .probe = sdhci_s3c_probe,
711 .remove = __devexit_p(sdhci_s3c_remove),
712 .id_table = sdhci_s3c_driver_ids,
714 .owner = THIS_MODULE,
716 .pm = SDHCI_S3C_PMOPS,
720 module_platform_driver(sdhci_s3c_driver);
722 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
723 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
724 MODULE_LICENSE("GPL v2");
725 MODULE_ALIAS("platform:s3c-sdhci");