2 * SDHCI support for SiRF primaII and marco SoCs
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/mmc/host.h>
12 #include <linux/module.h>
14 #include <linux/of_gpio.h>
15 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
18 #define SDHCI_CLK_DELAY_SETTING 0x4C
19 #define SDHCI_SIRF_8BITBUS BIT(3)
20 #define SIRF_TUNING_COUNT 16384
22 struct sdhci_sirf_priv {
26 static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
30 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
31 ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS);
34 * CSR atlas7 and prima2 SD host version is not 3.0
35 * 8bit-width enable bit of CSR SD hosts is 3,
36 * while stardard hosts use bit 5
38 if (width == MMC_BUS_WIDTH_8)
39 ctrl |= SDHCI_SIRF_8BITBUS;
40 else if (width == MMC_BUS_WIDTH_4)
41 ctrl |= SDHCI_CTRL_4BITBUS;
43 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
46 static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
48 u32 val = readl(host->ioaddr + reg);
50 if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
51 (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
52 /* fake CAP_1 register */
53 val = SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
56 if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
58 /* fake chips as V3.0 host conreoller */
59 prss &= ~(0xFF << 16);
60 val = prss | (SDHCI_SPEC_300 << 16);
65 static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
69 ret = readw(host->ioaddr + reg);
71 if (unlikely(reg == SDHCI_HOST_VERSION)) {
72 ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
73 ret |= SDHCI_SPEC_300;
79 static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
81 int tuning_seq_cnt = 3;
83 u8 tuned_phase_cnt = 0;
84 int rc = 0, longest_range = 0;
85 int start = -1, end = 0, tuning_value = -1, range = 0;
87 struct mmc_host *mmc = host->mmc;
89 clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING);
90 clock_setting &= ~0x3fff;
97 clock_setting | phase,
98 SDHCI_CLK_DELAY_SETTING);
100 if (!mmc_send_tuning(mmc)) {
101 /* Tuning is successful at this tuning point */
103 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
104 mmc_hostname(mmc), phase);
109 if (phase == (SIRF_TUNING_COUNT - 1)
110 && range > longest_range)
111 tuning_value = (start + end) / 2;
113 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n",
114 mmc_hostname(mmc), phase);
115 if (range > longest_range) {
116 tuning_value = (start + end) / 2;
117 longest_range = range;
122 } while (++phase < SIRF_TUNING_COUNT);
124 if (tuned_phase_cnt && tuning_value > 0) {
126 * Finally set the selected phase in delay
129 phase = tuning_value;
131 clock_setting | phase,
132 SDHCI_CLK_DELAY_SETTING);
134 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
135 mmc_hostname(mmc), phase);
137 if (--tuning_seq_cnt)
140 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
148 static struct sdhci_ops sdhci_sirf_ops = {
149 .read_l = sdhci_sirf_readl_le,
150 .read_w = sdhci_sirf_readw_le,
151 .platform_execute_tuning = sdhci_sirf_execute_tuning,
152 .set_clock = sdhci_set_clock,
153 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
154 .set_bus_width = sdhci_sirf_set_bus_width,
155 .reset = sdhci_reset,
156 .set_uhs_signaling = sdhci_set_uhs_signaling,
159 static struct sdhci_pltfm_data sdhci_sirf_pdata = {
160 .ops = &sdhci_sirf_ops,
161 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
162 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
163 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
164 SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
165 SDHCI_QUIRK_DELAY_AFTER_POWER,
168 static int sdhci_sirf_probe(struct platform_device *pdev)
170 struct sdhci_host *host;
171 struct sdhci_pltfm_host *pltfm_host;
172 struct sdhci_sirf_priv *priv;
177 clk = devm_clk_get(&pdev->dev, NULL);
179 dev_err(&pdev->dev, "unable to get clock");
183 if (pdev->dev.of_node)
184 gpio_cd = of_get_named_gpio(pdev->dev.of_node, "cd-gpios", 0);
188 host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, sizeof(struct sdhci_sirf_priv));
190 return PTR_ERR(host);
192 pltfm_host = sdhci_priv(host);
193 pltfm_host->clk = clk;
194 priv = sdhci_pltfm_priv(pltfm_host);
195 priv->gpio_cd = gpio_cd;
197 sdhci_get_of_property(pdev);
199 ret = clk_prepare_enable(pltfm_host->clk);
201 goto err_clk_prepare;
203 ret = sdhci_add_host(host);
208 * We must request the IRQ after sdhci_add_host(), as the tasklet only
209 * gets setup in sdhci_add_host() and we oops.
211 if (gpio_is_valid(priv->gpio_cd)) {
212 ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd, 0);
214 dev_err(&pdev->dev, "card detect irq request failed: %d\n",
218 mmc_gpiod_request_cd_irq(host->mmc);
224 sdhci_remove_host(host, 0);
226 clk_disable_unprepare(pltfm_host->clk);
228 sdhci_pltfm_free(pdev);
232 #ifdef CONFIG_PM_SLEEP
233 static int sdhci_sirf_suspend(struct device *dev)
235 struct sdhci_host *host = dev_get_drvdata(dev);
236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
239 ret = sdhci_suspend_host(host);
243 clk_disable(pltfm_host->clk);
248 static int sdhci_sirf_resume(struct device *dev)
250 struct sdhci_host *host = dev_get_drvdata(dev);
251 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
254 ret = clk_enable(pltfm_host->clk);
256 dev_dbg(dev, "Resume: Error enabling clock\n");
260 return sdhci_resume_host(host);
263 static SIMPLE_DEV_PM_OPS(sdhci_sirf_pm_ops, sdhci_sirf_suspend, sdhci_sirf_resume);
266 static const struct of_device_id sdhci_sirf_of_match[] = {
267 { .compatible = "sirf,prima2-sdhc" },
270 MODULE_DEVICE_TABLE(of, sdhci_sirf_of_match);
272 static struct platform_driver sdhci_sirf_driver = {
274 .name = "sdhci-sirf",
275 .of_match_table = sdhci_sirf_of_match,
276 #ifdef CONFIG_PM_SLEEP
277 .pm = &sdhci_sirf_pm_ops,
280 .probe = sdhci_sirf_probe,
281 .remove = sdhci_pltfm_unregister,
284 module_platform_driver(sdhci_sirf_driver);
286 MODULE_DESCRIPTION("SDHCI driver for SiRFprimaII/SiRFmarco");
287 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
288 MODULE_LICENSE("GPL v2");